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https://github.com/Rockbox/rockbox.git
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Ingenic Jz4740:
* Add initial RoLo support * Don't enable IRAM in plugins for now * Initial try at getting PCM working (doesn't crash anymore at least) * Replace hard-coded constant with #define in usb-jz4740 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20115 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
935fad7fd1
commit
38436038a9
12 changed files with 137 additions and 36 deletions
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@ -12,10 +12,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o)
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#define STUBOFFSET 0
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#endif
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#define PLUGINSIZE PLUGIN_BUFFER_SIZE
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#define CODECSIZE CODEC_SIZE
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#define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE)
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE
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#define DRAMORIG 0x80004000
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#define IRAMORIG 0x80000000
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@ -25,7 +22,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o)
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#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
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/* Where the codec buffer ends, and the plugin buffer starts */
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#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
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#define ENDADDR (ENDAUDIOADDR + CODEC_SIZE)
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MEMORY
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{
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@ -77,7 +77,7 @@ static void i2s_codec_init(void)
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i2s_codec_reset();
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//REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
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REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48)
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REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_44)
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| ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6));
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REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST);
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@ -98,7 +98,7 @@ static void i2s_codec_init(void)
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REG_ICDC_CDCCR2 |= 3;
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HP_on_off_flag = 0; /* HP is off */
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HP_on_off_flag = 1; /* HP is on */
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}
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static void i2s_codec_set_mic(unsigned short v) /* 0 <= v <= 100 */
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@ -208,37 +208,36 @@ static void i2s_codec_set_samplerate(unsigned short rate)
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switch (rate)
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{
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case 8000:
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speed = 0;
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speed = 0 << 8;
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break;
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case 11025:
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speed = 1;
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speed = 1 << 8;
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break;
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case 12000:
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speed = 2;
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speed = 2 << 8;
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break;
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case 16000:
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speed = 3;
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speed = 3 << 8;
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break;
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case 22050:
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speed = 4;
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speed = 4 << 8;
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break;
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case 24000:
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speed = 5;
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speed = 5 << 8;
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break;
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case 32000:
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speed = 6;
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speed = 6 << 8;
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break;
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case 44100:
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speed = 7;
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speed = 7 << 8;
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break;
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case 48000:
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speed = 8;
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speed = 8 << 8;
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break;
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default:
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break;
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}
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REG_ICDC_CDCCR2 |= 0x00000f00;
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speed = speed << 8;
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speed |= 0xfffff0ff;
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REG_ICDC_CDCCR2 &= speed;
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@ -327,3 +326,8 @@ void audiohw_init(void)
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{
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i2s_codec_init();
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}
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void audiohw_set_frequency(int freq)
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{
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i2s_codec_set_samplerate(freq);
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}
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@ -32,13 +32,17 @@
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** Playback DMA transfer
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**/
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static bool playback_started = false;
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static void* playback_address;
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void pcm_postinit(void)
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{
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audiohw_postinit();
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/* playback sample:16 bits, burst:16 bytes */
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__i2s_set_transmit_trigger(4);
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/* playback sample: 16 bits burst: 16 bytes */
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__i2s_set_iss_sample_size(16);
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__i2s_set_oss_sample_size(16);
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__i2s_set_transmit_trigger(16 - 4);
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__i2s_set_receive_trigger(4);
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}
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void pcm_play_dma_init(void)
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@ -54,15 +58,24 @@ void pcm_play_dma_init(void)
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void pcm_dma_apply_settings(void)
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{
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/* TODO */
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audiohw_set_frequency(pcm_fsel);
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}
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static void play_start_pcm(void)
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{
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/* Prefill FIFO */
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REG_AIC_DR = 0;
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REG_AIC_DR = 0;
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REG_AIC_DR = 0;
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REG_AIC_DR = 0;
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__i2s_enable_transmit_dma();
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__i2s_enable_replay();
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
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REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) |= DMAC_DCMD_TIE;
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playback_started = true;
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}
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static void play_stop_pcm(void)
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@ -73,22 +86,52 @@ static void play_stop_pcm(void)
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__i2s_disable_transmit_dma();
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__i2s_disable_replay();
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playback_started = false;
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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dma_enable();
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__dcache_writeback_all();
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES;
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REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr);
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REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);
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REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size;
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REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
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REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32);
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REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_16);
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playback_address = (void*)addr;
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play_start_pcm();
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}
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static void play_dma_callback(void)
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{
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unsigned char *start;
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size_t size = 0;
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pcm_callback_for_more(&start, &size);
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if(size != 0)
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{
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__dcache_writeback_all();
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES;
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REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)start);
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REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);
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REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size;
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REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
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REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_16);
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
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REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) |= DMAC_DCMD_TIE;
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return;
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}
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/* Error, callback missing or no more DMA to do */
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pcm_play_dma_stop();
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pcm_play_dma_stopped_callback();
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}
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void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void)
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{
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if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_AR)
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@ -101,21 +144,31 @@ void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void)
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{
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~(DMAC_DCCSR_TT | DMAC_DCCSR_HLT);
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REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_EN;
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__aic_disable_transmit_dma();
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play_dma_callback();
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}
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL);
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if(playback_started)
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return REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) & ~3;
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else
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return 0;
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}
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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/* TODO */
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//*count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL)>>2;
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*count = 0;
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return NULL;
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if(playback_started)
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{
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*count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL);
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return (void*)(playback_address + ((REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) + 2) & ~3));
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}
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else
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{
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*count = 0;
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return NULL;
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}
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}
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void pcm_play_dma_stop(void)
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@ -281,7 +281,7 @@ void dma_enable(void)
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REG_DMAC_DCCSR(4) = 0;
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REG_DMAC_DCCSR(5) = 0;
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REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE);
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REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE);
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}
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}
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@ -730,7 +730,7 @@ int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
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{
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//dma_cache_wback_inv((unsigned long)ptr, length);
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__dcache_writeback_all();
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REG_USB_REG_ADDR1 = (unsigned long)ptr & 0x7fffffff;
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REG_USB_REG_ADDR1 = PHYSADDR((unsigned long)ptr);
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REG_USB_REG_COUNT1 = length;
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REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
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USB_CNTL_DIR_IN | USB_CNTL_ENA |
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@ -780,7 +780,7 @@ int usb_drv_recv(int endpoint, void* ptr, int length)
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{
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//dma_cache_wback_inv((unsigned long)ptr, length);
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__dcache_writeback_all();
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REG_USB_REG_ADDR2 = (unsigned long)ptr & 0x7fffffff;
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REG_USB_REG_ADDR2 = PHYSADDR((unsigned long)ptr);
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REG_USB_REG_COUNT2 = length;
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REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
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USB_CNTL_ENA | USB_CNTL_EP(endpoint) |
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