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s5l87xx: Use pointer arithmetic in register address calculation
This allows to reuse a register definition across similar SoCs that have the same layout of registers (same offsets), but are using a different base address for the peripheral. The include guard was also fixed to reflect the new file name of the header. Some registers were renamed in order to match the datasheet and for consistency with the other register numbering. Change-Id: I0192e227a3c467504b8fcd1eb684a7fc861f7896
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18fdb41b2c
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375a6bc9b1
7 changed files with 872 additions and 888 deletions
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@ -381,7 +381,7 @@ static void s5l_clickwheel_init(void)
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PDAT10 &= ~2;
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PDAT10 &= ~2;
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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clockgate_enable(CLOCKGATE_CWHEEL, true);
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clockgate_enable(CLOCKGATE_CWHEEL, true);
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PCONE = (PCONE & ~0x00ffff00) | 0x00222200;
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PCON14 = (PCON14 & ~0x00ffff00) | 0x00222200;
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WHEEL00 = 0; /* stop s5l8702 controller */
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WHEEL00 = 0; /* stop s5l8702 controller */
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WHEELINT = 7;
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WHEELINT = 7;
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WHEEL10 = 1;
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WHEEL10 = 1;
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@ -420,7 +420,7 @@ bool headphones_inserted(void)
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#if CONFIG_CPU==S5L8701
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#if CONFIG_CPU==S5L8701
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return ((PDAT14 & (1 << 5)) != 0);
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return ((PDAT14 & (1 << 5)) != 0);
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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return ((PDATA & (1 << 6)) != 0);
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return ((PDAT10 & (1 << 6)) != 0);
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#endif
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#endif
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}
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}
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#endif
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#endif
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@ -455,7 +455,7 @@ int button_read_device(void)
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PWRCONEXT |= 1;
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PWRCONEXT |= 1;
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
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WHEEL00 = 0;
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WHEEL00 = 0;
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PCONE = (PCONE & ~0x00ffff00) | 0x000e0e00;
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PCON14 = (PCON14 & ~0x00ffff00) | 0x000e0e00;
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clockgate_enable(CLOCKGATE_CWHEEL, false);
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clockgate_enable(CLOCKGATE_CWHEEL, false);
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#endif
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#endif
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}
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}
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@ -72,7 +72,7 @@ void power_init(void)
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* is not present or it is insufficient or limited,
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* is not present or it is insufficient or limited,
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* additional required power is drained from battery.
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* additional required power is drained from battery.
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*/
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*/
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PCONB = (PCONB & 0x000000ff)
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PCON11 = (PCON11 & 0x000000ff)
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| (0xe << 8) /* route D+ to ADC2: off */
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| (0xe << 8) /* route D+ to ADC2: off */
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| (0xe << 12) /* route D- to ADC2: off */
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| (0xe << 12) /* route D- to ADC2: off */
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| (0x0 << 16) /* USB related input, POL pin ??? */
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| (0x0 << 16) /* USB related input, POL pin ??? */
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@ -80,7 +80,7 @@ void power_init(void)
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| (0xe << 24) /* HPWR: 100mA */
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| (0xe << 24) /* HPWR: 100mA */
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| (0xe << 28); /* USB suspend: off */
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| (0xe << 28); /* USB suspend: off */
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PCONC = (PCONC & 0xffff0000)
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PCON12 = (PCON12 & 0xffff0000)
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| (0xe << 0) /* double HPWR limit: off */
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| (0xe << 0) /* double HPWR limit: off */
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| (0xe << 4) /* disable battery charge: off */
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| (0xe << 4) /* disable battery charge: off */
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| (0xe << 8) /* disable battery charge: off */
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| (0xe << 8) /* disable battery charge: off */
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@ -678,11 +678,11 @@ static int ata_power_up(void)
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*((uint32_t volatile*)0x3cf0010c) = 0xff;
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*((uint32_t volatile*)0x3cf0010c) = 0xff;
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SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
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SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
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| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
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| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
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SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
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SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260);
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*((uint32_t volatile*)0x3cf00200) = 0xb000f;
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*((uint32_t volatile*)0x3cf00200) = 0xb000f;
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SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
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SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
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PASS_RC(mmc_init(), 3, 0);
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PASS_RC(mmc_init(), 3, 0);
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SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
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SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4);
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sleep(HZ / 100);
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sleep(HZ / 100);
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PASS_RC(ceata_init(8), 3, 1);
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PASS_RC(ceata_init(8), 3, 1);
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PASS_RC(ata_identify(identify_info), 3, 2);
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PASS_RC(ata_identify(identify_info), 3, 2);
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@ -51,8 +51,8 @@ void spi_init(int port, bool state)
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PCON6 = (PCON6 & ~0xffff0000) | (val << 16);
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PCON6 = (PCON6 & ~0xffff0000) | (val << 16);
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break;
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break;
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case 2:
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case 2:
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PCONE = (PCONE & ~0xff000000) | (val << 24);
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PCON14 = (PCON14 & ~0xff000000) | (val << 24);
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PCONF = (PCONF & ~0xff) | (val >> 8);
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PCON15 = (PCON15 & ~0xff) | (val >> 8);
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break;
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break;
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}
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}
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}
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}
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@ -157,9 +157,10 @@ void irq_handler(void)
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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void* dummy = VIC0ADDRESS;
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const void* dummy0 = VIC0ADDRESS;
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dummy = VIC1ADDRESS;
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(void)dummy0;
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(void)dummy;
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const void* dummy1 = VIC1ADDRESS;
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(void)dummy1;
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uint32_t irqs0 = VIC0IRQSTATUS;
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uint32_t irqs0 = VIC0IRQSTATUS;
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uint32_t irqs1 = VIC1IRQSTATUS;
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uint32_t irqs1 = VIC1IRQSTATUS;
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for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)
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for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)
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@ -55,7 +55,7 @@ void uart_target_enable_gpio(int uart_id, int port_id)
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break;
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break;
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case 1:
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case 1:
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/* configure UART1 GPIO ports, including RTS/CTS signals */
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/* configure UART1 GPIO ports, including RTS/CTS signals */
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PCOND = (PCOND & 0xff0000ff) | 0x00222200;
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PCON13 = (PCON13 & 0xff0000ff) | 0x00222200;
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break;
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break;
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case 2:
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case 2:
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case 3:
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case 3:
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@ -74,7 +74,7 @@ void uart_target_disable_gpio(int uart_id, int port_id)
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PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000;
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PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000;
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break;
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break;
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case 1:
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case 1:
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PCOND = (PCOND & 0xff0000ff) | 0x00eeee00;
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PCON13 = (PCON13 & 0xff0000ff) | 0x00eeee00;
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break;
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break;
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case 2:
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case 2:
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case 3:
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case 3:
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