s5l87xx: Use pointer arithmetic in register address calculation

This allows to reuse a register definition across similar SoCs that have the same layout of registers (same offsets), but are using a different base address for the peripheral. The include guard was also fixed to reflect the new file name of the header.

Some registers were renamed in order to match the datasheet and for consistency with the other register numbering.

Change-Id: I0192e227a3c467504b8fcd1eb684a7fc861f7896
This commit is contained in:
Vencislav Atanasov 2024-11-24 01:10:11 +02:00 committed by Solomon Peachy
parent 18fdb41b2c
commit 375a6bc9b1
7 changed files with 872 additions and 888 deletions

File diff suppressed because it is too large Load diff

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@ -381,7 +381,7 @@ static void s5l_clickwheel_init(void)
PDAT10 &= ~2; PDAT10 &= ~2;
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
clockgate_enable(CLOCKGATE_CWHEEL, true); clockgate_enable(CLOCKGATE_CWHEEL, true);
PCONE = (PCONE & ~0x00ffff00) | 0x00222200; PCON14 = (PCON14 & ~0x00ffff00) | 0x00222200;
WHEEL00 = 0; /* stop s5l8702 controller */ WHEEL00 = 0; /* stop s5l8702 controller */
WHEELINT = 7; WHEELINT = 7;
WHEEL10 = 1; WHEEL10 = 1;
@ -420,7 +420,7 @@ bool headphones_inserted(void)
#if CONFIG_CPU==S5L8701 #if CONFIG_CPU==S5L8701
return ((PDAT14 & (1 << 5)) != 0); return ((PDAT14 & (1 << 5)) != 0);
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
return ((PDATA & (1 << 6)) != 0); return ((PDAT10 & (1 << 6)) != 0);
#endif #endif
} }
#endif #endif
@ -455,7 +455,7 @@ int button_read_device(void)
PWRCONEXT |= 1; PWRCONEXT |= 1;
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
WHEEL00 = 0; WHEEL00 = 0;
PCONE = (PCONE & ~0x00ffff00) | 0x000e0e00; PCON14 = (PCON14 & ~0x00ffff00) | 0x000e0e00;
clockgate_enable(CLOCKGATE_CWHEEL, false); clockgate_enable(CLOCKGATE_CWHEEL, false);
#endif #endif
} }

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@ -72,7 +72,7 @@ void power_init(void)
* is not present or it is insufficient or limited, * is not present or it is insufficient or limited,
* additional required power is drained from battery. * additional required power is drained from battery.
*/ */
PCONB = (PCONB & 0x000000ff) PCON11 = (PCON11 & 0x000000ff)
| (0xe << 8) /* route D+ to ADC2: off */ | (0xe << 8) /* route D+ to ADC2: off */
| (0xe << 12) /* route D- to ADC2: off */ | (0xe << 12) /* route D- to ADC2: off */
| (0x0 << 16) /* USB related input, POL pin ??? */ | (0x0 << 16) /* USB related input, POL pin ??? */
@ -80,7 +80,7 @@ void power_init(void)
| (0xe << 24) /* HPWR: 100mA */ | (0xe << 24) /* HPWR: 100mA */
| (0xe << 28); /* USB suspend: off */ | (0xe << 28); /* USB suspend: off */
PCONC = (PCONC & 0xffff0000) PCON12 = (PCON12 & 0xffff0000)
| (0xe << 0) /* double HPWR limit: off */ | (0xe << 0) /* double HPWR limit: off */
| (0xe << 4) /* disable battery charge: off */ | (0xe << 4) /* disable battery charge: off */
| (0xe << 8) /* disable battery charge: off */ | (0xe << 8) /* disable battery charge: off */

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@ -678,11 +678,11 @@ static int ata_power_up(void)
*((uint32_t volatile*)0x3cf0010c) = 0xff; *((uint32_t volatile*)0x3cf0010c) = 0xff;
SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14; | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
SDCI_CDIV = SDCI_CDIV_CLKDIV(260); SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260);
*((uint32_t volatile*)0x3cf00200) = 0xb000f; *((uint32_t volatile*)0x3cf00200) = 0xb000f;
SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT; SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
PASS_RC(mmc_init(), 3, 0); PASS_RC(mmc_init(), 3, 0);
SDCI_CDIV = SDCI_CDIV_CLKDIV(4); SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4);
sleep(HZ / 100); sleep(HZ / 100);
PASS_RC(ceata_init(8), 3, 1); PASS_RC(ceata_init(8), 3, 1);
PASS_RC(ata_identify(identify_info), 3, 2); PASS_RC(ata_identify(identify_info), 3, 2);

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@ -51,8 +51,8 @@ void spi_init(int port, bool state)
PCON6 = (PCON6 & ~0xffff0000) | (val << 16); PCON6 = (PCON6 & ~0xffff0000) | (val << 16);
break; break;
case 2: case 2:
PCONE = (PCONE & ~0xff000000) | (val << 24); PCON14 = (PCON14 & ~0xff000000) | (val << 24);
PCONF = (PCONF & ~0xff) | (val >> 8); PCON15 = (PCON15 & ~0xff) | (val >> 8);
break; break;
} }
} }

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@ -157,9 +157,10 @@ void irq_handler(void)
asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
"sub sp, sp, #8 \n"); /* Reserve stack */ "sub sp, sp, #8 \n"); /* Reserve stack */
void* dummy = VIC0ADDRESS; const void* dummy0 = VIC0ADDRESS;
dummy = VIC1ADDRESS; (void)dummy0;
(void)dummy; const void* dummy1 = VIC1ADDRESS;
(void)dummy1;
uint32_t irqs0 = VIC0IRQSTATUS; uint32_t irqs0 = VIC0IRQSTATUS;
uint32_t irqs1 = VIC1IRQSTATUS; uint32_t irqs1 = VIC1IRQSTATUS;
for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1) for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)

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@ -55,7 +55,7 @@ void uart_target_enable_gpio(int uart_id, int port_id)
break; break;
case 1: case 1:
/* configure UART1 GPIO ports, including RTS/CTS signals */ /* configure UART1 GPIO ports, including RTS/CTS signals */
PCOND = (PCOND & 0xff0000ff) | 0x00222200; PCON13 = (PCON13 & 0xff0000ff) | 0x00222200;
break; break;
case 2: case 2:
case 3: case 3:
@ -74,7 +74,7 @@ void uart_target_disable_gpio(int uart_id, int port_id)
PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000; PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000;
break; break;
case 1: case 1:
PCOND = (PCOND & 0xff0000ff) | 0x00eeee00; PCON13 = (PCON13 & 0xff0000ff) | 0x00eeee00;
break; break;
case 2: case 2:
case 3: case 3: