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Reenable scaling on Sansa since a reasonable solution to clicks has been found.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13995 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2007-07-26 10:46:17 +00:00
parent 414dd752eb
commit 31cf7e95b4
5 changed files with 44 additions and 3 deletions
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2
firmware/export/config-e200.h
View file

@ -160,7 +160,7 @@
#define CONFIG_LED LED_VIRTUAL #define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */ /* Define this if you have adjustable CPU frequency */
/*#define HAVE_ADJUSTABLE_CPU_FREQ*/ #define HAVE_ADJUSTABLE_CPU_FREQ
#define MI4_FORMAT #define MI4_FORMAT
#define BOOTFILE_EXT "mi4" #define BOOTFILE_EXT "mi4"

1
firmware/export/i2s.h
View file

@ -18,3 +18,4 @@
****************************************************************************/ ****************************************************************************/
void i2s_reset(void); void i2s_reset(void);
void i2s_scale_attn_level(long frequency);

31
firmware/target/arm/i2s-pp.c
View file

@ -25,6 +25,7 @@
****************************************************************************/ ****************************************************************************/
#include "system.h" #include "system.h"
#include "cpu.h"
/* TODO: Add in PP5002 defs */ /* TODO: Add in PP5002 defs */
#if CONFIG_CPU == PP5002 #if CONFIG_CPU == PP5002
@ -140,4 +141,34 @@ void i2s_reset(void)
/* Rx.CLR = 1, TX.CLR = 1 */ /* Rx.CLR = 1, TX.CLR = 1 */
IISFIFO_CFG |= 0x1100; IISFIFO_CFG |= 0x1100;
} }
#ifdef SANSA_E200
void i2s_scale_attn_level(long frequency)
{
unsigned int iisfifo_cfg = IISFIFO_CFG & ~0xff;
/* TODO: set this more appropriately for frequency */
if (frequency <= CPUFREQ_DEFAULT)
{
/* when 4 slots full */
/* when 4 slots empty */
iisfifo_cfg |= 0x11;
}
else if (frequency < CPUFREQ_MAX)
{
/* when 8 slots full */
/* when 8 slots empty */
iisfifo_cfg |= 0x22;
}
else
{
/* when 12 slots full */
/* when 12 slots empty */
iisfifo_cfg |= 0x33;
}
IISFIFO_CFG = iisfifo_cfg;
}
#endif /* SANSA_E200 */
#endif #endif

4
firmware/target/arm/pcm-pp.c
View file

@ -378,7 +378,7 @@ void fiq_record(void)
if (audio_channels == 2) { if (audio_channels == 2) {
/* RX is stereo */ /* RX is stereo */
while (p_size > 0) { while (p_size > 0) {
if (FIFO_FREE_COUNT < 8) { if (FIFO_FREE_COUNT < 2) {
/* enable interrupt */ /* enable interrupt */
IISCONFIG |= (1 << 0); IISCONFIG |= (1 << 0);
goto fiq_record_exit; goto fiq_record_exit;
@ -402,7 +402,7 @@ void fiq_record(void)
else { else {
/* RX is left channel mono */ /* RX is left channel mono */
while (p_size > 0) { while (p_size > 0) {
if (FIFO_FREE_COUNT < 8) { if (FIFO_FREE_COUNT < 2) {
/* enable interrupt */ /* enable interrupt */
IISCONFIG |= (1 << 0); IISCONFIG |= (1 << 0);
goto fiq_record_exit; goto fiq_record_exit;

9
firmware/target/arm/system-pp502x.c
View file

@ -18,6 +18,7 @@
****************************************************************************/ ****************************************************************************/
#include "system.h" #include "system.h"
#include "thread.h" #include "thread.h"
#include "i2s.h"
#if NUM_CORES > 1 #if NUM_CORES > 1
struct mutex boostctrl_mtx NOCACHEBSS_ATTR; struct mutex boostctrl_mtx NOCACHEBSS_ATTR;
@ -165,6 +166,10 @@ void set_cpu_frequency(long frequency)
postmult = CPUFREQ_DEFAULT_MULT; postmult = CPUFREQ_DEFAULT_MULT;
cpu_frequency = frequency; cpu_frequency = frequency;
#ifdef SANSA_E200
i2s_scale_attn_level(CPUFREQ_DEFAULT);
#endif
unknown2 = inl(0x600060a0); unknown2 = inl(0x600060a0);
outl(inl(0x70000020) | (1<<30), 0x70000020); /* Enable PLL power */ outl(inl(0x70000020) | (1<<30), 0x70000020); /* Enable PLL power */
@ -197,6 +202,10 @@ void set_cpu_frequency(long frequency)
inl(0x600060a0); /* sync pipeline (?) */ inl(0x600060a0); /* sync pipeline (?) */
outl(unknown2, 0x600060a0); outl(unknown2, 0x600060a0);
#ifdef SANSA_E200
i2s_scale_attn_level(frequency);
#endif
# if NUM_CORES > 1 # if NUM_CORES > 1
boostctrl_mtx.locked = 0; boostctrl_mtx.locked = 0;
# endif # endif