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Gigabeat S: Allow recording from FM. Give FM the same volume range as playback. NOTE: This bumps the si4700 output volume to -0dB so other players with that may need a minor adjustment.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19619 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
9ac7af749b
commit
2e99b3d931
10 changed files with 454 additions and 166 deletions
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@ -18,39 +18,55 @@
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "wm8978.h"
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#include "config.h"
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#include "system.h"
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#include "audiohw.h"
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#include "audio.h"
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/* Set the audio source for IIS TX */
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void audio_set_output_source(int source)
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{
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(void)source; /* TODO */
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switch (source)
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{
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default:
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case AUDIO_SRC_PLAYBACK:
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/* Receive data from PORT1 (SSI1) */
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AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT1;
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/* wmc_clear(WMC_COMPANDING_CTRL, WMC_LOOPBACK); */
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break;
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case AUDIO_SRC_FMRADIO:
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/* External source - receive data from self (loopback to TX) */
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AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT4;
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/* wmc_set(WMC_COMPANDING_CTRL, WMC_LOOPBACK); */
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break;
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}
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}
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void audio_input_mux(int source, unsigned int flags)
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{
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(void)flags;
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/* Prevent pops from unneeded switching */
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static int last_source = AUDIO_SRC_PLAYBACK;
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bool recording = flags & SRCF_RECORDING;
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static bool last_recording = false;
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switch (source)
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{
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case AUDIO_SRC_PLAYBACK:
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/* deselect bypass patths and set volume to -15dB */
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wmc_clear(WMC_LEFT_MIXER_CTRL, (WMC_BYPL2LMIX) | (7<<2));
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wmc_clear(WMC_RIGHT_MIXER_CTRL, (WMC_BYPR2RMIX) | (7<<2));
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/* disable L2/R2 inputs and boost stage */
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wmc_clear(WMC_POWER_MANAGEMENT2,
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WMC_INPPGAENR | WMC_INPPGAENL | WMC_BOOSTENL | WMC_BOOSTENR);
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break;
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case AUDIO_SRC_FMRADIO:
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/* enable L2/R2 inputs and boost stage */
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wmc_set(WMC_POWER_MANAGEMENT2,
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WMC_INPPGAENR | WMC_INPPGAENL | WMC_BOOSTENL | WMC_BOOSTENR);
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/* select bypass patths and set volume to 0dB */
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wmc_set(WMC_LEFT_MIXER_CTRL, (WMC_BYPL2LMIX) | (5<<2));
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wmc_set(WMC_RIGHT_MIXER_CTRL, (WMC_BYPR2RMIX) | (5<<2));
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break;
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default:
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source = AUDIO_SRC_PLAYBACK;
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/* Fallthrough */
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case AUDIO_SRC_PLAYBACK: /* playback - no recording */
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if (source != last_source)
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audiohw_set_recsrc(AUDIO_SRC_PLAYBACK, false);
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break;
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case AUDIO_SRC_FMRADIO: /* recording and playback */
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if (source != last_source || recording != last_recording)
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audiohw_set_recsrc(AUDIO_SRC_FMRADIO, recording);
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break;
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}
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last_source = source;
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last_recording = recording;
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}
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@ -111,17 +111,12 @@ void pcm_play_dma_init(void)
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SSI_SCR2 &= ~SSI_SCR_SSIEN;
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SSI_SCR1 &= ~SSI_SCR_SSIEN;
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SSI_SIER1 = SSI_SIER_TFE0;
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SSI_SIER2 = 0;
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/* Set up audio mux */
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/* Port 1 (internally connected to SSI1)
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* All clocking is output sourced from port 4 */
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AUDMUX_PTCR1 = AUDMUX_PTCR_TFS_DIR | AUDMUX_PTCR_TFSEL_PORT4 |
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AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT4 |
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AUDMUX_PTCR_RFSDIR | AUDMUX_PTCR_RFSSEL_PORT4 |
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AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4 |
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AUDMUX_PTCR_SYN;
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/* Receive data from port 4 */
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@ -133,18 +128,22 @@ void pcm_play_dma_init(void)
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/* Receive data from port 1 */
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AUDMUX_PDCR4 = AUDMUX_PDCR_RXDSEL_PORT1;
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/* Port 2 (internally connected to SSI2) routes clocking to port 5 to
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/* PORT2 (internally connected to SSI2) routes clocking to PORT5 to
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* provide MCLK to the codec */
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/* All port 2 clocks are inputs taken from SSI2 */
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AUDMUX_PTCR2 = 0;
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AUDMUX_PDCR2 = 0;
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/* Port 5 outputs TCLK sourced from port 2 */
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/* TX clocks are inputs taken from SSI2 */
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/* RX clocks are outputs taken from PORT4 */
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AUDMUX_PTCR2 = AUDMUX_PTCR_RFS_DIR | AUDMUX_PTCR_RFSSEL_PORT4 |
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AUDMUX_PTCR_RCLKDIR | AUDMUX_PTCR_RCSEL_PORT4;
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/* RX data taken from PORT4 */
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AUDMUX_PDCR2 = AUDMUX_PDCR_RXDSEL_PORT4;
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/* PORT5 outputs TCLK sourced from PORT2 (SSI2) */
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AUDMUX_PTCR5 = AUDMUX_PTCR_TCLKDIR | AUDMUX_PTCR_TCSEL_PORT2;
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AUDMUX_PDCR5 = 0;
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/* Setup SSIs */
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/* SSI1 - interface for all I2S data */
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/* SSI1 - SoC software interface for all I2S data out */
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SSI_SCR1 = SSI_SCR_SYN | SSI_SCR_I2S_MODE_SLAVE;
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SSI_STCR1 = SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
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SSI_STCR_TEFS | SSI_STCR_TFEN0;
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@ -153,26 +152,11 @@ void pcm_play_dma_init(void)
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SSI_STCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
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SSI_STRCCR_PMw(4-1);
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/* Transmit low watermark - 2 samples in FIFO */
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SSI_SFCSR1 = SSI_SFCSR_TFWM1w(1) | SSI_SFCSR_TFWM0w(2);
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SSI_STMSK1 = 0;
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/* Receive */
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SSI_SRCR1 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI |
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SSI_SRCR_REFS | SSI_SRCR_RFEN0;
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/* 16 bits per word, 2 words per frame */
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SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
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SSI_STRCCR_PMw(4-1);
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/* Receive high watermark - 6 samples in FIFO
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* Transmit low watermark - 2 samples in FIFO */
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SSI_SFCSR1 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_TFWM1w(1) |
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SSI_SFCSR_RFWM0w(6) | SSI_SFCSR_TFWM0w(2);
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SSI_SRMSK1 = 0;
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/* SSI2 - provides MCLK only */
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SSI_SCR2 = 0;
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SSI_SRCR2 = 0;
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/* SSI2 - provides MCLK to codec. Receives data from codec. */
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SSI_STCR2 = SSI_STCR_TXDIR;
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/* f(INT_BIT_CLK) =
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@ -189,6 +173,20 @@ void pcm_play_dma_init(void)
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*/
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SSI_STCCR2 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1);
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/* SSI2 - receive - asynchronous clocks */
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SSI_SCR2 = SSI_SCR_I2S_MODE_SLAVE;
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SSI_SRCR2 = SSI_SRCR_RXBIT0 | SSI_SRCR_RSCKP | SSI_SRCR_RFSI |
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SSI_SRCR_REFS;
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/* 16 bits per word, 2 words per frame */
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SSI_SRCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
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SSI_STRCCR_PMw(4-1);
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/* Receive high watermark - 6 samples in FIFO */
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SSI_SFCSR2 = SSI_SFCSR_RFWM1w(8) | SSI_SFCSR_RFWM0w(6);
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SSI_SRMSK2 = 0;
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/* Enable SSI2 (codec clock) */
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SSI_SCR2 |= SSI_SCR_SSIEN;
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@ -210,7 +208,8 @@ static void play_start_pcm(void)
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dma_play_data.state = 1;
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/* Fill the FIFO or start when data is used up */
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SSI_SCR1 |= SSI_SCR_SSIEN; /* Enable SSI */
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SSI_SCR1 |= SSI_SCR_SSIEN; /* Enable SSI */
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SSI_STCR1 |= SSI_STCR_TFEN0; /* Enable TX FIFO */
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while (1)
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{
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@ -235,6 +234,7 @@ static void play_stop_pcm(void)
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while (SSI_SFCSR_TFCNT0r(SSI_SFCSR1) > 0);
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/* Disable transmission */
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SSI_STCR1 &= ~SSI_STCR_TFEN0;
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SSI_SCR1 &= ~(SSI_SCR_TE | SSI_SCR_SSIEN);
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/* Do not enable interrupt on unlock */
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@ -285,4 +285,113 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
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return (void *)((addr + 2) & ~3);
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}
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/* Any recording functionality should be implemented similarly */
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#ifdef HAVE_RECORDING
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static struct dma_data dma_rec_data =
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{
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/* Initialize to a locked, stopped state */
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.p = NULL,
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.size = 0,
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.locked = 0,
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.state = 0
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};
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static void __attribute__((interrupt("IRQ"))) SSI2_HANDLER(void)
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{
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register pcm_more_callback_type2 more_ready;
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while (dma_rec_data.size > 0)
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{
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if (SSI_SFCSR_RFCNT0r(SSI_SFCSR2) < 2)
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return;
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*dma_rec_data.p++ = SSI_SRX0_2;
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*dma_rec_data.p++ = SSI_SRX0_2;
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dma_rec_data.size -= 4;
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}
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more_ready = pcm_callback_more_ready;
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if (more_ready == NULL || more_ready(0) < 0) {
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/* Finished recording */
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pcm_rec_dma_stop();
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pcm_rec_dma_stopped_callback();
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}
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}
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void pcm_rec_lock(void)
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{
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if (++dma_rec_data.locked == 1)
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{
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/* Atomically disable receive interrupt */
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imx31_regclr32(&SSI_SIER2, SSI_SIER_RIE);
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}
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}
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void pcm_rec_unlock(void)
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{
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if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0)
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{
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/* Atomically enable receive interrupt */
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imx31_regset32(&SSI_SIER2, SSI_SIER_RIE);
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}
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}
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void pcm_record_more(void *start, size_t size)
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{
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pcm_rec_peak_addr = start; /* Start peaking at dest */
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dma_rec_data.p = start; /* Start of RX buffer */
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dma_rec_data.size = size; /* Bytes to transfer */
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}
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void pcm_rec_dma_stop(void)
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{
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/* Stop receiving data */
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SSI_SCR2 &= ~SSI_SCR_RE; /* Disable RX */
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SSI_SRCR2 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */
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dma_rec_data.state = 0;
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avic_disable_int(SSI2);
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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pcm_rec_dma_stop();
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pcm_rec_peak_addr = addr;
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dma_rec_data.p = addr;
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dma_rec_data.size = size;
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dma_rec_data.state = 1;
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avic_enable_int(SSI2, IRQ, 9, SSI2_HANDLER);
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SSI_SRCR2 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */
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/* Ensure clear FIFO */
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while (SSI_SFCSR2 & SSI_SFCSR_RFCNT0)
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SSI_SRX0_2;
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/* Enable receive */
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SSI_SCR2 |= SSI_SCR_RE;
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}
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void pcm_rec_dma_close(void)
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{
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pcm_rec_dma_stop();
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}
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void pcm_rec_dma_init(void)
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{
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pcm_rec_dma_stop();
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}
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const void * pcm_rec_dma_get_peak_buffer(int *count)
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{
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unsigned long addr = (uint32_t)pcm_rec_peak_addr;
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unsigned long end = (uint32_t)dma_rec_data.p;
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*count = (end >> 2) - (addr >> 2);
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return (void *)(addr & ~3);
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}
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#endif /* HAVE_RECORDING */
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