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Make RoLo work on PP5002. * Rename CACHE_CTL flag values on PP5002 for consistency.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23277 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2009-10-19 21:38:52 +00:00
parent 09de59708d
commit 2dd45f7c6d
4 changed files with 17 additions and 13 deletions
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2
firmware/target/arm/crt0-pp-bl.S
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@ -45,7 +45,7 @@ start:
.equ CPUSLEEPING, 0x8000
.equ COPSLEEPING, 0x4000
.equ CACHE_CTRL, 0xcf004024
.equ CACHE_ENAB, 0x2 /* Actually the CACHE_INIT flag */
.equ CACHE_ENAB, 0x2 /* Actually the CACHE_CTL_INIT flag */
#else
.equ PROC_ID, 0x60000000
.equ CPU_CTRL, 0x60007000

4
firmware/target/arm/system-pp5002.c
View file

@ -97,7 +97,7 @@ static void ipod_init_cache(void)
PROC_STAT &= ~0x700;
outl(0x4000, 0xcf004020);
CACHE_CTL = CACHE_INIT;
CACHE_CTL = CACHE_CTL_INIT;
for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE;
b < e; b += 16) {
@ -113,7 +113,7 @@ static void ipod_init_cache(void)
CACHE_MASK = 0x00001c00;
CACHE_OPERATION = 0x3fc0;
CACHE_CTL = CACHE_INIT | CACHE_RUN;
CACHE_CTL = CACHE_CTL_INIT | CACHE_CTL_RUN;
}
#ifdef HAVE_ADJUSTABLE_CPU_FREQ