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https://github.com/Rockbox/rockbox.git
synced 2025-11-15 08:02:34 -05:00
fuze+: add more clocking code, add dma code, add ssp code, add stub usb code, update storage to SD + MMC, beginning of the driver
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30010 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly
parent
d4800fa385
commit
2cf3313382
15 changed files with 1069 additions and 4 deletions
307
firmware/target/arm/imx233/ssp-imx233.c
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307
firmware/target/arm/imx233/ssp-imx233.c
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by amaury Pouly
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*
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* Based on Rockbox iriver bootloader by Linus Nielsen Feltzing
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* and the ipodlinux bootloader by Daniel Palffy and Bernard Leach
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "ssp-imx233.h"
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#include "clkctrl-imx233.h"
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#include "pinctrl-imx233.h"
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#include "dma-imx233.h"
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/* Used for DMA */
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struct ssp_dma_command_t
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{
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struct apb_dma_command_t dma;
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/* PIO words */
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uint32_t ctrl0;
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uint32_t cmd0;
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uint32_t cmd1;
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};
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static int ssp_in_use = 0;
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static struct mutex ssp_mutex[2];
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static struct semaphore ssp_sema[2];
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static struct ssp_dma_command_t ssp_dma_cmd[2];
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void INT_SSP(int ssp)
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{
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/* reset dma channel on error */
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if(imx233_dma_is_channel_error_irq(APB_SSP(ssp)))
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imx233_dma_reset_channel(APB_SSP(ssp));
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/* clear irq flags */
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imx233_dma_clear_channel_interrupt(APB_SSP(ssp));
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semaphore_release(&ssp_sema[ssp - 1]);
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}
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void INT_SSP1_DMA(void)
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{
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INT_SSP(1);
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}
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void INT_SSP2_DMA(void)
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{
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INT_SSP(2);
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}
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void INT_SSP1_ERROR(void)
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{
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panicf("ssp1 error");
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}
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void INT_SSP2_ERROR(void)
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{
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panicf("ssp2 error");
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}
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void imx233_ssp_init(void)
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{
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/* power down */
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__REG_SET(HW_SSP_CTRL0(1)) = __BLOCK_CLKGATE;
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__REG_SET(HW_SSP_CTRL0(2)) = __BLOCK_CLKGATE;
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ssp_in_use = 0;
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semaphore_init(&ssp_sema[0], 1, 0);
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semaphore_init(&ssp_sema[1], 1, 0);
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mutex_init(&ssp_mutex[0]);
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mutex_init(&ssp_mutex[1]);
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}
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void imx233_ssp_start(int ssp)
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{
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/* Gate block */
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__REG_CLR(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE;
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while(HW_SSP_CTRL0(ssp) & __BLOCK_CLKGATE);
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/* Gate dma channel */
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imx233_dma_clkgate_channel(APB_SSP(ssp), true);
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/* If first block to start, start SSP clock */
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if(ssp_in_use == 0)
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{
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/* fracdiv = 18 => clk_io = pll = 480Mhz
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* intdiv = 4 => clk_ssp = 120Mhz */
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imx233_set_fractional_divisor(CLK_IO, 18);
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imx233_enable_clock(CLK_SSP, false);
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imx233_set_clock_divisor(CLK_SSP, 4);
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imx233_set_bypass_pll(CLK_SSP, false); /* use IO */
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imx233_enable_clock(CLK_SSP, true);
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}
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ssp_in_use++;
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}
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void imx233_ssp_stop(int ssp)
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{
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/* Gate off */
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__REG_SET(HW_SSP_CTRL0(ssp)) = __BLOCK_CLKGATE;
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/* Gate off dma */
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imx233_dma_clkgate_channel(APB_SSP(ssp), false);
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/* If last block to stop, stop SSP clock */
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ssp_in_use--;
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if(ssp_in_use == 0)
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{
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imx233_enable_clock(CLK_SSP, false);
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imx233_set_fractional_divisor(CLK_IO, 0);
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}
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}
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void imx233_ssp_softreset(int ssp)
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{
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imx233_reset_block(&HW_SSP_CTRL0(ssp));
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}
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void imx233_ssp_set_timings(int ssp, int divide, int rate)
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{
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__REG_CLR(HW_SSP_TIMING(ssp)) =
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HW_SSP_TIMING__CLOCK_DIVIDE_BM | HW_SSP_TIMING__CLOCK_RATE_BM;
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__REG_SET(HW_SSP_TIMING(ssp)) =
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divide << HW_SSP_TIMING__CLOCK_DIVIDE_BP | rate;
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}
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void imx233_ssp_set_timeout(int ssp, int timeout)
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{
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__REG_CLR(HW_SSP_TIMING(ssp)) = HW_SSP_TIMING__CLOCK_TIMEOUT_BM;
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__REG_SET(HW_SSP_TIMING(ssp)) =
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timeout << HW_SSP_TIMING__CLOCK_TIMEOUT_BP;
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}
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#if 0
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static void setup_ssp_sd_pins(int ssp)
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{
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imx233_set_pin_function(1, 29, PINCTRL_FUNCTION_GPIO);
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imx233_enable_gpio_output(1, 29, true);
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imx233_set_gpio_output(1, 29, false);
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if(ssp == 1)
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{
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/* SSP_SCK: drive 8mA */
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imx233_set_pin_drive_strength(2, 6, PINCTRL_DRIVE_8mA);
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/* SSP_{SCK,DATA{3,2,1,0},DETECT,CMD} */
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imx233_set_pin_function(2, 6, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 5, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 4, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 3, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 2, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 1, PINCTRL_FUNCTION_MAIN);
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imx233_set_pin_function(2, 0, PINCTRL_FUNCTION_MAIN);
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/* SSP_CMD: pullup */
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imx233_enable_pin_pullup(2, 0, true);
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imx233_enable_pin_pullup(2, 2, true);
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imx233_enable_pin_pullup(2, 3, true);
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imx233_enable_pin_pullup(2, 4, true);
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imx233_enable_pin_pullup(2, 5, true);
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}
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else
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{
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}
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}
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#endif
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void imx233_ssp_setup_ssp2_sd_mmc_pins(bool enable_pullups, unsigned bus_width,
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unsigned drive_strength)
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{
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/* SSP_{CMD,SCK} */
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imx233_set_pin_drive_strength(0, 20, drive_strength);
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imx233_set_pin_drive_strength(0, 24, drive_strength);
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imx233_set_pin_function(0, 20, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 24, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 20, enable_pullups);
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/* SSP_DATA{0-7}*/
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imx233_set_pin_drive_strength(0, 0, drive_strength);
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imx233_set_pin_function(0, 0, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 0, enable_pullups);
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if(bus_width >= 4)
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{
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imx233_set_pin_drive_strength(0, 1, drive_strength);
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imx233_set_pin_drive_strength(0, 2, drive_strength);
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imx233_set_pin_drive_strength(0, 3, drive_strength);
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imx233_set_pin_function(0, 1, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 2, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 3, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 1, enable_pullups);
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imx233_enable_pin_pullup(0, 2, enable_pullups);
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imx233_enable_pin_pullup(0, 3, enable_pullups);
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}
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if(bus_width >= 8)
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{
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imx233_set_pin_drive_strength(0, 4, drive_strength);
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imx233_set_pin_drive_strength(0, 5, drive_strength);
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imx233_set_pin_drive_strength(0, 6, drive_strength);
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imx233_set_pin_drive_strength(0, 7, drive_strength);
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imx233_set_pin_function(0, 4, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 5, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 6, PINCTRL_FUNCTION_ALT2);
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imx233_set_pin_function(0, 7, PINCTRL_FUNCTION_ALT2);
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imx233_enable_pin_pullup(0, 4, enable_pullups);
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imx233_enable_pin_pullup(0, 5, enable_pullups);
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imx233_enable_pin_pullup(0, 6, enable_pullups);
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imx233_enable_pin_pullup(0, 7, enable_pullups);
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}
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imx233_enable_gpio_output_mask(0, 0x11000ff, false);
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imx233_set_gpio_output_mask(0, 0x11000ff, false);
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}
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void imx233_ssp_set_mode(int ssp, unsigned mode)
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{
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switch(mode)
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{
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case HW_SSP_CTRL1__SSP_MODE__SD_MMC:
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/* clear mode and word length */
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__REG_CLR(HW_SSP_CTRL1(ssp)) =
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HW_SSP_CTRL1__SSP_MODE_BM | HW_SSP_CTRL1__WORD_LENGTH_BM;
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/* set mode, set word length to 8-bit, polarity and enable dma */
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__REG_SET(HW_SSP_CTRL1(ssp)) = mode |
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HW_SSP_CTRL1__WORD_LENGTH__EIGHT_BITS << HW_SSP_CTRL1__WORD_LENGTH_BP |
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HW_SSP_CTRL1__POLARITY | HW_SSP_CTRL1__DMA_ENABLE;
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break;
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default: return;
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}
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}
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enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd, uint32_t cmd_arg,
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enum imx233_ssp_resp_t resp, void *buffer, int xfer_size, bool read, uint32_t *resp_ptr)
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{
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mutex_lock(&ssp_mutex[ssp - 1]);
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/* Enable all interrupts */
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imx233_enable_interrupt(INT_SRC_SSP_DMA(ssp), true);
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imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true);
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/* Assume only one block so ignore block_count and block_size */
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ssp_dma_cmd[ssp - 1].cmd0 = cmd | HW_SSP_CMD0__APPEND_8CYC;
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ssp_dma_cmd[ssp - 1].cmd1 = cmd_arg;
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/* setup all flags and run */
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ssp_dma_cmd[ssp - 1].ctrl0 = xfer_size | HW_SSP_CTRL0__ENABLE |
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HW_SSP_CTRL0__IGNORE_CRC |
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(resp != SSP_NO_RESP ? HW_SSP_CTRL0__GET_RESP | HW_SSP_CTRL0__WAIT_FOR_IRQ : 0) |
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(resp == SSP_LONG_RESP ? HW_SSP_CTRL0__LONG_RESP : 0) |
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HW_SSP_CTRL0__BUS_WIDTH__ONE_BIT << HW_SSP_CTRL0__BUS_WIDTH_BP |
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(buffer ? HW_SSP_CTRL0__DATA_XFER : 0) |
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(read ? HW_SSP_CTRL0__READ : 0);
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/* setup the dma parameters */
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ssp_dma_cmd[ssp - 1].dma.buffer = buffer;
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ssp_dma_cmd[ssp - 1].dma.next = NULL;
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ssp_dma_cmd[ssp - 1].dma.cmd =
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(buffer == NULL ? HW_APB_CHx_CMD__COMMAND__NO_XFER :
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read ? HW_APB_CHx_CMD__COMMAND__WRITE : HW_APB_CHx_CMD__COMMAND__READ) |
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HW_APB_CHx_CMD__IRQONCMPLT | HW_APB_CHx_CMD__SEMAPHORE |
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HW_APB_CHx_CMD__WAIT4ENDCMD | HW_APB_CHx_CMD__HALTONTERMINATE |
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(3 << HW_APB_CHx_CMD__CMDWORDS_BP) |
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(xfer_size << HW_APB_CHx_CMD__XFER_COUNT_BP);
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imx233_dma_start_command(APB_SSP(ssp), &ssp_dma_cmd[ssp - 1].dma);
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/* the SSP hardware already has a timeout but we never know; 1 sec is a maximum
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* for all operations */
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enum imx233_ssp_error_t ret;
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if(semaphore_wait(&ssp_sema[ssp - 1], HZ) == OBJ_WAIT_TIMEDOUT)
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ret = SSP_TIMEOUT;
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else if((HW_SSP_CTRL1(ssp) & HW_SSP_CTRL1__ALL_IRQ) == 0)
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ret = SSP_SUCCESS;
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else if(HW_SSP_CTRL1(ssp) & (HW_SSP_CTRL1__RESP_TIMEOUT_IRQ |
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HW_SSP_CTRL1__DATA_TIMEOUT_IRQ | HW_SSP_CTRL1__RECV_TIMEOUT_IRQ))
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ret = SSP_TIMEOUT;
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else
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ret = SSP_ERROR;
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if(ret == SSP_SUCCESS && resp_ptr != NULL)
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{
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if(resp != SSP_NO_RESP)
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*resp_ptr++ = HW_SSP_SDRESP0(ssp);
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if(resp == SSP_LONG_RESP)
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{
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*resp_ptr++ = HW_SSP_SDRESP1(ssp);
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*resp_ptr++ = HW_SSP_SDRESP2(ssp);
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*resp_ptr++ = HW_SSP_SDRESP3(ssp);
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}
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}
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mutex_unlock(&ssp_mutex[ssp - 1]);
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return ret;
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}
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void imx233_ssp_sd_mmc_power_up_sequence(int ssp)
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{
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__SLOW_CLKING_EN;
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__REG_SET(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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mdelay(1);
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__REG_CLR(HW_SSP_CMD0(ssp)) = HW_SSP_CMD0__CONT_CLKING_EN;
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}
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