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Patch #2 from FS#10633 (Nano 2G developments) by Michael Sparmann - Some hardware define corrections for the S5L8701, needed for the FTL.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22875 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman
parent
14eb02d347
commit
2b7bc42deb
2 changed files with 160 additions and 74 deletions
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@ -127,6 +127,7 @@
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#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
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#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */
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#if CONFIG_CPU==S5L8701
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#if CONFIG_CPU==S5L8701
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#define INTMSK_TIMERB (1<<5)
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#define INTMSK_TIMERB (1<<5)
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#define INTMSK_ECC (1<<19)
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#else
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#else
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#define INTMSK_TIMERB (1<<7)
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#define INTMSK_TIMERB (1<<7)
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#endif
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#endif
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@ -192,7 +193,58 @@
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#define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */
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#define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */
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#define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */
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#define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */
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#define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */
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#define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */
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#if CONFIG_CPU==S5L8701
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#define DMABASE4 (*(REG32_PTR_T)(0x38400080)) /* Base address register for channel 4 */
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#define DMACON4 (*(REG32_PTR_T)(0x38400084)) /* Configuration register for channel 4 */
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#define DMATCNT4 (*(REG32_PTR_T)(0x38400088)) /* Transfer count register for channel 4 */
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#define DMACADDR4 (*(REG32_PTR_T)(0x3840008C)) /* Current memory address register for channel 4 */
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#define DMACTCNT4 (*(REG32_PTR_T)(0x38400090)) /* Current transfer count register for channel 4 */
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#define DMACOM4 (*(REG32_PTR_T)(0x38400094)) /* Channel 4 command register */
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#define DMABASE5 (*(REG32_PTR_T)(0x384000A0)) /* Base address register for channel 5 */
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#define DMACON5 (*(REG32_PTR_T)(0x384000A4)) /* Configuration register for channel 5 */
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#define DMATCNT5 (*(REG32_PTR_T)(0x384000A8)) /* Transfer count register for channel 5 */
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#define DMACADDR5 (*(REG32_PTR_T)(0x384000AC)) /* Current memory address register for channel 5 */
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#define DMACTCNT5 (*(REG32_PTR_T)(0x384000B0)) /* Current transfer count register for channel 5 */
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#define DMACOM5 (*(REG32_PTR_T)(0x384000B4)) /* Channel 5 command register */
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#define DMABASE6 (*(REG32_PTR_T)(0x384000C0)) /* Base address register for channel 6 */
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#define DMACON6 (*(REG32_PTR_T)(0x384000C4)) /* Configuration register for channel 6 */
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#define DMATCNT6 (*(REG32_PTR_T)(0x384000C8)) /* Transfer count register for channel 6 */
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#define DMACADDR6 (*(REG32_PTR_T)(0x384000CC)) /* Current memory address register for channel 6 */
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#define DMACTCNT6 (*(REG32_PTR_T)(0x384000D0)) /* Current transfer count register for channel 6 */
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#define DMACOM6 (*(REG32_PTR_T)(0x384000D4)) /* Channel 6 command register */
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#define DMABASE7 (*(REG32_PTR_T)(0x384000E0)) /* Base address register for channel 7 */
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#define DMACON7 (*(REG32_PTR_T)(0x384000E4)) /* Configuration register for channel 7 */
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#define DMATCNT7 (*(REG32_PTR_T)(0x384000E8)) /* Transfer count register for channel 7 */
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#define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */
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#define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */
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#define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */
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#define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */
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#else
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#define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */
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#define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */
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#endif
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#define DMACON_DEVICE_SHIFT 30
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#define DMACON_DIRECTION_SHIFT 29
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#define DMACON_DATA_SIZE_SHIFT 22
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#define DMACON_BURST_LEN_SHIFT 19
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#define DMACOM_START 4
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#define DMACOM_CLEARBOTHDONE 7
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#define DMAALLST_WCOM0 (1 << 0)
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#define DMAALLST_HCOM0 (1 << 1)
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#define DMAALLST_DMABUSY0 (1 << 2)
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#define DMAALLST_HOLD_SKIP (1 << 3)
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#define DMAALLST_WCOM1 (1 << 4)
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#define DMAALLST_HCOM1 (1 << 5)
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#define DMAALLST_DMABUSY1 (1 << 6)
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#define DMAALLST_WCOM2 (1 << 8)
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#define DMAALLST_HCOM2 (1 << 9)
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#define DMAALLST_DMABUSY2 (1 << 10)
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#define DMAALLST_WCOM3 (1 << 12)
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#define DMAALLST_HCOM3 (1 << 13)
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#define DMAALLST_DMABUSY3 (1 << 14)
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#define DMAALLST_CHAN0_MASK (0xF << 0)
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#define DMAALLST_CHAN1_MASK (0xF << 4)
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#define DMAALLST_CHAN2_MASK (0xF << 8)
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#define DMAALLST_CHAN3_MASK (0xF << 12)
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/* 10. REAL TIMER CLOCK (RTC) */
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/* 10. REAL TIMER CLOCK (RTC) */
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#define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */
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#define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */
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@ -246,59 +298,79 @@
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#define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */
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#define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */
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/* 12. NAND FLASH CONTROLER */
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/* 12. NAND FLASH CONTROLER */
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#define FMCTRL0 (*(REG32_PTR_T)(0x3C200000)) /* Control Register0 */
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#if CONFIG_CPU==S5L8701
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#define FMCTRL1 (*(REG32_PTR_T)(0x3C200004)) /* Control Register1 */
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#define FMC_BASE 0x39400000
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#define FMCMD (*(REG32_PTR_T)(0x3C200008)) /* Command Register */
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#else
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#define FMADDR0 (*(REG32_PTR_T)(0x3C20000C)) /* Address Register0 */
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#define FMC_BASE 0x3C200000
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#define FMADDR1 (*(REG32_PTR_T)(0x3C200010)) /* Address Register1 */
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#endif
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#define FMADDR2 (*(REG32_PTR_T)(0x3C200014)) /* Address Register2 */
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#define FMCTRL0 (*(REG32_PTR_T)(FMC_BASE + 0x0000)) /* Control Register0 */
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#define FMADDR3 (*(REG32_PTR_T)(0x3C200018)) /* Address Register3 */
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#define FMCTRL1 (*(REG32_PTR_T)(FMC_BASE + 0x0004)) /* Control Register1 */
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#define FMADDR4 (*(REG32_PTR_T)(0x3C20001C)) /* Address Register4 */
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#define FMCMD (*(REG32_PTR_T)(FMC_BASE + 0x0008)) /* Command Register */
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#define FMADDR5 (*(REG32_PTR_T)(0x3C200020)) /* Address Register5 */
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#define FMADDR0 (*(REG32_PTR_T)(FMC_BASE + 0x000C)) /* Address Register0 */
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#define FMADDR6 (*(REG32_PTR_T)(0x3C200024)) /* Address Register6 */
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#define FMADDR1 (*(REG32_PTR_T)(FMC_BASE + 0x0010)) /* Address Register1 */
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#define FMADDR7 (*(REG32_PTR_T)(0x3C200028)) /* Address Register7 */
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#define FMADDR2 (*(REG32_PTR_T)(FMC_BASE + 0x0014)) /* Address Register2 */
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#define FMANUM (*(REG32_PTR_T)(0x3C20002C)) /* Address Counter Register */
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#define FMADDR3 (*(REG32_PTR_T)(FMC_BASE + 0x0018)) /* Address Register3 */
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#define FMDNUM (*(REG32_PTR_T)(0x3C200030)) /* Data Counter Register */
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#define FMADDR4 (*(REG32_PTR_T)(FMC_BASE + 0x001C)) /* Address Register4 */
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#define FMDATAW0 (*(REG32_PTR_T)(0x3C200034)) /* Write Data Register0 */
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#define FMADDR5 (*(REG32_PTR_T)(FMC_BASE + 0x0020)) /* Address Register5 */
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#define FMDATAW1 (*(REG32_PTR_T)(0x3C200038)) /* Write Data Register1 */
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#define FMADDR6 (*(REG32_PTR_T)(FMC_BASE + 0x0024)) /* Address Register6 */
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#define FMDATAW2 (*(REG32_PTR_T)(0x3C20003C)) /* Write Data Register2 */
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#define FMADDR7 (*(REG32_PTR_T)(FMC_BASE + 0x0028)) /* Address Register7 */
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#define FMDATAW3 (*(REG32_PTR_T)(0x3C200040)) /* Write Data Register3 */
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#define FMANUM (*(REG32_PTR_T)(FMC_BASE + 0x002C)) /* Address Counter Register */
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#define FMCSTAT (*(REG32_PTR_T)(0x3C200048)) /* Status Register */
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#define FMDNUM (*(REG32_PTR_T)(FMC_BASE + 0x0030)) /* Data Counter Register */
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#define FMSYND0 (*(REG32_PTR_T)(0x3C20004C)) /* Hamming Syndrome0 */
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#define FMDATAW0 (*(REG32_PTR_T)(FMC_BASE + 0x0034)) /* Write Data Register0 */
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#define FMSYND1 (*(REG32_PTR_T)(0x3C200050)) /* Hamming Syndrome1 */
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#define FMDATAW1 (*(REG32_PTR_T)(FMC_BASE + 0x0038)) /* Write Data Register1 */
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#define FMSYND2 (*(REG32_PTR_T)(0x3C200054)) /* Hamming Syndrome2 */
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#define FMDATAW2 (*(REG32_PTR_T)(FMC_BASE + 0x003C)) /* Write Data Register2 */
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#define FMSYND3 (*(REG32_PTR_T)(0x3C200058)) /* Hamming Syndrome3 */
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#define FMDATAW3 (*(REG32_PTR_T)(FMC_BASE + 0x0040)) /* Write Data Register3 */
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#define FMSYND4 (*(REG32_PTR_T)(0x3C20005C)) /* Hamming Syndrome4 */
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#define FMCSTAT (*(REG32_PTR_T)(FMC_BASE + 0x0048)) /* Status Register */
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#define FMSYND5 (*(REG32_PTR_T)(0x3C200060)) /* Hamming Syndrome5 */
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#define FMSYND0 (*(REG32_PTR_T)(FMC_BASE + 0x004C)) /* Hamming Syndrome0 */
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#define FMSYND6 (*(REG32_PTR_T)(0x3C200064)) /* Hamming Syndrome6 */
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#define FMSYND1 (*(REG32_PTR_T)(FMC_BASE + 0x0050)) /* Hamming Syndrome1 */
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#define FMSYND7 (*(REG32_PTR_T)(0x3C200068)) /* Hamming Syndrome7 */
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#define FMSYND2 (*(REG32_PTR_T)(FMC_BASE + 0x0054)) /* Hamming Syndrome2 */
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#define FMFIFO (*(REG32_PTR_T)(0x3C200080)) /* WRITE/READ FIFO FIXME */
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#define FMSYND3 (*(REG32_PTR_T)(FMC_BASE + 0x0058)) /* Hamming Syndrome3 */
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#define RSCRTL (*(REG32_PTR_T)(0x3C200100)) /* Reed-Solomon Control Register */
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#define FMSYND4 (*(REG32_PTR_T)(FMC_BASE + 0x005C)) /* Hamming Syndrome4 */
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#define RSPaity0_0 (*(REG32_PTR_T)(0x3C200110)) /* On-the-fly Parity Register0[31:0] */
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#define FMSYND5 (*(REG32_PTR_T)(FMC_BASE + 0x0060)) /* Hamming Syndrome5 */
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#define RSPaity0_1 (*(REG32_PTR_T)(0x3C200114)) /* On-the-fly Parity Register0[63:32] */
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#define FMSYND6 (*(REG32_PTR_T)(FMC_BASE + 0x0064)) /* Hamming Syndrome6 */
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#define RSPaity0_2 (*(REG32_PTR_T)(0x3C200118)) /* On-the-fly Parity Register0[71:64] */
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#define FMSYND7 (*(REG32_PTR_T)(FMC_BASE + 0x0068)) /* Hamming Syndrome7 */
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#define RSPaity1_0 (*(REG32_PTR_T)(0x3C200120)) /* On-the-fly Parity Register1[31:0] */
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#define FMFIFO (*(REG32_PTR_T)(FMC_BASE + 0x0080)) /* WRITE/READ FIFO FIXME */
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#define RSPaity1_1 (*(REG32_PTR_T)(0x3C200124)) /* On-the-fly Parity Register1[63:32] */
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#define RSCRTL (*(REG32_PTR_T)(FMC_BASE + 0x0100)) /* Reed-Solomon Control Register */
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#define RSPaity1_2 (*(REG32_PTR_T)(0x3C200128)) /* On-the-fly Parity Register1[71:64] */
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#define RSPARITY0_0 (*(REG32_PTR_T)(FMC_BASE + 0x0110)) /* On-the-fly Parity Register0[31:0] */
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#define RSPaity2_0 (*(REG32_PTR_T)(0x3C200130)) /* On-the-fly Parity Register2[31:0] */
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#define RSPARITY0_1 (*(REG32_PTR_T)(FMC_BASE + 0x0114)) /* On-the-fly Parity Register0[63:32] */
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#define RSPaity2_1 (*(REG32_PTR_T)(0x3C200134)) /* On-the-fly Parity Register2[63:32] */
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#define RSPARITY0_2 (*(REG32_PTR_T)(FMC_BASE + 0x0118)) /* On-the-fly Parity Register0[71:64] */
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#define RSPaity2_2 (*(REG32_PTR_T)(0x3C200138)) /* On-the-fly Parity Register2[71:64] */
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#define RSPARITY1_0 (*(REG32_PTR_T)(FMC_BASE + 0x0120)) /* On-the-fly Parity Register1[31:0] */
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#define RSPaity3_0 (*(REG32_PTR_T)(0x3C200140)) /* On-the-fly Parity Register3[31:0] */
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#define RSPARITY1_1 (*(REG32_PTR_T)(FMC_BASE + 0x0124)) /* On-the-fly Parity Register1[63:32] */
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#define RSPaity3_1 (*(REG32_PTR_T)(0x3C200144)) /* On-the-fly Parity Register3[63:32] */
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#define RSPARITY1_2 (*(REG32_PTR_T)(FMC_BASE + 0x0128)) /* On-the-fly Parity Register1[71:64] */
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#define RSPaity3_2 (*(REG32_PTR_T)(0x3C200148)) /* On-the-fly Parity Register3[71:64] */
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#define RSPARITY2_0 (*(REG32_PTR_T)(FMC_BASE + 0x0130)) /* On-the-fly Parity Register2[31:0] */
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#define RSSynd0_0 (*(REG32_PTR_T)(0x3C200150)) /* On-the-fly Synd Register0[31:0] */
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#define RSPARITY2_1 (*(REG32_PTR_T)(FMC_BASE + 0x0134)) /* On-the-fly Parity Register2[63:32] */
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#define RSSynd0_1 (*(REG32_PTR_T)(0x3C200154)) /* On-the-fly Synd Register0[63:32] */
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#define RSPARITY2_2 (*(REG32_PTR_T)(FMC_BASE + 0x0138)) /* On-the-fly Parity Register2[71:64] */
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#define RSSynd0_2 (*(REG32_PTR_T)(0x3C200158)) /* On-the-fly Synd Register0[71:64] */
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#define RSPARITY3_0 (*(REG32_PTR_T)(FMC_BASE + 0x0140)) /* On-the-fly Parity Register3[31:0] */
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#define RSSynd1_0 (*(REG32_PTR_T)(0x3C200160)) /* On-the-fly Synd Register1[31:0] */
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#define RSPARITY3_1 (*(REG32_PTR_T)(FMC_BASE + 0x0144)) /* On-the-fly Parity Register3[63:32] */
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#define RSSynd1_1 (*(REG32_PTR_T)(0x3C200164)) /* On-the-fly Synd Register1[63:32] */
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#define RSPARITY3_2 (*(REG32_PTR_T)(FMC_BASE + 0x0148)) /* On-the-fly Parity Register3[71:64] */
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#define RSSynd1_2 (*(REG32_PTR_T)(0x3C200168)) /* On-the-fly Synd Register1[71:64] */
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#define RSSYND0_0 (*(REG32_PTR_T)(FMC_BASE + 0x0150)) /* On-the-fly Synd Register0[31:0] */
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#define RSSynd2_0 (*(REG32_PTR_T)(0x3C200170)) /* On-the-fly Synd Register2[31:0] */
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#define RSSYND0_1 (*(REG32_PTR_T)(FMC_BASE + 0x0154)) /* On-the-fly Synd Register0[63:32] */
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#define RSSynd2_1 (*(REG32_PTR_T)(0x3C200174)) /* On-the-fly Synd Register2[63:32] */
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#define RSSYND0_2 (*(REG32_PTR_T)(FMC_BASE + 0x0158)) /* On-the-fly Synd Register0[71:64] */
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#define RSSynd2_2 (*(REG32_PTR_T)(0x3C200178)) /* On-the-fly Synd Register2[71:64] */
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#define RSSYND1_0 (*(REG32_PTR_T)(FMC_BASE + 0x0160)) /* On-the-fly Synd Register1[31:0] */
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#define RSSynd3_0 (*(REG32_PTR_T)(0x3C200180)) /* On-the-fly Synd Register3[31:0] */
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#define RSSYND1_1 (*(REG32_PTR_T)(FMC_BASE + 0x0164)) /* On-the-fly Synd Register1[63:32] */
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#define RSSynd3_1 (*(REG32_PTR_T)(0x3C200184)) /* On-the-fly Synd Register3[63:32] */
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#define RSSYND1_2 (*(REG32_PTR_T)(FMC_BASE + 0x0168)) /* On-the-fly Synd Register1[71:64] */
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#define RSSynd3_2 (*(REG32_PTR_T)(0x3C200188)) /* On-the-fly Synd Register3[71:64] */
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#define RSSYND2_0 (*(REG32_PTR_T)(FMC_BASE + 0x0170)) /* On-the-fly Synd Register2[31:0] */
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#define FlagSynd (*(REG32_PTR_T)(0x3C200190)) /* On-the-fly ECC Result Flag */
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#define RSSYND2_1 (*(REG32_PTR_T)(FMC_BASE + 0x0174)) /* On-the-fly Synd Register2[63:32] */
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#define RSSYND2_2 (*(REG32_PTR_T)(FMC_BASE + 0x0178)) /* On-the-fly Synd Register2[71:64] */
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#define RSSYND3_0 (*(REG32_PTR_T)(FMC_BASE + 0x0180)) /* On-the-fly Synd Register3[31:0] */
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#define RSSYND3_1 (*(REG32_PTR_T)(FMC_BASE + 0x0184)) /* On-the-fly Synd Register3[63:32] */
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#define RSSYND3_2 (*(REG32_PTR_T)(FMC_BASE + 0x0188)) /* On-the-fly Synd Register3[71:64] */
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#define FLAGSYND (*(REG32_PTR_T)(FMC_BASE + 0x0190)) /* On-the-fly ECC Result Flag */
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#define FMCTRL0_ENABLEDMA (1 << 10)
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#define FMCTRL0_UNK1 (1 << 11)
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#define FMCTRL1_DOTRANSADDR (1 << 0)
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#define FMCTRL1_DOREADDATA (1 << 1)
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#define FMCTRL1_DOWRITEDATA (1 << 2)
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#define FMCTRL1_CLEARWFIFO (1 << 6)
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#define FMCTRL1_CLEARRFIFO (1 << 7)
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#define FMCSTAT_RBB (1 << 0)
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#define FMCSTAT_RBBDONE (1 << 1)
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#define FMCSTAT_CMDDONE (1 << 2)
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#define FMCSTAT_ADDRDONE (1 << 3)
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#define FMCSTAT_BANK0READY (1 << 4)
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#define FMCSTAT_BANK1READY (1 << 5)
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#define FMCSTAT_BANK2READY (1 << 6)
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#define FMCSTAT_BANK3READY (1 << 7)
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/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
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/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
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#define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */
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#define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */
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@ -335,21 +407,25 @@
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#define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */
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#define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */
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/* 16. REED-SOLOMON ECC CODEC */
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/* 16. REED-SOLOMON ECC CODEC */
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#define DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */
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#define ECC_DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */
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||||||
#define SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */
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#define ECC_SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */
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||||||
#define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */
|
#define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */
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||||||
#define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */
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#define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */
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||||||
|
#define ECC_UNK1 (*(REG32_PTR_T)(0x39E00014)) /* No idea what this is, but the OFW uses it on S5L8701 */
|
||||||
#define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */
|
#define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */
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||||||
#define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */
|
#define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */
|
||||||
#define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */
|
#define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */
|
||||||
#define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */
|
#define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */
|
||||||
#define PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */
|
#define ECC_PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */
|
||||||
#define PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */
|
#define ECC_PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */
|
||||||
#define PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */
|
#define ECC_PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */
|
||||||
#define INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */
|
#define ECC_INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */
|
||||||
#define SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */
|
#define ECC_SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */
|
||||||
#define SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */
|
#define ECC_SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */
|
||||||
#define SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */
|
#define ECC_SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */
|
||||||
|
#define ECCCTRL_STARTDECODING (1 << 0)
|
||||||
|
#define ECCCTRL_STARTENCODING (1 << 1)
|
||||||
|
#define ECCCTRL_STARTDECNOSYND (1 << 2)
|
||||||
|
|
||||||
/* 17. IIS Tx/Rx INTERFACE */
|
/* 17. IIS Tx/Rx INTERFACE */
|
||||||
#define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */
|
#define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */
|
||||||
|
|
|
||||||
|
|
@ -64,31 +64,41 @@ default_interrupt(INT_ADC);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if CONFIG_CPU==S5L8701
|
||||||
|
static void (* const irqvector[])(void) =
|
||||||
|
{ /* still 90% unverified and probably incorrect */
|
||||||
|
EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERB,INT_WDT,INT_TIMERA,
|
||||||
|
INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
|
||||||
|
INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
|
||||||
|
INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
|
||||||
|
};
|
||||||
|
#else
|
||||||
static void (* const irqvector[])(void) =
|
static void (* const irqvector[])(void) =
|
||||||
{
|
{
|
||||||
EXT0,EXT1,EXT2,EINT_VBUS,EINTG,
|
EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
|
||||||
#if CONFIG_CPU==S5L8701
|
|
||||||
INT_TIMERB,INT_WDT,INT_TIMERA,
|
|
||||||
#else
|
|
||||||
INT_TIMERA,INT_WDT,INT_TIMERB,
|
|
||||||
#endif
|
|
||||||
INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
|
INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
|
||||||
INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
|
INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
|
||||||
INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
|
INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_CPU==S5L8701
|
||||||
|
static const char * const irqname[] =
|
||||||
|
{ /* still 90% unverified and probably incorrect */
|
||||||
|
"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERB","INT_WDT","INT_TIMERA",
|
||||||
|
"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
|
||||||
|
"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC",
|
||||||
|
"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
|
||||||
|
};
|
||||||
|
#else
|
||||||
static const char * const irqname[] =
|
static const char * const irqname[] =
|
||||||
{
|
{
|
||||||
"EXT0","EXT1","EXT2","EINT_VBUS","EINTG",
|
"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
|
||||||
#if CONFIG_CPU==S5L8701
|
|
||||||
"INT_TIMERB","INT_WDT","INT_TIMERA",
|
|
||||||
#else
|
|
||||||
"INT_TIMERA","INT_WDT","INT_TIMERB",
|
|
||||||
#endif
|
|
||||||
"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
|
"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
|
||||||
"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
|
"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
|
||||||
"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
|
"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
|
||||||
};
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
static void UIRQ(void)
|
static void UIRQ(void)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue