From 2b6886d107e5d6adf70bdf217960a5a3fc47a251 Mon Sep 17 00:00:00 2001
From: Marcin Bukat <marcin.bukat@gmail.com>
Date: Mon, 27 Aug 2012 23:32:23 +0200
Subject: [PATCH] rk27xx: Turn off lsadc clock when not in use

Change-Id: Ic3f29e75aa5b894f17e289263a370fac13e2f1d8
---
 firmware/target/arm/rk27xx/adc-rk27xx.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/firmware/target/arm/rk27xx/adc-rk27xx.c b/firmware/target/arm/rk27xx/adc-rk27xx.c
index 3a2f7970c1..48fab390e3 100644
--- a/firmware/target/arm/rk27xx/adc-rk27xx.c
+++ b/firmware/target/arm/rk27xx/adc-rk27xx.c
@@ -28,6 +28,14 @@
 
 unsigned short adc_read(int channel)
 {
+    unsigned short result;
+
+    /* ungate lsadc clocks */
+    SCU_CLKCFG &= ~(3<<23);
+
+    /* wait a bit for clock to stabilize */
+    udelay(10);
+
     ADC_CTRL = (1<<4)|(1<<3) | (channel & (NUM_ADC_CHANNELS - 1));
 
     /* Wait for conversion ready.
@@ -38,16 +46,18 @@ unsigned short adc_read(int channel)
      * ~10us should be enough so we wait 20us to be on the safe side
      */
     udelay(20);
- 
+
     /* 10bits result */
-    return (ADC_DATA & 0x3ff);
+    result = (ADC_DATA & 0x3ff);
+
+    /* turn off lsadc clock when not in use */
+    SCU_CLKCFG |= (3<<23);
+
+    return result; 
 }
 
 void adc_init(void)
 {
     /* ADC clock divider to reach max 1MHz */
     SCU_DIVCON1 = (SCU_DIVCON1 & ~(0xff<<10)) | (49<<10);
-
-    /* enable clocks for ADC */
-    SCU_CLKCFG &= ~(3<<23);
 }