mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-11 22:22:33 -05:00
imx233: rewrite clkctrl using new register headers
Change-Id: I6c79e99ed4ab20e00c3110d870e144a6c8596769
This commit is contained in:
Amaury Pouly
parent
f545908c16
commit
2a01b3766f
4 changed files with 98 additions and 218 deletions
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@ -26,9 +26,9 @@
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void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
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{
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if(enable)
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__REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk;
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HW_CLKCTRL_XTAL_CLR = xtal_clk;
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else
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__REG_SET(HW_CLKCTRL_XTAL) = xtal_clk;
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HW_CLKCTRL_XTAL_SET = xtal_clk;
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}
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bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
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@ -38,78 +38,49 @@ bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
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void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
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{
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volatile uint32_t *REG;
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bool gate = !enable;
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switch(clk)
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{
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case CLK_PIX: REG = &HW_CLKCTRL_PIX; break;
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case CLK_SSP: REG = &HW_CLKCTRL_SSP; break;
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case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break;
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case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break;
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case CLK_PLL:
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{
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/* pll is a special case */
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if(enable)
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{
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER;
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while(!(HW_CLKCTRL_PLLCTRL1 & HW_CLKCTRL_PLLCTRL1__LOCK));
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BF_SET(CLKCTRL_PLLCTRL0, POWER);
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while(!BF_RD(CLKCTRL_PLLCTRL1, LOCK));
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}
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else
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__REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__POWER;
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return;
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}
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default: return;
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}
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
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if(enable)
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{
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*REG = (*REG) & ~__CLK_CLKGATE;
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while((*REG) & __CLK_CLKGATE);
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while((*REG) & __CLK_BUSY);
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}
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else
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{
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*REG |= __CLK_CLKGATE;
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while(!((*REG) & __CLK_CLKGATE));
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BF_CLR(CLKCTRL_PLLCTRL0, POWER);
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break;
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default:
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break;
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}
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}
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bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
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{
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volatile uint32_t *REG;
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switch(clk)
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{
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case CLK_PLL: return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__POWER;
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case CLK_PIX: REG = &HW_CLKCTRL_PIX; break;
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case CLK_SSP: REG = &HW_CLKCTRL_SSP; break;
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case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER);
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case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE);
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case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE);
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default: return true;
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}
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return !((*REG) & __CLK_CLKGATE);
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}
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void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
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{
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
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/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant !
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* assume that we always derive emi and cpu from ref_XX */
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switch(clk)
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{
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case CLK_PIX:
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__FIELD_SET(HW_CLKCTRL_PIX, DIV, div);
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break;
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case CLK_SSP:
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__FIELD_SET(HW_CLKCTRL_SSP, DIV, div);
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break;
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case CLK_CPU:
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__FIELD_SET(HW_CLKCTRL_CPU, DIV_CPU, div);
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break;
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case CLK_EMI:
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__FIELD_SET(HW_CLKCTRL_EMI, DIV_EMI, div);
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break;
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case CLK_HBUS:
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/* disable frac enable at the same time */
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HW_CLKCTRL_HBUS = div << HW_CLKCTRL_HBUS__DIV_BP |
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(HW_CLKCTRL_HBUS & ~(HW_CLKCTRL_HBUS__DIV_FRAC_EN | HW_CLKCTRL_HBUS__DIV_BM));
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break;
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case CLK_XBUS:
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__FIELD_SET(HW_CLKCTRL_XBUS, DIV, div);
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break;
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case CLK_PIX: BF_WR(CLKCTRL_PIX, DIV, div); break;
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case CLK_CPU: BF_WR(CLKCTRL_CPU, DIV_CPU, div); break;
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case CLK_EMI: BF_WR(CLKCTRL_EMI, DIV_EMI, div); break;
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case CLK_SSP: BF_WR(CLKCTRL_SSP, DIV, div); break;
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case CLK_HBUS: BF_WR(CLKCTRL_HBUS, DIV, div); break;
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case CLK_XBUS: BF_WR(CLKCTRL_XBUS, DIV, div); break;
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default: return;
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}
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}
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@ -118,66 +89,54 @@ int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
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{
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switch(clk)
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{
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case CLK_PIX: return __XTRACT(HW_CLKCTRL_PIX, DIV);
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case CLK_SSP: return __XTRACT(HW_CLKCTRL_SSP, DIV);
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case CLK_CPU: return __XTRACT(HW_CLKCTRL_CPU, DIV_CPU);
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case CLK_EMI: return __XTRACT(HW_CLKCTRL_EMI, DIV_EMI);
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case CLK_HBUS:
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if(HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__DIV_FRAC_EN)
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return 0;
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else
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return __XTRACT(HW_CLKCTRL_HBUS, DIV);
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case CLK_XBUS: return __XTRACT(HW_CLKCTRL_XBUS, DIV);
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case CLK_PIX: return BF_RD(CLKCTRL_PIX, DIV);
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case CLK_CPU: return BF_RD(CLKCTRL_CPU, DIV_CPU);
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case CLK_EMI: return BF_RD(CLKCTRL_EMI, DIV_EMI);
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case CLK_SSP: return BF_RD(CLKCTRL_SSP, DIV);
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case CLK_HBUS: return BF_RD(CLKCTRL_HBUS, DIV);
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case CLK_XBUS: return BF_RD(CLKCTRL_XBUS, DIV);
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default: return 0;
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}
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}
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void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
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{
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/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
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volatile uint8_t *REG;
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#define handle_frac(dev) \
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case CLK_##dev: \
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if(fracdiv == 0) \
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BF_SET(CLKCTRL_FRAC, CLKGATE##dev); \
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else { \
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BF_WR(CLKCTRL_FRAC, dev##FRAC, fracdiv); \
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BF_CLR(CLKCTRL_FRAC, CLKGATE##dev); } \
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break;
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switch(clk)
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{
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case CLK_HBUS:
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/* set frac enable at the same time */
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HW_CLKCTRL_HBUS = fracdiv << HW_CLKCTRL_HBUS__DIV_BP | HW_CLKCTRL_HBUS__DIV_FRAC_EN |
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(HW_CLKCTRL_HBUS & ~HW_CLKCTRL_HBUS__DIV_BM);
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return;
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case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break;
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case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break;
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case CLK_CPU: REG = &HW_CLKCTRL_FRAC_CPU; break;
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case CLK_EMI: REG = &HW_CLKCTRL_FRAC_EMI; break;
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default: return;
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handle_frac(PIX)
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handle_frac(IO)
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handle_frac(CPU)
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handle_frac(EMI)
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default: break;
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}
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if(fracdiv != 0)
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*REG = fracdiv;
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else
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*REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;
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#undef handle_frac
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}
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int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
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{
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/* NOTE: HW_CLKCTRL_FRAC only support byte access ! */
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volatile uint8_t *REG;
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#define handle_frac(dev) \
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case CLK_##dev:\
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if(BF_RD(CLKCTRL_FRAC, CLKGATE##dev)) \
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return 0; \
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else \
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return BF_RD(CLKCTRL_FRAC, dev##FRAC);
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switch(clk)
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{
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case CLK_HBUS:
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if(HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__DIV_FRAC_EN)
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return __XTRACT(HW_CLKCTRL_HBUS, DIV);
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else
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return 0;
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case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break;
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case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break;
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case CLK_CPU: REG = &HW_CLKCTRL_FRAC_CPU; break;
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case CLK_EMI: REG = &HW_CLKCTRL_FRAC_EMI; break;
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handle_frac(PIX)
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handle_frac(IO)
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handle_frac(CPU)
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handle_frac(EMI)
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default: return 0;
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}
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if((*REG) & HW_CLKCTRL_FRAC_XX__CLKGATEXX)
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return 0;
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else
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return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE;
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#undef handle_frac
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}
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void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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@ -185,45 +144,42 @@ void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
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uint32_t msk;
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switch(clk)
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{
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case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break;
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case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break;
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case CLK_CPU: msk = HW_CLKCTRL_CLKSEQ__BYPASS_CPU; break;
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case CLK_EMI: msk = HW_CLKCTRL_CLKSEQ__BYPASS_EMI; break;
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case CLK_PIX: msk = BM_CLKCTRL_CLKSEQ_BYPASS_PIX; break;
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case CLK_SSP: msk = BM_CLKCTRL_CLKSEQ_BYPASS_SSP; break;
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case CLK_CPU: msk = BM_CLKCTRL_CLKSEQ_BYPASS_CPU; break;
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case CLK_EMI: msk = BM_CLKCTRL_CLKSEQ_BYPASS_EMI; break;
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default: return;
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}
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if(bypass)
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__REG_SET(HW_CLKCTRL_CLKSEQ) = msk;
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HW_CLKCTRL_CLKSEQ_SET = msk;
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else
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__REG_CLR(HW_CLKCTRL_CLKSEQ) = msk;
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HW_CLKCTRL_CLKSEQ_CLR = msk;
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}
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bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
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{
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uint32_t msk;
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switch(clk)
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{
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case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break;
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case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break;
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case CLK_CPU: msk = HW_CLKCTRL_CLKSEQ__BYPASS_CPU; break;
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case CLK_EMI: msk = HW_CLKCTRL_CLKSEQ__BYPASS_EMI; break;
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case CLK_PIX: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_PIX);
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case CLK_SSP: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_SSP);
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case CLK_CPU: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_CPU);
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case CLK_EMI: return BF_RD(CLKCTRL_CLKSEQ, BYPASS_EMI);
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default: return false;
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}
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return HW_CLKCTRL_CLKSEQ & msk;
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}
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void imx233_clkctrl_enable_usb_pll(bool enable)
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{
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if(enable)
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__REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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else
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__REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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}
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bool imx233_clkctrl_is_usb_pll_enabled(void)
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{
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return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS;
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return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
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}
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void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
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@ -231,34 +187,31 @@ void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
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/* the SLOW_DIV must only be set when auto-slow is disabled */
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bool old_status = imx233_clkctrl_is_auto_slow_enabled();
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imx233_clkctrl_enable_auto_slow(false);
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__FIELD_SET(HW_CLKCTRL_HBUS, SLOW_DIV, div);
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BF_WR(CLKCTRL_HBUS, SLOW_DIV, div);
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imx233_clkctrl_enable_auto_slow(old_status);
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}
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enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
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{
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return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV);
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return BF_RD(CLKCTRL_HBUS, SLOW_DIV);
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}
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void imx233_clkctrl_enable_auto_slow(bool enable)
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{
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if(enable)
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__REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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else
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__REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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BF_WR(CLKCTRL_HBUS, AUTO_SLOW_MODE, enable);
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}
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bool imx233_clkctrl_is_auto_slow_enabled(void)
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{
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return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE;
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return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE);
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}
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void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
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{
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if(enable)
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__REG_SET(HW_CLKCTRL_HBUS) = monitor;
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HW_CLKCTRL_HBUS_SET = monitor;
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else
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__REG_CLR(HW_CLKCTRL_HBUS) = monitor;
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HW_CLKCTRL_HBUS_CLR = monitor;
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}
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bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
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@ -268,7 +221,7 @@ bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monito
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bool imx233_clkctrl_is_emi_sync_enabled(void)
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{
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return !!(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__SYNC_MODE_EN);
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return BF_RD(CLKCTRL_EMI, SYNC_MODE_EN);
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}
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unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
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@ -289,9 +242,9 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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/* Integer divide mode vs fractional divide mode */
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if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN)
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if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN))
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return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32;
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return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32;
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else
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return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
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}
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@ -357,10 +310,10 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
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if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
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{
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ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
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if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE)
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if(BF_RD(CLKCTRL_EMI, CLKGATE))
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return 0;
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else
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return ref / __XTRACT(HW_CLKCTRL_EMI, DIV_XTAL);
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return ref / BF_RD(CLKCTRL_EMI, DIV_XTAL);
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}
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else
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{
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