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ipod Classic: implement HAVE_RECORDING
This patch has been tested on iPod 80 and 160slim, actually it works but some updates must be done to the final version: - unlimitted input buffer - decrease CHUNK_SIZE - use non-cached addresses instead of discard d-cache ??? Capture hardware versions: Ver iPod models capture support --- ----------- --------------- 0 80/160fat dock line-in 1 120/160slim dock line-in + jack mic HW version 1 includes an amplifier for the jack plug mic. Capture HW detection only tested on iPod 80 and 160slim. CODEC power: AFAIK, OF powers CS42L55 at VA=2.4V for capture (1.8V for playback) and turns on the ADC charge pump. CODEC datasheet recommmends to disable the charge pump for VA>2.1V. CS42L55 DS, s4.13 (Required Initialization Settings): for VA>2.1V, some adjustments "must" be done using undocummented "control port compensation" registers. OF does not modifies these registers when VA=2.4V. This patch configures capture HW in the same way as OF does. TODO: - ADC full scale voltage depends on VA, perform tests to find clipping levels for VA=1.8V and VA=2.4V Change-Id: I7e20fd3ecaa83b1c58d5c746f5153fe5c3891d75
This commit is contained in:
Cástor Muñoz
parent
42abc6a496
commit
291b2338c9
6 changed files with 246 additions and 14 deletions
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@ -250,37 +250,201 @@ void * pcm_dma_addr(void *addr)
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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static volatile int rec_locked = 0;
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static void *rec_dma_addr;
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static size_t rec_dma_size;
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static bool pcm_rec_initialized = false;
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static int completed_task;
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/* ahead capture buffer */
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#define PCM_AHEADBUF_SAMPLES 128
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#define AHEADBUF_SZ (PCM_AHEADBUF_SAMPLES * 4)
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static unsigned char ahead_buf[AHEADBUF_SZ] CACHEALIGN_ATTR;
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/* DMA configuration */
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static void dma_rec_callback(void *cb_data) ICODE_ATTR;
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enum { /* cb_data */
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TASK_AHEADBUF,
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TASK_RECBUF
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};
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#define DMA_REC_TSKBUF_SZ 2 /* N tasks, MUST be pow2 */
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#define DMA_REC_LLIBUF_SZ 8 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk dma_rec_tskbuf[DMA_REC_TSKBUF_SZ];
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static struct dmac_lli volatile \
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dma_rec_llibuf[DMA_REC_LLIBUF_SZ] CACHEALIGN_ATTR;
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static struct dmac_ch dma_rec_ch = {
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.dmac = &s5l8702_dmac0,
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.prio = DMAC_CH_PRIO(1),
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.cb_fn = dma_rec_callback,
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.llibuf = dma_rec_llibuf,
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.llibuf_mask = DMA_REC_LLIBUF_SZ - 1,
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.llibuf_bus = DMAC_MASTER_AHB1,
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.tskbuf = dma_rec_tskbuf,
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.tskbuf_mask = DMA_REC_TSKBUF_SZ - 1,
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.queue_mode = QUEUE_LINK,
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};
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static struct dmac_ch_cfg dma_rec_ch_cfg = {
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.srcperi = S5L8702_DMAC0_PERI_IIS0_RX,
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.dstperi = S5L8702_DMAC0_PERI_MEM,
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.sbsize = DMACCxCONTROL_BSIZE_4,
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.dbsize = DMACCxCONTROL_BSIZE_4,
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.swidth = DMACCxCONTROL_WIDTH_16,
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.dwidth = DMACCxCONTROL_WIDTH_16,
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.sbus = DMAC_MASTER_AHB1,
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.dbus = DMAC_MASTER_AHB1,
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.sinc = DMACCxCONTROL_INC_DISABLE,
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.dinc = DMACCxCONTROL_INC_ENABLE,
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.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
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/* align LLI transfers to L-R pairs (samples) */
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.lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
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};
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/* maximum and minimum supported block sizes in bytes */
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#define MIN_SIZE ((size_t) (AHEADBUF_SZ * 2))
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#define MAX_SIZE ((size_t) (AHEADBUF_SZ + ((DMA_REC_LLIBUF_SZ - 1) * \
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(dma_rec_ch_cfg.lli_xfer_max_count << dma_rec_ch_cfg.swidth))))
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#if 0
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#define SIZE_PANIC(sz) { \
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if (((sz) < MIN_SIZE) || ((sz) > MAX_SIZE)) \
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panicf("pcm record: unsupported size: %d", (sz)); \
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}
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#else
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#define SIZE_PANIC(sz) {}
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#endif
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static void rec_dmac_ch_queue(void *addr, size_t size, int cb_data)
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{
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discard_dcache_range(addr, size);
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dmac_ch_queue(&dma_rec_ch, (void*)S5L8702_DADDR_PERI_IIS0_RX,
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addr, size, (void *)cb_data);
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}
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static void dma_rec_callback(void *cb_data)
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{
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completed_task = (int)cb_data;
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if (completed_task == TASK_AHEADBUF)
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{
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/* safety check */
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if (rec_dma_addr == NULL)
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return; /* capture finished */
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/* move ahead buffer to record buffer and queue
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next capture-ahead task */
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memcpy(rec_dma_addr, ahead_buf, AHEADBUF_SZ);
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rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
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}
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else /* TASK_RECBUF */
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{
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/* Inform middle layer */
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if (pcm_rec_dma_complete_callback(
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PCM_DMAST_OK, &rec_dma_addr, &rec_dma_size))
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{
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SIZE_PANIC(rec_dma_size);
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rec_dmac_ch_queue(rec_dma_addr + AHEADBUF_SZ,
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rec_dma_size - AHEADBUF_SZ, TASK_RECBUF);
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pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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}
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void pcm_rec_lock(void)
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{
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if ((rec_locked++ == 0) && pcm_rec_initialized)
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dmac_ch_lock_int(&dma_rec_ch);
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}
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void pcm_rec_unlock(void)
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{
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if ((--rec_locked == 0) && pcm_rec_initialized)
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dmac_ch_unlock_int(&dma_rec_ch);
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}
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void pcm_rec_dma_stop(void)
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{
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if (!pcm_rec_initialized)
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return;
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dmac_ch_stop(&dma_rec_ch);
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I2SRXCOM = 0x2; /* stop Rx I2S */
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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(void)addr;
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(void)size;
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SIZE_PANIC(size);
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pcm_rec_dma_stop();
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rec_dma_addr = addr;
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rec_dma_size = size;
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completed_task = -1;
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/* launch first DMA transfer to capture into ahead buffer,
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link the second task to capture into record buffer */
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rec_dmac_ch_queue(ahead_buf, AHEADBUF_SZ, TASK_AHEADBUF);
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rec_dmac_ch_queue(addr + AHEADBUF_SZ, size - AHEADBUF_SZ, TASK_RECBUF);
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I2SRXCOM = 0x6; /* start Rx I2S */
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}
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void pcm_rec_dma_close(void)
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{
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pcm_rec_dma_stop();
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}
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void pcm_rec_dma_init(void)
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{
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}
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if (pcm_rec_initialized)
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return;
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PWRCON(0) &= ~(1 << 4);
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PWRCON(0) &= ~(1 << 7);
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dmac_ch_init(&dma_rec_ch, &dma_rec_ch_cfg);
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/* synchronize lock status */
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if (rec_locked)
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dmac_ch_lock_int(&dma_rec_ch);
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I2SRXCON = 0x1000;
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I2SCLKCON = 1;
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pcm_rec_initialized = true;
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}
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const void * pcm_rec_dma_get_peak_buffer(void)
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{
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return NULL;
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}
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void *dstaddr;
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pcm_rec_lock();
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if (completed_task == TASK_AHEADBUF) {
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dstaddr = dmac_ch_get_info(&dma_rec_ch, NULL, NULL);
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if ((dstaddr < rec_dma_addr) ||
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(dstaddr > rec_dma_addr + rec_dma_size))
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/* At this moment, interrupt for TASK_RECBUF is waiting to
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be handled. TASK_RECBUF is already finished and HW is
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transfering next TASK_AHEADBUF. Return whole block. */
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dstaddr = rec_dma_addr + rec_dma_size;
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}
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else {
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/* Ahead buffer not yet captured _and_ moved to
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record buffer. Return nothing. */
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dstaddr = rec_dma_addr;
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}
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pcm_rec_unlock();
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return CACHEALIGN_DOWN(dstaddr);
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}
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#endif /* HAVE_RECORDING */
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