len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-08 20:55:17 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

Revise the PCM callback system after adding multichannel audio.

Browse source 
Additional status callback is added to pcm_play/rec_data instead of
using a special function to set it. Status includes DMA error
reporting to the status callback. Playback and recording callback
become more alike except playback uses "const void **addr" (because
the data should not be altered) and recording  uses "void **addr".
"const" is put in place throughout where appropriate.

Most changes are fairly trivial. One that should be checked in
particular because it isn't so much is telechips, if anyone cares to
bother. PP5002 is not so trivial either but that tested as working.

Change-Id: I4928d69b3b3be7fb93e259f81635232df9bd1df2
Reviewed-on: http://gerrit.rockbox.org/166
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>
This commit is contained in:
Michael Sevakis 2012-02-23 08:14:46 -05:00
parent 3f82f3aca1
commit 286a4c5caa
48 changed files with 799 additions and 752 deletions
Download patch file Download diff file Expand all files Collapse all files

20
firmware/target/arm/as3525/pcm-as3525.c
View file

@ -36,9 +36,9 @@
* and the number of 32bits words has to
* fit in 11 bits of DMA register */
static void *dma_start_addr; /* Pointer to callback buffer */
static const void *dma_start_addr; /* Pointer to callback buffer */
static size_t dma_start_size; /* Size of callback buffer */
static void *dma_sub_addr; /* Pointer to sub buffer */
static const void *dma_sub_addr; /* Pointer to sub buffer */
static size_t dma_rem_size; /* Remaining size - in 4*32 bits */
static size_t play_sub_size; /* size of current subtransfer */
static void dma_callback(void);
@ -100,9 +100,8 @@ static void dma_callback(void)
if(!dma_rem_size)
{
pcm_play_get_more_callback(&dma_start_addr, &dma_start_size);
if (!dma_start_size)
if(!pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_start_addr,
&dma_start_size))
return;
dma_sub_addr = dma_start_addr;
@ -111,7 +110,7 @@ static void dma_callback(void)
/* force writeback */
commit_dcache_range(dma_start_addr, dma_start_size);
play_start_pcm();
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
else
{
@ -123,7 +122,7 @@ void pcm_play_dma_start(const void *addr, size_t size)
{
is_playing = true;
dma_start_addr = (void*)addr;
dma_start_addr = addr;
dma_start_size = size;
dma_sub_addr = dma_start_addr;
dma_rem_size = size;
@ -368,7 +367,12 @@ void INT_I2SIN(void)
}
}
pcm_rec_more_ready_callback(0, (void *)&rec_dma_addr, &rec_dma_size);
/* Inform middle layer */
if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, (void **)&rec_dma_addr,
&rec_dma_size))
{
pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
}
}

9
firmware/target/arm/imx233/pcm-imx233.c
View file

@ -49,15 +49,13 @@ static void play(const void *addr, size_t size)
void INT_DAC_DMA(void)
{
void *start;
const void *start;
size_t size;
pcm_play_get_more_callback(&start, &size);
if(size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
{
play(start, size);
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
imx233_dma_clear_channel_interrupt(APB_AUDIO_DAC);
@ -65,6 +63,7 @@ void INT_DAC_DMA(void)
void INT_DAC_ERROR(void)
{
/* TODO: Inform of error through pcm_play_dma_complete_callback */
}
void pcm_play_lock(void)

121
firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
View file

@ -78,12 +78,20 @@ static struct dma_data dma_play_data =
.state = 0
};
static void play_start_dma(const void *addr, size_t size)
{
commit_dcache_range(addr, size);
dma_play_bd.buf_addr = (void *)addr_virt_to_phys((unsigned long)addr);
dma_play_bd.mode.count = size;
dma_play_bd.mode.command = TRANSFER_16BIT;
dma_play_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
sdma_channel_run(DMA_PLAY_CH_NUM);
}
static void play_dma_callback(void)
{
void *start;
size_t size;
bool rror;
if (dma_play_data.locked != 0)
{
/* Callback is locked out */
@ -91,22 +99,17 @@ static void play_dma_callback(void)
return;
}
rror = dma_play_bd.mode.status & BD_RROR;
pcm_play_get_more_callback(rror ? NULL : &start, &size);
if (size == 0)
return;
/* Flush any pending cache writes */
commit_dcache_range(start, size);
dma_play_bd.buf_addr = (void *)addr_virt_to_phys((unsigned long)start);
dma_play_bd.mode.count = size;
dma_play_bd.mode.command = TRANSFER_16BIT;
dma_play_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
sdma_channel_run(DMA_PLAY_CH_NUM);
pcm_play_dma_started_callback();
/* Inform of status and get new buffer */
enum pcm_dma_status status = (dma_play_bd.mode.status & BD_RROR) ?
PCM_DMAST_ERR_DMA : PCM_DMAST_OK;
const void *addr;
size_t size;
if (pcm_play_dma_complete_callback(status, &addr, &size))
{
play_start_dma(addr, size);
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
}
void pcm_play_lock(void)
@ -221,15 +224,11 @@ void pcm_play_dma_start(const void *addr, size_t size)
if (!sdma_channel_reset(DMA_PLAY_CH_NUM))
return;
commit_dcache_range(addr, size);
dma_play_bd.buf_addr =
(void *)addr_virt_to_phys((unsigned long)(void *)addr);
dma_play_bd.mode.count = size;
dma_play_bd.mode.command = TRANSFER_16BIT;
dma_play_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
/* Begin I2S transmission */
play_start_pcm();
sdma_channel_run(DMA_PLAY_CH_NUM);
/* Begin DMA transfer */
play_start_dma(addr, size);
}
void pcm_play_dma_stop(void)
@ -332,37 +331,39 @@ static struct dma_data dma_rec_data =
.state = 0
};
static void rec_start_dma(void *addr, size_t size)
{
discard_dcache_range(addr, size);
addr = (void *)addr_virt_to_phys((unsigned long)addr);
dma_rec_bd.buf_addr = addr;
dma_rec_bd.mode.count = size;
dma_rec_bd.mode.command = TRANSFER_16BIT;
dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
sdma_channel_run(DMA_REC_CH_NUM);
}
static void rec_dma_callback(void)
{
int status = 0;
void *start;
size_t size;
if (dma_rec_data.locked != 0)
{
dma_rec_data.callback_pending = dma_rec_data.state;
return; /* Callback is locked out */
}
if (dma_rec_bd.mode.status & BD_RROR)
status = DMA_REC_ERROR_DMA;
/* Inform middle layer */
enum pcm_dma_status status = (dma_rec_bd.mode.status & BD_RROR) ?
PCM_DMAST_ERR_DMA : PCM_DMAST_OK;
void *addr;
size_t size;
pcm_rec_more_ready_callback(status, &start, &size);
if (size == 0)
return;
/* Invalidate - buffer must be coherent */
discard_dcache_range(start, size);
start = (void *)addr_virt_to_phys((unsigned long)start);
dma_rec_bd.buf_addr = start;
dma_rec_bd.mode.count = size;
dma_rec_bd.mode.command = TRANSFER_16BIT;
dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
sdma_channel_run(DMA_REC_CH_NUM);
if (pcm_rec_dma_complete_callback(status, &addr, &size))
{
rec_start_dma(addr, size);
pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
}
}
void pcm_rec_lock(void)
@ -426,29 +427,21 @@ void pcm_rec_dma_start(void *addr, size_t size)
if (!sdma_channel_reset(DMA_REC_CH_NUM))
return;
/* Invalidate - buffer must be coherent */
discard_dcache_range(addr, size);
addr = (void *)addr_virt_to_phys((unsigned long)addr);
dma_rec_bd.buf_addr = addr;
dma_rec_bd.mode.count = size;
dma_rec_bd.mode.command = TRANSFER_16BIT;
dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
dma_rec_data.state = 1; /* Check callback on unlock */
SSI_SRCR1 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */
/* Ensure clear FIFO */
while (SSI_SFCSR1 & SSI_SFCSR_RFCNT0)
SSI_SRX0_1;
dma_rec_data.state = 1; /* Check callback on unlock */
SSI_SRCR1 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */
/* Enable receive */
SSI_SCR1 |= SSI_SCR_RE;
SSI_SIER1 |= SSI_SIER_RDMAE; /* Enable DMA req. */
sdma_channel_run(DMA_REC_CH_NUM);
/* Begin DMA transfer */
rec_start_dma(addr, size);
}
void pcm_rec_dma_close(void)

62
firmware/target/arm/pcm-telechips.c
View file

@ -33,7 +33,12 @@ struct dma_data
{
/* NOTE: The order of size and p is important if you use assembler
optimised fiq handler, so don't change it. */
uint16_t *p;
union
{
uint16_t *p;
const void *p_r;
void *p_w;
};
size_t size;
#if NUM_CORES > 1
unsigned core;
@ -143,7 +148,7 @@ static void play_stop_pcm(void)
void pcm_play_dma_start(const void *addr, size_t size)
{
dma_play_data.p = (uint16_t*)addr;
dma_play_data.p_r = addr;
dma_play_data.size = size;
#if NUM_CORES > 1
@ -248,8 +253,9 @@ void fiq_handler(void)
* r0-r3 and r12 is a working register.
*/
asm volatile (
"stmfd sp!, { r0-r4, lr } \n" /* stack scratch regs and lr */
"mov r4, #0 \n" /* Was the callback called? */
"sub lr, lr, #4 \n"
"stmfd sp!, { r0-r3, lr } \n" /* stack scratch regs and lr */
"mov r14, #0 \n" /* Was the callback called? */
#if defined(CPU_TCC780X)
"mov r8, #0xc000 \n" /* DAI_TX_IRQ_MASK | DAI_RX_IRQ_MASK */
"ldr r9, =0xf3001004 \n" /* CREQ */
@ -260,7 +266,7 @@ void fiq_handler(void)
"str r8, [r9] \n" /* clear DAI IRQs */
"ldmia r11, { r8-r9 } \n" /* r8 = p, r9 = size */
"cmp r9, #0x10 \n" /* is size <16? */
"blt .more_data \n" /* if so, ask pcmbuf for more data */
"blo .more_data \n" /* if so, ask pcmbuf for more data */
".fill_fifo: \n"
"ldr r12, [r8], #4 \n" /* load two samples */
@ -282,29 +288,30 @@ void fiq_handler(void)
"sub r9, r9, #0x10 \n" /* 4 words written */
"stmia r11, { r8-r9 } \n" /* save p and size */
"cmp r4, #0 \n" /* Callback called? */
"beq .exit \n"
/* "mov r4, #0 \n" If get_more could be called multiple times! */
"ldr r2, =pcm_play_dma_started\n"
"ldr r2, [r2] \n"
"cmp r2, #0 \n"
"blxne r2 \n"
"cmp r14, #0 \n" /* Callback called? */
"ldmeqfd sp!, { r0-r3, pc }^ \n" /* no? -> exit */
".exit: \n"
"ldmfd sp!, { r0-r4, lr } \n"
"subs pc, lr, #4 \n" /* FIQ specific return sequence */
"ldr r1, =pcm_play_status_callback \n"
"ldr r1, [r1] \n"
"cmp r1, #0 \n"
"movne r0, %1 \n"
"blxne r1 \n"
"ldmfd sp!, { r0-r3, pc }^ \n" /* exit */
".more_data: \n"
"mov r4, #1 \n" /* Remember we got more data in this FIQ */
"ldr r2, =pcm_play_get_more_callback \n"
"mov r0, r11 \n" /* r0 = &p */
"add r1, r11, #4 \n" /* r1 = &size */
"blx r2 \n" /* call pcm_play_get_more_callback */
"ldmia r11, { r8-r9 } \n" /* load new p and size */
"cmp r9, #0x10 \n" /* did we actually get enough data? */
"bpl .fill_fifo \n" /* not stop and enough? refill */
"b .exit \n"
"mov r14, #1 \n" /* Remember we got more data in this FIQ */
"mov r0, %0 \n" /* r0 = status */
"mov r1, r11 \n" /* r1 = &dma_play_data.p_r */
"add r2, r11, #4 \n" /* r2 = &dma_play_data.size */
"mov lr, pc \n"
"ldr pc, =pcm_play_dma_complete_callback \n"
"cmp r0, #0 \n" /* any more to play? */
"ldmneia r11, { r8-r9 } \n" /* load new p and size */
"cmpne r9, #0x0f \n" /* did we actually get enough data? */
"bhi .fill_fifo \n" /* not stop and enough? refill */
"ldmfd sp!, { r0-r3, pc }^ \n" /* exit */
".ltorg \n"
: : "i"(PCM_DMAST_OK), "i"(PCM_DMAST_STARTED)
);
}
#else /* C version for reference */
@ -316,9 +323,8 @@ void fiq_handler(void)
if (dma_play_data.size < 16)
{
/* p is empty, get some more data */
new_buffer = true;
pcm_play_get_more_callback((void**)&dma_play_data.p,
&dma_play_data.size);
new_buffer = pcm_play_dma_complete_callback(&dma_play_data.p_r,
&dma_play_data.size);
}
if (dma_play_data.size >= 16)
@ -339,7 +345,7 @@ void fiq_handler(void)
CREQ = DAI_TX_IRQ_MASK | DAI_RX_IRQ_MASK;
if (new_buffer)
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
#endif

14
firmware/target/arm/pnx0101/pcm-pnx0101.c
View file

@ -28,7 +28,7 @@
short __attribute__((section(".dmabuf"))) dma_buf_left[DMA_BUF_SAMPLES];
short __attribute__((section(".dmabuf"))) dma_buf_right[DMA_BUF_SAMPLES];
unsigned short* p IBSS_ATTR;
const int16_t* p IBSS_ATTR;
size_t p_size IBSS_ATTR;
void pcm_play_lock(void)
@ -41,7 +41,7 @@ void pcm_play_unlock(void)
void pcm_play_dma_start(const void *addr, size_t size)
{
p = (unsigned short*)addr;
p = addr;
p_size = size;
}
@ -69,7 +69,7 @@ static inline void fill_dma_buf(int offset)
do
{
int count;
unsigned short *tmp_p;
const int16_t *tmp_p;
count = MIN(p_size / 4, (size_t)(lend - l));
tmp_p = p;
p_size -= count * 4;
@ -109,16 +109,14 @@ static inline void fill_dma_buf(int offset)
if (new_buffer)
{
new_buffer = false;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
if (l >= lend)
return;
pcm_play_get_more_callback((void**)&p, &p_size);
if (p_size)
new_buffer = true;
new_buffer = pcm_play_dma_complete_callback(PCM_DMAST_OK,
&p, &p_size);
}
while (p_size);
}

675
firmware/target/arm/pp/pcm-pp.c
View file

@ -30,26 +30,6 @@
/** DMA **/
#ifdef CPU_PP502x
/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
#define SAMPLE_SIZE 16
/* DMA Requests from IIS, Memory to peripheral, single transfer,
wait for DMA request, interrupt on complete */
#define DMA_PLAY_CONFIG ((DMA_REQ_IIS << DMA_CMD_REQ_ID_POS) | \
DMA_CMD_RAM_TO_PER | DMA_CMD_SINGLE | \
DMA_CMD_WAIT_REQ | DMA_CMD_INTR)
/* DMA status cannot be viewed from outside code in control because that can
* clear the interrupt from outside the handler and prevent the handler from
* from being called. Split up transfers to a reasonable size that is good as
* a timer, obtaining a keyclick position and peaking yet still keeps the
* FIQ count low.
*/
#define MAX_DMA_CHUNK_SIZE (pcm_curr_sampr >> 6) /* ~1/256 seconds */
#else
/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
#define SAMPLE_SIZE 32
#endif
struct dma_data
{
/* NOTE: The order of size and p is important if you use assembler
@ -57,6 +37,8 @@ struct dma_data
union
{
unsigned long addr;
const void *p_r;
void *p_w;
uint32_t *p16; /* For packed 16-16 stereo pairs */
uint16_t *p32; /* For individual samples converted to 32-bit */
};
@ -113,286 +95,72 @@ void pcm_dma_apply_settings(void)
}
#if defined(CPU_PP502x)
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void ICODE_ATTR __attribute__((interrupt("FIQ"))) fiq_playback(void)
{
bool new_buffer = false;
register size_t size;
DMA0_STATUS; /* Clear any pending interrupt */
size = (DMA0_CMD & 0xffff) + 4; /* Get size of trasfer that caused this
interrupt */
dma_play_data.addr += size;
dma_play_data.size -= size;
while (1)
{
if (dma_play_data.size > 0) {
size = MAX_DMA_CHUNK_SIZE;
/* Not at least MAX_DMA_CHUNK_SIZE left or there would be less
* than a FIFO's worth of data after this transfer? */
if (size + 16*4 > dma_play_data.size)
size = dma_play_data.size;
/* Set the new DMA values and activate channel */
DMA0_RAM_ADDR = dma_play_data.addr;
DMA0_CMD = DMA_PLAY_CONFIG | (size - 4) | DMA_CMD_START;
if (new_buffer)
pcm_play_dma_started_callback();
return;
}
new_buffer = true;
/* Buffer empty. Try to get more. */
pcm_play_get_more_callback((void **)&dma_play_data.addr,
&dma_play_data.size);
if (dma_play_data.size == 0) {
/* No more data */
return;
}
if (dma_play_data.addr < UNCACHED_BASE_ADDR) {
/* Flush any pending cache writes */
dma_play_data.addr = UNCACHED_ADDR(dma_play_data.addr);
commit_dcache();
}
}
}
#else
/* ASM optimised FIQ handler. Checks for the minimum allowed loop cycles by
* evalutation of free IISFIFO-slots against available source buffer words.
* Through this it is possible to move the check for IIS_TX_FREE_COUNT outside
* the loop and do some further optimization. Right after the loops (source
* buffer -> IISFIFO) are done we need to check whether we have to exit FIQ
* handler (this must be done, if all free FIFO slots were filled) or we will
* have to get some new source data. Important information kept from former
* ASM implementation (not used anymore): GCC fails to make use of the fact
* that FIQ mode has registers r8-r14 banked, and so does not need to be saved.
* This routine uses only these registers, and so will never touch the stack
* unless it actually needs to do so when calling pcm_callback_for_more.
* C version is still included below for reference and testing.
/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
#define SAMPLE_SIZE 16
/* DMA Requests from IIS, Memory to peripheral, single transfer,
wait for DMA request, interrupt on complete */
#define DMA_PLAY_CONFIG ((DMA_REQ_IIS << DMA_CMD_REQ_ID_POS) | \
DMA_CMD_RAM_TO_PER | DMA_CMD_SINGLE | \
DMA_CMD_WAIT_REQ | DMA_CMD_INTR)
/* DMA status cannot be viewed from outside code in control because that can
* clear the interrupt from outside the handler and prevent the handler from
* from being called. Split up transfers to a reasonable size that is good as
* a timer and peaking yet still keeps the FIQ count low.
*/
#if 1
void fiq_playback(void) ICODE_ATTR __attribute__((naked));
void fiq_playback(void)
#define MAX_DMA_CHUNK_SIZE (pcm_curr_sampr >> 6) /* ~1/256 seconds */
static inline void dma_tx_init(void)
{
/* r10 contains IISCONFIG address (set in crt0.S to minimise code in actual
* FIQ handler. r11 contains address of p (also set in crt0.S). Most other
* addresses we need are generated by using offsets with these two.
* r10 + 0x40 is IISFIFO_WR, and r10 + 0x0c is IISFIFO_CFG.
* r8 and r9 contains local copies of p and size respectively.
* r0-r3 and r12 is a working register.
*/
asm volatile (
"stmfd sp!, { r0-r4, lr } \n" /* stack scratch regs and lr */
"mov r4, #0 \n" /* Was the callback called? */
#if CONFIG_CPU == PP5002
"ldr r12, =0xcf001040 \n" /* Some magic from iPodLinux */
"ldr r12, [r12] \n"
#endif
"ldmia r11, { r8-r9 } \n" /* r8 = p, r9 = size */
"cmp r9, #0 \n" /* is size 0? */
"beq .more_data \n" /* if so, ask pcmbuf for more data */
#if SAMPLE_SIZE == 16
".check_fifo: \n"
"ldr r0, [r10, %[cfg]] \n" /* read IISFIFO_CFG to check FIFO status */
"and r0, r0, %[mask] \n" /* r0 = IIS_TX_FREE_COUNT << 16 (PP502x) */
"mov r1, r0, lsr #16 \n" /* number of free FIFO slots */
"cmp r1, r9, lsr #2 \n" /* number of words from source */
"movgt r1, r9, lsr #2 \n" /* r1 = amount of allowed loops */
"sub r9, r9, r1, lsl #2 \n" /* r1 words will be written in following loop */
"subs r1, r1, #2 \n"
".fifo_loop_2: \n"
"ldmgeia r8!, {r2, r12} \n" /* load four samples */
"strge r2 , [r10, %[wr]] \n" /* write sample 0-1 to IISFIFO_WR */
"strge r12, [r10, %[wr]] \n" /* write sample 2-3 to IISFIFO_WR */
"subges r1, r1, #2 \n" /* one more loop? */
"bge .fifo_loop_2 \n" /* yes, continue */
"tst r1, #1 \n" /* two samples (one word) left? */
"ldrne r12, [r8], #4 \n" /* load two samples */
"strne r12, [r10, %[wr]] \n" /* write sample 0-1 to IISFIFO_WR */
#elif SAMPLE_SIZE == 32
".check_fifo: \n"
"ldr r0, [r10, %[cfg]] \n" /* read IISFIFO_CFG to check FIFO status */
"and r0, r0, %[mask] \n" /* r0 = IIS_TX_FREE_COUNT << 23 (PP5002) */
"movs r1, r0, lsr #24 \n" /* number of free pairs of FIFO slots */
"beq .fifo_fill_complete \n" /* no complete pair? -> exit */
"cmp r1, r9, lsr #2 \n" /* number of words from source */
"movgt r1, r9, lsr #2 \n" /* r1 = amount of allowed loops */
"sub r9, r9, r1, lsl #2 \n" /* r1 words will be written in following loop */
".fifo_loop: \n"
"ldr r12, [r8], #4 \n" /* load two samples */
"mov r2 , r12, lsl #16 \n" /* put left sample at the top bits */
"str r2 , [r10, %[wr]] \n" /* write top sample to IISFIFO_WR */
"str r12, [r10, %[wr]] \n" /* write low sample to IISFIFO_WR*/
"subs r1, r1, #1 \n" /* one more loop? */
"bgt .fifo_loop \n" /* yes, continue */
".fifo_fill_complete: \n"
#endif
"cmp r4, #0 \n" /* If fill came after get_more... */
"beq .still_old_buffer \n"
"mov r4, #0 \n"
"ldr r2, =pcm_play_dma_started \n"
"ldrne r2, [r2] \n"
"cmp r2, #0 \n"
"movne lr, pc \n"
"bxne r2 \n"
".still_old_buffer: \n"
"cmp r9, #0 \n" /* either FIFO is full or source buffer is empty */
"bgt .exit \n" /* if source buffer is not empty, FIFO must be full */
".more_data: \n"
"mov r4, #1 \n" /* Remember we did this */
"ldr r2, =pcm_play_get_more_callback \n"
"mov r0, r11 \n" /* r0 = &p */
"add r1, r11, #4 \n" /* r1 = &size */
"mov lr, pc \n" /* call pcm_play_get_more_callback */
"bx r2 \n"
"ldmia r11, { r8-r9 } \n" /* load new p and size */
"cmp r9, #0 \n"
"bne .check_fifo \n" /* size != 0? refill */
".exit: \n" /* (r9=0 if stopping, look above) */
"stmia r11, { r8-r9 } \n" /* save p and size */
"ldmfd sp!, { r0-r4, lr } \n"
"subs pc, lr, #4 \n" /* FIQ specific return sequence */
".ltorg \n"
: /* These must only be integers! No regs */
: [mask]"i"(IIS_TX_FREE_MASK),
[cfg]"i"((int)&IISFIFO_CFG - (int)&IISCONFIG),
[wr]"i"((int)&IISFIFO_WR - (int)&IISCONFIG)
);
/* Enable DMA controller */
DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN;
/* FIQ priority for DMA */
CPU_INT_PRIORITY |= DMA_MASK;
/* Enable request?? Not setting or clearing everything doesn't seem to
* prevent it operating. Perhaps important for reliability (how requests
* are handled). */
DMA_REQ_STATUS |= 1ul << DMA_REQ_IIS;
DMA0_STATUS;
}
#else /* C version for reference */
void fiq_playback(void) __attribute__((interrupt ("FIQ"))) ICODE_ATTR;
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void fiq_playback(void)
static inline void dma_tx_setup(void)
{
bool new_buffer = false;
#if CONFIG_CPU == PP5002
inl(0xcf001040);
#endif
do {
while (dma_play_data.size > 0) {
if (IIS_TX_FREE_COUNT < 2) {
if (new_buffer) {
new_buffer = false;
pcm_play_dma_started_callback();
}
return;
}
#if SAMPLE_SIZE == 16
IISFIFO_WR = *dma_play_data.p16++;
#elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p32++ << 16;
IISFIFO_WR = *dma_play_data.p32++ << 16;
#endif
dma_play_data.size -= 4;
}
if (new_buffer) {
new_buffer = false;
pcm_play_dma_started_callback();
}
/* p is empty, get some more data */
pcm_play_get_more_callback((void **)&dma_play_data.addr,
&dma_play_data.size);
new_buffer = true;
} while (dma_play_data.size);
/* No more data */
/* Setup DMA controller */
DMA0_PER_ADDR = (unsigned long)&IISFIFO_WR;
DMA0_FLAGS = DMA_FLAGS_UNK26;
DMA0_INCR = DMA_INCR_RANGE_FIXED | DMA_INCR_WIDTH_32BIT;
}
#endif /* ASM / C selection */
#endif /* CPU_PP502x */
/* For the locks, FIQ must be disabled because the handler manipulates
IISCONFIG and the operation is not atomic - dual core support
will require other measures */
void pcm_play_lock(void)
static inline unsigned long dma_tx_buf_prepare(const void *addr)
{
int status = disable_fiq_save();
unsigned long a = (unsigned long)addr;
if (++dma_play_data.locked == 1) {
#ifdef CPU_PP502x
CPU_INT_DIS = DMA_MASK;
#else
IIS_IRQTX_REG &= ~IIS_IRQTX;
#endif
if (a < UNCACHED_BASE_ADDR) {
/* VA in DRAM - writeback all data and get PA */
a = UNCACHED_ADDR(a);
commit_dcache();
}
restore_fiq(status);
return a;
}
void pcm_play_unlock(void)
static inline void dma_tx_start(bool begin)
{
int status = disable_fiq_save();
if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
#ifdef CPU_PP502x
CPU_INT_EN = DMA_MASK;
#else
IIS_IRQTX_REG |= IIS_IRQTX;
#endif
}
restore_fiq(status);
}
static void play_start_pcm(void)
{
fiq_function = fiq_playback;
#ifdef CPU_PP502x
/* Not at least MAX_DMA_CHUNK_SIZE left or there would be less than a
* FIFO's worth of data after this transfer? */
size_t size = MAX_DMA_CHUNK_SIZE;
/* Not at least MAX_DMA_CHUNK_SIZE left or there would be less
* than a FIFO's worth of data after this transfer? */
if (size + 16*4 > dma_play_data.size)
size = dma_play_data.size;
/* Set the new DMA values and activate channel */
DMA0_RAM_ADDR = dma_play_data.addr;
DMA0_CMD = DMA_PLAY_CONFIG | (size - 4) | DMA_CMD_START;
dma_play_data.state = 1;
#else
IISCONFIG &= ~IIS_TXFIFOEN; /* Stop transmitting */
/* Fill the FIFO or start when data is used up */
while (1) {
if (IIS_TX_FREE_COUNT < 2 || dma_play_data.size == 0) {
IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
dma_play_data.state = 1;
return;
}
#if SAMPLE_SIZE == 16
IISFIFO_WR = *dma_play_data.p16++;
#elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p32++ << 16;
IISFIFO_WR = *dma_play_data.p32++ << 16;
#endif
dma_play_data.size -= 4;
}
#endif
(void)begin;
}
static void play_stop_pcm(void)
static void dma_tx_stop(void)
{
#ifdef CPU_PP502x
unsigned long status = DMA0_STATUS; /* Snapshot- resume from this point */
unsigned long cmd = DMA0_CMD;
size_t size = 0;
@ -420,10 +188,281 @@ static void play_stop_pcm(void)
if (dma_play_data.size == 0)
dma_play_data.addr = 0; /* Entire buffer has completed. */
#else
}
static inline void dma_tx_lock(void)
{
CPU_INT_DIS = DMA_MASK;
}
static inline void dma_tx_unlock(void)
{
CPU_INT_EN = DMA_MASK;
}
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void fiq_playback(void) ICODE_ATTR __attribute__((interrupt("FIQ")));
void fiq_playback(void)
{
DMA0_STATUS; /* Clear any pending interrupt */
size_t size = (DMA0_CMD & 0xffff) + 4; /* Get size of trasfer that caused
this interrupt */
dma_play_data.addr += size;
dma_play_data.size -= size;
if (LIKELY(dma_play_data.size != 0)) {
/* Begin next segment */
dma_tx_start(false);
}
else if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_play_data.p_r,
&dma_play_data.size)) {
dma_play_data.addr = dma_tx_buf_prepare(dma_play_data.p_r);
dma_tx_start(false);
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
}
#else /* !defined (CPU_PP502x) */
/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
#define SAMPLE_SIZE 32
static void dma_tx_init(void)
{
/* Set up banked registers for FIQ mode */
/* Use non-banked registers for scratch. */
register volatile void *iiscfg asm("r0") = &IISCONFIG;
register volatile void *dmapd asm("r1") = &dma_play_data;
asm volatile (
"mrs r2, cpsr \n" /* Save mode and interrupt status */
"msr cpsr_c, #0xd1 \n" /* Switch to FIQ mode */
"mov r8, #0 \n"
"mov r9, #0 \n"
"mov r10, %[iiscfg] \n"
"mov r11, %[dmapd] \n"
"msr cpsr_c, r2 \n"
:
: [iiscfg]"r"(iiscfg), [dmapd]"r"(dmapd)
: "r2");
/* FIQ priority for I2S */
CPU_INT_PRIORITY |= IIS_MASK;
CPU_INT_EN = IIS_MASK;
}
static inline void dma_tx_setup(void)
{
/* Nothing to do */
}
static inline unsigned long dma_tx_buf_prepare(const void *addr)
{
return (unsigned long)addr;
}
static inline void dma_tx_start(bool begin)
{
if (begin) {
IISCONFIG &= ~IIS_TXFIFOEN; /* Stop transmitting */
}
/* Fill the FIFO or start when data is used up */
while (IIS_TX_FREE_COUNT >= 2 && dma_play_data.size != 0) {
IISFIFO_WRH = *dma_play_data.p32++;
IISFIFO_WRH = *dma_play_data.p32++;
dma_play_data.size -= 4;
}
if (begin) {
IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
}
}
static inline void dma_tx_stop(void)
{
/* Disable TX interrupt */
IIS_IRQTX_REG &= ~IIS_IRQTX;
#endif
}
static inline void dma_tx_lock(void)
{
IIS_IRQTX_REG &= ~IIS_IRQTX;
}
static inline void dma_tx_unlock(void)
{
IIS_IRQTX_REG |= IIS_IRQTX;
}
/* ASM optimised FIQ handler. Checks for the minimum allowed loop cycles by
* evalutation of free IISFIFO-slots against available source buffer words.
* Through this it is possible to move the check for IIS_TX_FREE_COUNT outside
* the loop and do some further optimization. Right after the loops (source
* buffer -> IISFIFO) are done we need to check whether we have to exit FIQ
* handler (this must be done, if all free FIFO slots were filled) or we will
* have to get some new source data. Important information kept from former
* ASM implementation (not used anymore): GCC fails to make use of the fact
* that FIQ mode has registers r8-r14 banked, and so does not need to be saved.
* This routine uses only these registers, and so will never touch the stack
* unless it actually needs to do so when calling pcm_play_dma_complete_callback.
* C version is still included below for reference and testing.
*/
#if 1
void fiq_playback(void) ICODE_ATTR __attribute__((naked));
void fiq_playback(void)
{
/* r8 and r9 contains local copies of p and size respectively.
* r10 contains IISCONFIG address (set during PCM init to minimize code in
* FIQ handler.Most other addresses we need are generated by using offsets
* from this.
* r10 + 0x40 is IISFIFO_WR, and r10 + 0x1c is IISFIFO_CFG.
* r11 contains address of dma_play_data
* r12 and r14 are working registers.
*
* Divided into two blocks: one where no external calls are needed and
* one where external callbacks are made
*/
asm volatile (
/* No external calls */
"sub lr, lr, #4 \n" /* Prepare return address */
"stmfd sp!, { lr } \n" /* stack lr so we can use it */
"ldr r12, =0xcf001040 \n" /* Some magic from iPodLinux ... */
"ldr r12, [r12] \n" /* ... actually a DMA INT ack? */
"ldmia r11, { r8-r9 } \n" /* r8 = p, r9 = size */
"cmp r9, #0 \n" /* is size 0? */
"beq 1f \n" /* if so, ask PCM for more data */
"ldr r14, [r10, #0x1c] \n" /* read IISFIFO_CFG to check FIFO status */
"and r14, r14, #(0xe<<23) \n" /* r14 = (IIS_TX_FREE_COUNT & ~1) << 23 */
"cmp r9, r14, lsr #22 \n" /* number of words from source */
"movlo r14, r9, lsl #22 \n" /* r14 = amount of allowed loops */
"sub r9, r9, r14, lsr #22 \n" /* r14 words will be written in loop */
"0: \n"
"ldr r12, [r8], #4 \n" /* load left-right pair */
"subs r14, r14, #(0x2<<23) \n" /* one more loop? ... */
"strh r12, [r10, #0x40] \n" /* left sample to IISFIFO_WR */
"mov r12, r12, lsr #16 \n" /* put right sample in bottom 16 bits */
"strh r12, [r10, #0x40] \n" /* right sample to IISFIFO_WR */
"bhi 0b \n" /* ... yes, continue */
"cmp r9, #0 \n" /* either FIFO full or size empty? */
"stmneia r11, { r8-r9 } \n" /* save p and size, if not empty */
"ldmnefd sp!, { pc }^ \n" /* RFE if not empty */
/* Making external calls */
"1: \n"
"stmfd sp!, { r0-r3 } \n" /* Must save volatiles */
"2: \n"
"mov r0, %0 \n" /* r0 = status */
"mov r1, r11 \n" /* r1 = &dma_play_data.p_r */
"add r2, r11, #4 \n" /* r2 = &dma_play_data.size */
"ldr r3, =pcm_play_dma_complete_callback \n"
"mov lr, pc \n" /* long call (not in same section) */
"bx r3 \n"
"cmp r0, #0 \n" /* more data? */
"ldmeqfd sp!, { r0-r3, pc }^ \n" /* no? -> exit */
"ldr r14, [r10, #0x1c] \n" /* read IISFIFO_CFG to check FIFO status */
"ands r14, r14, #(0xe<<23) \n" /* r14 = (IIS_TX_FREE_COUNT & ~1) << 23 */
"bne 4f \n"
"3: \n" /* inform of started status if registered */
"ldr r1, =pcm_play_status_callback \n"
"ldr r1, [r1] \n"
"cmp r1, #0 \n"
"movne r0, %1 \n"
"movne lr, pc \n"
"bxne r1 \n"
"ldmfd sp!, { r0-r3, pc }^ \n" /* exit */
"4: \n"
"ldmia r11, { r8-r9 } \n" /* load new p and size */
"cmp r9, r14, lsr #22 \n" /* number of words from source */
"movlo r14, r9, lsl #22 \n" /* r14 = amount of allowed loops */
"sub r9, r9, r14, lsr #22 \n" /* r14 words will be written in loop */
"0: \n"
"ldr r12, [r8], #4 \n" /* load left-right pair */
"subs r14, r14, #(0x2<<23) \n" /* one more loop? ... */
"strh r12, [r10, #0x40] \n" /* left sample to IISFIFO_WR */
"mov r12, r12, lsr #16 \n" /* put right sample in bottom 16 bits */
"strh r12, [r10, #0x40] \n" /* right sample to IISFIFO_WR */
"bhi 0b \n" /* ... yes, continue */
"stmia r11, { r8-r9 } \n" /* save p and size */
"cmp r9, #0 \n" /* used up data in FIFO fill? */
"bne 3b \n" /* no? -> go return */
"b 2b \n" /* yes -> get even more */
".ltorg \n"
: /* These must only be integers! No regs */
: "i"(PCM_DMAST_OK), "i"(PCM_DMAST_STARTED));
}
#else /* C version for reference */
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void fiq_playback(void) ICODE_ATTR __attribute__((interrupt ("FIQ")));
void fiq_playback(void)
{
inl(0xcf001040);
if (LIKELY(dma_play_data.size != 0)) {
dma_tx_start(false);
if (dma_play_data.size != 0) {
/* Still more data */
return;
}
}
while (pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_play_data.p_r,
&dma_play_data.size)) {
dma_tx_start(false);
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
if (dma_play_data.size != 0) {
return;
}
}
}
#endif /* ASM / C selection */
#endif /* CPU_PP502x */
/* For the locks, FIQ must be disabled because the handler manipulates
IISCONFIG and the operation is not atomic - dual core support
will require other measures */
void pcm_play_lock(void)
{
int status = disable_fiq_save();
if (++dma_play_data.locked == 1) {
dma_tx_lock();
}
restore_fiq(status);
}
void pcm_play_unlock(void)
{
int status = disable_fiq_save();
if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
dma_tx_unlock();
}
restore_fiq(status);
}
static void play_start_pcm(void)
{
fiq_function = fiq_playback;
dma_play_data.state = 1;
dma_tx_start(true);
}
static void play_stop_pcm(void)
{
dma_tx_stop();
/* Wait for FIFO to empty */
while (!IIS_TX_IS_EMPTY);
@ -433,30 +472,17 @@ static void play_stop_pcm(void)
void pcm_play_dma_start(const void *addr, size_t size)
{
pcm_play_dma_stop();
#if NUM_CORES > 1
/* This will become more important later - and different ! */
dma_play_data.core = processor_id(); /* save initiating core */
#endif
pcm_play_dma_stop();
dma_tx_setup();
#ifdef CPU_PP502x
if ((unsigned long)addr < UNCACHED_BASE_ADDR) {
/* Flush any pending cache writes */
addr = UNCACHED_ADDR(addr);
commit_dcache();
}
dma_play_data.addr = (unsigned long)addr;
dma_play_data.addr = dma_tx_buf_prepare(addr);
dma_play_data.size = size;
DMA0_PER_ADDR = (unsigned long)&IISFIFO_WR;
DMA0_FLAGS = DMA_FLAGS_UNK26;
DMA0_INCR = DMA_INCR_RANGE_FIXED | DMA_INCR_WIDTH_32BIT;
#else
dma_play_data.addr = (unsigned long)addr;
dma_play_data.size = size;
#endif
play_start_pcm();
}
@ -490,39 +516,7 @@ void pcm_play_dma_init(void)
/* Initialize default register values. */
audiohw_init();
#ifdef CPU_PP502x
/* Enable DMA controller */
DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN;
/* FIQ priority for DMA */
CPU_INT_PRIORITY |= DMA_MASK;
/* Enable request?? Not setting or clearing everything doesn't seem to
* prevent it operating. Perhaps important for reliability (how requests
* are handled). */
DMA_REQ_STATUS |= 1ul << DMA_REQ_IIS;
DMA0_STATUS;
#else
/* Set up banked registers for FIQ mode */
/* Use non-banked registers for scratch. */
register volatile void *iiscfg asm("r0") = &IISCONFIG;
register volatile void *dmapd asm("r1") = &dma_play_data;
asm volatile (
"mrs r2, cpsr \n" /* Save mode and interrupt status */
"msr cpsr_c, #0xd1 \n" /* Switch to FIQ mode */
"mov r8, #0 \n"
"mov r9, #0 \n"
"mov r10, %[iiscfg] \n"
"mov r11, %[dmapd] \n"
"msr cpsr_c, r2 \n"
:
: [iiscfg]"r"(iiscfg), [dmapd]"r"(dmapd)
: "r2");
/* FIQ priority for I2S */
CPU_INT_PRIORITY |= IIS_MASK;
CPU_INT_EN = IIS_MASK;
#endif
dma_tx_init();
IISCONFIG |= IIS_TXFIFOEN;
}
@ -649,11 +643,15 @@ void fiq_record(void)
}
}
pcm_rec_more_ready_callback(0, (void *)&dma_rec_data.addr,
&dma_rec_data.size);
if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, &dma_rec_data.p_w,
&dma_rec_data.size))
{
pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
}
}
#else
#else /* !(SANSA_C200 || SANSA_E200) */
void fiq_record(void)
{
while (dma_rec_data.size > 0) {
@ -664,17 +662,20 @@ void fiq_record(void)
#if SAMPLE_SIZE == 16
*dma_rec_data.p16++ = IISFIFO_RD;
#elif SAMPLE_SIZE == 32
*dma_rec_data.p32++ = IISFIFO_RD >> 16;
*dma_rec_data.p32++ = IISFIFO_RD >> 16;
*dma_rec_data.p32++ = IISFIFO_RDH;
*dma_rec_data.p32++ = IISFIFO_RDH;
#endif
dma_rec_data.size -= 4;
}
pcm_rec_more_ready_callback(0, (void *)&dma_rec_data.addr,
&dma_rec_data.size);
if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, &dma_rec_data.p_w,
&dma_rec_data.size))
{
pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
}
}
#endif /* SANSA_E200 */
#endif /* SANSA_C200 || SANSA_E200 */
void pcm_rec_dma_stop(void)
{

8
firmware/target/arm/rk27xx/pcm-rk27xx.c
View file

@ -273,15 +273,13 @@ size_t pcm_get_bytes_waiting(void)
/* audio DMA ISR called when chunk from callers buffer has been transfered */
void INT_HDMA(void)
{
void *start;
const void *start;
size_t size;
pcm_play_get_more_callback(&start, &size);
if (size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
{
hdma_i2s_transfer(start, size);
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
}

8
firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
View file

@ -215,16 +215,14 @@ void pcm_play_dma_pause(bool pause)
void fiq_handler(void)
{
static void *start;
static const void *start;
static size_t size;
/* clear any pending interrupt */
SRCPND = DMA2_MASK;
/* Buffer empty. Try to get more. */
pcm_play_get_more_callback(&start, &size);
if (size == 0)
if (!pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
return;
/* Flush any pending cache writes */
@ -237,7 +235,7 @@ void fiq_handler(void)
/* Re-Activate the channel */
DMASKTRIG2 = 0x2;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
size_t pcm_get_bytes_waiting(void)

8
firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
View file

@ -255,16 +255,14 @@ void pcm_play_dma_pause(bool pause)
void fiq_handler(void)
{
static void *start;
static const void *start;
static size_t size;
/* clear any pending interrupt */
SRCPND = DMA2_MASK;
/* Buffer empty. Try to get more. */
pcm_play_get_more_callback(&start, &size);
if (size == 0)
if (!pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
return;
/* Flush any pending cache writes */
@ -277,7 +275,7 @@ void fiq_handler(void)
/* Re-Activate the channel */
DMASKTRIG2 = 0x2;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
size_t pcm_get_bytes_waiting(void)

9
firmware/target/arm/s5l8700/pcm-s5l8700.c
View file

@ -116,9 +116,10 @@ void INT_DMA(void)
{
if (!nextsize)
{
pcm_play_get_more_callback((void**)&nextbuf, &nextsize);
if (!nextsize) break;
new_buffer = true;
new_buffer = pcm_play_dma_complete_callback(PCM_DMAST_OK,
(const void**)&nextbuf, &nextsize);
if (!new_buffer)
break;
}
queuedsize = MIN(sizeof(dblbuf), nextsize / 2);
nextsize -= queuedsize;
@ -133,7 +134,7 @@ void INT_DMA(void)
if (new_buffer)
{
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
new_buffer = false;
}
}

4
firmware/target/arm/s5l8702/pcm-s5l8702.c
View file

@ -65,7 +65,7 @@ void INT_DMAC0C0(void)
DMAC0INTTCCLR = 1;
if (!pcm_remaining)
{
pcm_play_get_more_callback((void**)&dataptr, &pcm_remaining);
pcm_play_dma_complete_callback((const void**)&dataptr, &pcm_remaining);
pcm_chunksize = pcm_remaining;
}
if (!pcm_remaining)
@ -115,7 +115,7 @@ void INT_DMAC0C0(void)
}
else DMAC0C0NEXTLLI = pcm_lli;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
void pcm_play_dma_start(const void* addr, size_t size)

8
firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c
View file

@ -33,7 +33,7 @@
/* This is global to save some latency when pcm_play_dma_get_peak_buffer is
* called.
*/
static void *start;
static const void *start;
void pcm_play_dma_postinit(void)
{
@ -164,9 +164,7 @@ void DSPHINT(void)
case MSG_REFILL:
/* Buffer empty. Try to get more. */
pcm_play_get_more_callback(&start, &size);
if (size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
{
unsigned long sdem_addr=(unsigned long)start - CONFIG_SDRAM_START;
/* Flush any pending cache writes */
@ -180,7 +178,7 @@ void DSPHINT(void)
DEBUGF("pcm_sdram at 0x%08lx, sdem_addr 0x%08lx",
(unsigned long)start, (unsigned long)sdem_addr);
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
break;

8
firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c
View file

@ -34,7 +34,7 @@
/* This is global to save some latency when pcm_play_dma_get_peak_buffer is
* called.
*/
static void *start;
static const void *start;
static int dma_channel;
void pcm_play_dma_postinit(void)
@ -171,9 +171,7 @@ void DSPHINT(void)
case MSG_REFILL:
/* Buffer empty. Try to get more. */
pcm_play_get_more_callback(&start, &size);
if (size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
{
unsigned long sdem_addr=(unsigned long)start - CONFIG_SDRAM_START;
/* Flush any pending cache writes */
@ -187,7 +185,7 @@ void DSPHINT(void)
DEBUGF("pcm_sdram at 0x%08lx, sdem_addr 0x%08lx",
(unsigned long)start, (unsigned long)sdem_addr);
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
break;

36
firmware/target/coldfire/pcm-coldfire.c
View file

@ -294,8 +294,6 @@ void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
void DMA0(void)
{
unsigned long res = DSR0;
void *start;
size_t size;
and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
DSR0 = 1; /* Clear interrupt and errors */
@ -311,17 +309,18 @@ void DMA0(void)
#endif
}
/* Force stop on error */
pcm_play_get_more_callback((res & 0x70) ? NULL : &start, &size);
const void *addr;
size_t size;
if (size != 0)
if (pcm_play_dma_complete_callback((res & 0x70) ?
PCM_DMAST_ERR_DMA : PCM_DMAST_OK,
&addr, &size))
{
SAR0 = (unsigned long)start; /* Source address */
BCR0 = size; /* Bytes to transfer */
SAR0 = (unsigned long)addr; /* Source address */
BCR0 = (unsigned long)size; /* Bytes to transfer */
or_l(DMA_EEXT | DMA_INT, &DCR0); /* per request and int ON */
/* Call buffer callback */
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
/* else inished playing */
} /* DMA0 */
@ -368,7 +367,7 @@ void pcm_rec_unlock(void)
void pcm_rec_dma_start(void *addr, size_t size)
{
/* stop any DMA in progress */
/* Stop any DMA in progress */
pcm_rec_dma_stop();
and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
@ -430,16 +429,14 @@ void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
void DMA1(void)
{
unsigned long res = DSR1;
int status = 0;
void *start;
size_t size;
enum pcm_dma_status status = PCM_DMAST_OK;
and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
DSR1 = 1; /* Clear interrupt and errors */
if (res & 0x70)
{
status = DMA_REC_ERROR_DMA;
status = PCM_DMAST_ERR_DMA;
logf("DMA1 err: %02x", res);
#if 0
logf(" SAR1: %08x", SAR1);
@ -456,19 +453,22 @@ void DMA1(void)
* Ignore valnogood since several sources don't set it properly. */
/* clear: ebu1cnew, symbolerr, parityerr */
INTERRUPTCLEAR = (1 << 25) | (1 << 23) | (1 << 22);
status = DMA_REC_ERROR_SPDIF;
status = PCM_DMAST_ERR_SPDIF;
logf("spdif err");
}
#endif
/* Inform PCM we have more data (or error) */
pcm_rec_more_ready_callback(status, &start, &size);
void *addr;
size_t size;
if (size != 0)
if (pcm_rec_dma_complete_callback(status, &addr, &size))
{
DAR1 = (unsigned long)start; /* Destination address */
DAR1 = (unsigned long)addr; /* Destination address */
BCR1 = (unsigned long)size; /* Bytes to transfer */
or_l(DMA_EEXT | DMA_INT, &DCR1); /* per request and int ON */
pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
}
} /* DMA1 */

16
firmware/target/hosted/android/pcm-android.c
View file

@ -80,8 +80,8 @@ Java_org_rockbox_RockboxPCM_nativeWrite(JNIEnv *env, jobject this,
if (!pcm_data_size) /* get some initial data */
{
new_buffer = true;
pcm_play_get_more_callback((void**) &pcm_data_start, &pcm_data_size);
new_buffer = pcm_play_dma_complete_callback(PCM_DMAST_OK,
(const void**)&pcm_data_start, &pcm_data_size);
}
while(left > 0 && pcm_data_size)
@ -99,7 +99,7 @@ Java_org_rockbox_RockboxPCM_nativeWrite(JNIEnv *env, jobject this,
if (new_buffer)
{
new_buffer = false;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
/* NOTE: might need to release the mutex and sleep here if the
buffer is shorter than the required buffer (like pcm-sdl.c) to
@ -114,15 +114,15 @@ Java_org_rockbox_RockboxPCM_nativeWrite(JNIEnv *env, jobject this,
if (pcm_data_size == 0) /* need new data */
{
new_buffer = true;
pcm_play_get_more_callback((void**)&pcm_data_start, &pcm_data_size);
new_buffer = pcm_play_dma_complete_callback(PCM_DMAST_OK,
(const void**)&pcm_data_start, &pcm_data_size);
}
else /* increment data pointer and feed more */
pcm_data_start += transfer_size;
}
if (new_buffer && pcm_data_size)
pcm_play_dma_started_callback();
if (new_buffer)
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
unlock_audio();
return max_size - left;
@ -154,7 +154,7 @@ void pcm_play_dma_start(const void *addr, size_t size)
void pcm_play_dma_stop(void)
{
/* NOTE: due to how pcm_play_get_more_callback() works, this is
/* NOTE: due to how pcm_play_dma_complete_callback() works, this is
* possibly called from nativeWrite(), i.e. another (host) thread
* => need to discover the appropriate JNIEnv* */
JNIEnv* env = getJavaEnvironment();

7
firmware/target/hosted/maemo/pcm-gstreamer.c
View file

@ -189,9 +189,8 @@ static void feed_data(GstElement * appsrc, guint size_hint, void *unused)
from inside gstreamer's stream thread as it will deadlock */
inside_feed_data = 1;
pcm_play_get_more_callback((void **)&pcm_data, &pcm_data_size);
if (pcm_data_size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, (const void **)&pcm_data,
&pcm_data_size))
{
GstBuffer *buffer = gst_buffer_new ();
GstFlowReturn ret;
@ -205,7 +204,7 @@ static void feed_data(GstElement * appsrc, guint size_hint, void *unused)
if (ret != 0)
DEBUGF("push-buffer error result: %d\n", ret);
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
} else
{
DEBUGF("feed_data: No Data.\n");

8
firmware/target/hosted/pcm-alsa.c
View file

@ -223,9 +223,11 @@ static bool fill_frames(void)
if (!pcm_size)
{
new_buffer = true;
pcm_play_get_more_callback((void **)&pcm_data, &pcm_size);
if (!pcm_size || !pcm_data)
if (!pcm_play_dma_complete_callback(PCM_DMAST_OK,
(const void **)&pcm_data, &pcm_size))
{
return false;
}
}
copy_n = MIN((ssize_t)pcm_size, frames_left*4);
memcpy(&frames[2*(period_size-frames_left)], pcm_data, copy_n);
@ -237,7 +239,7 @@ static bool fill_frames(void)
if (new_buffer)
{
new_buffer = false;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
}
return true;

80
firmware/target/hosted/sdl/pcm-sdl.c
View file

@ -56,7 +56,7 @@ static int sim_volume = 0;
#if CONFIG_CODEC == SWCODEC
static int cvt_status = -1;
static Uint8* pcm_data;
static const Uint8* pcm_data;
static size_t pcm_data_size;
static size_t pcm_sample_bytes;
static size_t pcm_channel_bytes;
@ -109,7 +109,7 @@ void pcm_play_dma_start(const void *addr, size_t size)
{
pcm_dma_apply_settings_nolock();
pcm_data = (Uint8 *) addr;
pcm_data = addr;
pcm_data_size = size;
SDL_PauseAudio(0);
@ -245,48 +245,48 @@ static void sdl_audio_callback(struct pcm_udata *udata, Uint8 *stream, int len)
/* Audio card wants more? Get some more then. */
while (len > 0) {
new_buffer = true;
pcm_play_get_more_callback((void **)&pcm_data, &pcm_data_size);
start:
if (pcm_data_size != 0) {
udata->num_in = pcm_data_size / pcm_sample_bytes;
udata->num_out = len / pcm_sample_bytes;
new_buffer = pcm_play_dma_complete_callback(PCM_DMAST_OK,
(const void **)&pcm_data, &pcm_data_size);
write_to_soundcard(udata);
udata->num_in *= pcm_sample_bytes;
udata->num_out *= pcm_sample_bytes;
if (new_buffer)
{
new_buffer = false;
pcm_play_dma_started_callback();
if ((size_t)len > udata->num_out)
{
int delay = pcm_data_size*250 / pcm_sampr - 1;
if (delay > 0)
{
SDL_UnlockMutex(audio_lock);
SDL_Delay(delay);
SDL_LockMutex(audio_lock);
if (!pcm_is_playing())
break;
}
}
}
pcm_data += udata->num_in;
pcm_data_size -= udata->num_in;
udata->stream += udata->num_out;
len -= udata->num_out;
} else {
if (!new_buffer) {
DEBUGF("sdl_audio_callback: No Data.\n");
break;
}
start:
udata->num_in = pcm_data_size / pcm_sample_bytes;
udata->num_out = len / pcm_sample_bytes;
write_to_soundcard(udata);
udata->num_in *= pcm_sample_bytes;
udata->num_out *= pcm_sample_bytes;
if (new_buffer)
{
new_buffer = false;
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
if ((size_t)len > udata->num_out)
{
int delay = pcm_data_size*250 / pcm_sampr - 1;
if (delay > 0)
{
SDL_UnlockMutex(audio_lock);
SDL_Delay(delay);
SDL_LockMutex(audio_lock);
if (!pcm_is_playing())
break;
}
}
}
pcm_data += udata->num_in;
pcm_data_size -= udata->num_in;
udata->stream += udata->num_out;
len -= udata->num_out;
}
SDL_UnlockMutex(audio_lock);

12
firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
View file

@ -63,7 +63,7 @@ void pcm_dma_apply_settings(void)
audiohw_set_frequency(pcm_sampr);
}
static void* playback_address;
static const void* playback_address;
static inline void set_dma(const void *addr, size_t size)
{
int burst_size;
@ -96,21 +96,19 @@ static inline void set_dma(const void *addr, size_t size)
REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT;
REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | burst_size | DMAC_DCMD_DWDH_16 | DMAC_DCMD_TIE);
playback_address = (void*)addr;
playback_address = addr;
}
static inline void play_dma_callback(void)
{
void *start;
const void *start;
size_t size;
pcm_play_get_more_callback(&start, &size);
if (size != 0)
if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
{
set_dma(start, size);
REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN;
pcm_play_dma_started_callback();
pcm_play_dma_status_callback(PCM_DMAST_STARTED);
}
}