imx233: fix emi frequency scaling

On the ZEN X-Fi2, the fractiona dividers are gated by the
bootloader and must be ungated before switching emi to pll.

Change-Id: I5df57ed5581054883da4cbb3b4f3ce3539391ab5
This commit is contained in:
Amaury Pouly 2013-07-02 00:31:57 +02:00
parent bb87590e05
commit 2773673733
2 changed files with 5 additions and 3 deletions

View file

@ -121,7 +121,9 @@ static void set_frequency(unsigned long freq)
* clk_emi@64 MHz */
break;
}
BF_WR(CLKCTRL_FRAC, CLKGATEEMI, 0);
BF_WR(CLKCTRL_FRAC, EMIFRAC, fracdiv);
BF_WR(CLKCTRL_EMI, CLKGATE, 0);
BF_WR(CLKCTRL_EMI, DIV_EMI, div);
}

View file

@ -200,11 +200,11 @@ struct cpufreq_profile_t
static struct cpufreq_profile_t cpu_profiles[] =
{
/* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */
/* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.550 V */
{IMX233_CPUFREQ_454_MHz, 1550, 1450, 3, 1, 19, IMX233_EMIFREQ_130_MHz, 0},
/* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz */
/* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.275 V */
{IMX233_CPUFREQ_261_MHz, 1275, 1175, 2, 1, 33, IMX233_EMIFREQ_130_MHz, 0},
/* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz */
/* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz, VDDD@1.050 V */
{IMX233_CPUFREQ_64_MHz, 1050, 975, 1, 5, 27, IMX233_EMIFREQ_64_MHz, 0},
/* dummy */
{0, 0, 0, 0, 0, 0, 0, 0}