len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-09 13:15:18 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

Make basic cache functions into calls, and get rid of CACHE_FUNCTION_WRAPPERS and CACHE_FUNCTIONS_AS_CALL macros. Rename flush/invalidate_icache to cpucache_flush/invalidate. They're inlined only if an implementation isn't provided by defining HAVE_CPUCACHE_FLUSH/INVALIDATE.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19971 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2009-02-11 12:55:51 +00:00
parent 4cd7597172
commit 21f0c9a282
28 changed files with 136 additions and 173 deletions
Download patch file Download diff file Expand all files Collapse all files

32
firmware/target/arm/imx31/gigabeat-s/system-target.h
View file

@ -57,34 +57,12 @@ void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
#define KDEV_INIT
#define HAVE_INVALIDATE_ICACHE
static inline void invalidate_icache(void)
{
asm volatile(
/* Clean and invalidate entire data cache */
"mcr p15, 0, %0, c7, c14, 0 \n"
/* Invalidate entire instruction cache
* Also flushes the branch target cache */
"mcr p15, 0, %0, c7, c5, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, %0, c7, c10, 4 \n"
/* Flush prefetch buffer */
"mcr p15, 0, %0, c7, c5, 4 \n"
: : "r"(0)
);
}
#define HAVE_CPUCACHE_INVALIDATE
#define HAVE_CPUCACHE_FLUSH
#define HAVE_FLUSH_ICACHE
static inline void flush_icache(void)
{
asm volatile (
/* Clean entire data cache */
"mcr p15, 0, %0, c7, c10, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, %0, c7, c10, 4 \n"
: : "r"(0)
);
}
/* Different internal names */
#define cpucache_flush clean_dcache
#define cpucache_invalidate invalidate_idcache
struct ARM_REGS {
int r0;

30
firmware/target/arm/mmu-arm.c
View file

@ -265,6 +265,8 @@ void __attribute__((naked)) clean_dcache(void)
/* Clean entire data cache */
"mov r0, #0 \n"
"mcr p15, 0, r0, c7, c10, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, r0, c7, c10, 4 \n"
"bx lr \n"
);
}
@ -290,3 +292,31 @@ void clean_dcache(void)
}
#endif
#if CONFIG_CPU == IMX31L
void invalidate_idcache(void)
{
asm volatile(
/* Clean and invalidate entire data cache */
"mcr p15, 0, %0, c7, c14, 0 \n"
/* Invalidate entire instruction cache
* Also flushes the branch target cache */
"mcr p15, 0, %0, c7, c5, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, %0, c7, c10, 4 \n"
/* Flush prefetch buffer */
"mcr p15, 0, %0, c7, c5, 4 \n"
: : "r"(0)
);
}
#else
void invalidate_idcache(void)
{
clean_dcache();
asm volatile(
"mov r0, #0 \n"
"mcr p15, 0, r0, c7, c5, 0 \n"
: : : "r0"
);
}
#endif

14
firmware/target/arm/s3c2440/gigabeat-fx/system-target.h
View file

@ -41,15 +41,9 @@ void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
/* Clear register bits */
void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
#define HAVE_INVALIDATE_ICACHE
static inline void invalidate_icache(void)
{
clean_dcache();
asm volatile(
"mov r0, #0 \n"
"mcr p15, 0, r0, c7, c5, 0 \n"
: : : "r0"
);
}
#define HAVE_CPUCACHE_FLUSH
#define HAVE_CPUCACHE_INVALIDATE
#define cpucache_flush clean_dcache
#define cpucache_invalidate invalidate_idcache
#endif /* SYSTEM_TARGET_H */

6
firmware/target/arm/system-pp5002.c
View file

@ -62,8 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
some other CPU frequency scaling. */
#ifndef BOOTLOADER
void flush_icache(void) ICODE_ATTR;
void flush_icache(void)
void ICODE_ATTR cpucache_flush(void)
{
intptr_t b, e;
@ -73,8 +72,7 @@ void flush_icache(void)
}
}
void invalidate_icache(void) ICODE_ATTR;
void invalidate_icache(void)
void ICODE_ATTR cpucache_invalidate(void)
{
intptr_t b, e;

6
firmware/target/arm/system-pp502x.c
View file

@ -163,8 +163,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
to extend the funtions to do alternate cache configurations. */
#ifndef BOOTLOADER
void flush_icache(void) ICODE_ATTR;
void flush_icache(void)
void ICODE_ATTR cpucache_flush(void)
{
if (CACHE_CTL & CACHE_CTL_ENABLE)
{
@ -173,8 +172,7 @@ void flush_icache(void)
}
}
void invalidate_icache(void) ICODE_ATTR;
void invalidate_icache(void)
void ICODE_ATTR cpucache_invalidate(void)
{
if (CACHE_CTL & CACHE_CTL_ENABLE)
{

9
firmware/target/arm/system-target.h
View file

@ -168,13 +168,8 @@ static inline void wake_core(int core)
/** cache functions **/
#ifndef BOOTLOADER
#define CACHE_FUNCTIONS_AS_CALL
#define HAVE_INVALIDATE_ICACHE
void invalidate_icache(void);
#define HAVE_FLUSH_ICACHE
void flush_icache(void);
#define HAVE_CPUCACHE_INVALIDATE
#define HAVE_CPUCACHE_FLUSH
#endif
#endif /* CPU_PP */