x1000: Centralize common definitions, memory layout

Change-Id: I8daad058ae55d4b750b1ae407153e4917de5d095

apps/plugins/plugin.lds

@@ -77,9 +77,9 @@ OUTPUT_FORMAT(elf32-littlemips)
 #include "cpu.h"
 #define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - FRAME_SIZE - TTB_SIZE)
 #elif CONFIG_CPU==X1000
-#include "config.h"
+#include "cpu.h"
 #undef STUBOFFSET
-#define STUBOFFSET 0x4000
+#define DRAMSIZE (X1000_DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
 #endif
 
  /* default to full RAM (minus codecs&plugins) unless specified otherwise */
@@ -179,7 +179,7 @@ OUTPUT_FORMAT(elf32-littlemips)
 /* The bit of IRAM that is available is used in the core */
 
 #elif CONFIG_CPU == X1000
-#define DRAMORIG (0x80000000 + STUBOFFSET)
+#define DRAMORIG X1000_DRAM_BASE
 #define IRAM DRAM
 #define IRAMSIZE 0
 

firmware/export/cpu.h

@@ -77,3 +77,6 @@
 #if CONFIG_CPU == RK27XX
 #include "rk27xx.h"
 #endif
+#if CONFIG_CPU == X1000
+#include "x1000.h"
+#endif

firmware/export/x1000.h

@@ -0,0 +1,72 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2021 Aidan MacDonald
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __X1000_H__
+#define __X1000_H__
+
+#include "config.h"
+
+/* Frequency of external oscillator EXCLK */
+//#define X1000_EXCLK_FREQ 24000000
+
+/* Maximum CPU frequency that can be achieved on the target */
+//#define CPU_FREQ         1008000000
+
+/* Only 24 MHz and 26 MHz external oscillators are supported by the X1000 */
+#if X1000_EXCLK_FREQ == 24000000
+# define X1000_EXCLK_24MHZ
+#elif X1000_EXCLK_FREQ == 26000000
+# define X1000_EXCLK_26MHZ
+#else
+# error "Unsupported EXCLK freq"
+#endif
+
+/* On-chip TCSM (tightly coupled shared memory), aka IRAM */
+#define X1000_TCSM_BASE         0xf4000000
+#define X1000_TCSM_SIZE         (16 * 1024)
+
+/* External SDRAM */
+#define X1000_SDRAM_BASE        0x80000000
+#define X1000_SDRAM_SIZE        (MEMORYSIZE * 1024 * 1024)
+
+/* Memory definitions for Rockbox */
+#define X1000_IRAM_BASE         X1000_SDRAM_BASE
+#define X1000_IRAM_SIZE         (16 * 1024)
+#define X1000_IRAM_END          (X1000_IRAM_BASE + X1000_IRAM_SIZE)
+#define X1000_DRAM_BASE         X1000_IRAM_END
+#define X1000_DRAM_SIZE         (X1000_SDRAM_SIZE - X1000_IRAM_SIZE)
+#define X1000_DRAM_END          (X1000_DRAM_BASE + X1000_DRAM_SIZE)
+#define X1000_STACKSIZE         0x1e00
+#define X1000_IRQSTACKSIZE      0x300
+
+/* Convert kseg0 address to physical address or uncached address */
+#define PHYSADDR(x)     ((unsigned long)(x) & 0x1fffffff)
+#define UNCACHEDADDR(x) (PHYSADDR(x) | 0xa0000000)
+
+/* Defines for usb-designware driver */
+#define OTGBASE             0xb3500000
+#define USB_NUM_ENDPOINTS   9
+
+/* CPU cache parameters */
+#define CACHEALIGN_BITS     5
+#define CACHE_SIZE          (16 * 1024)
+
+#endif /* __X1000_H__ */

firmware/target/mips/ingenic_x1000/app.lds

@@ -1,30 +1,21 @@
 #include "config.h"
+#include "cpu.h"
 
 OUTPUT_FORMAT("elf32-littlemips")
 OUTPUT_ARCH(MIPS)
 ENTRY(_start)
 STARTUP(target/mips/ingenic_x1000/crt0.o)
 
-/* Stub area is used for loading new firmware via RoLo */
-#define STUBSIZE    0x4000
-#define SDRAM_ORIG  0x80000000
-
-/* IRAM contains stub, DRAM contains main app */
-#define IRAMORIG SDRAM_ORIG
-#define IRAMSIZE STUBSIZE
-#define DRAMORIG (SDRAM_ORIG + STUBSIZE)
-#define DRAMSIZE (MEMORYSIZE * 0x100000 - STUBSIZE)
-
 /* End of the audio buffer, where the codec buffer starts */
-#define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
+#define ENDAUDIOADDR (X1000_DRAM_END - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
 
 /* Where the codec buffer ends, and the plugin buffer starts */
 #define ENDCODECADDR  (ENDAUDIOADDR + CODEC_SIZE)
 
 MEMORY
 {
-    IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+    IRAM : ORIGIN = X1000_IRAM_BASE, LENGTH = X1000_IRAM_SIZE
-    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+    DRAM : ORIGIN = X1000_DRAM_BASE, LENGTH = X1000_DRAM_SIZE
 }
 
 SECTIONS
@@ -50,7 +41,7 @@ SECTIONS
         *(.sdata*);
     } > DRAM
 
-    .iram IRAMORIG: AT (_bssbegin)
+    .iram X1000_IRAM_BASE: AT (_bssbegin)
     {
         _iramstart = .;
         . = 0x000; /* TLB refill */
@@ -75,10 +66,10 @@ SECTIONS
     {
          *(.stack);
          stackbegin = .;
-         . += 0x1E00;
+         . += X1000_STACKSIZE;
          stackend = .;
          _irqstackbegin = .;
-         . += 0x300;
+         . += X1000_IRQSTACKSIZE;
          _irqstackend = .;
     } > IRAM
 
@@ -93,23 +84,17 @@ SECTIONS
         _end = .;
     } > DRAM
 
-#ifdef BOOTLOADER
-    . = ALIGN(4);
-    loadbuffer = .;
-    . += 0x100000 * 4; /* Allow 4 MiB for the rockbox binary */
-    loadbufferend = .;
-#else
-
     .audiobuf :
     {
-        . = ALIGN(4); /* XXX might need more alignment here */
+        . = ALIGN(4);
         audiobuffer = .;
+        loadbuffer = .;
     } > DRAM
 
+    loadbufferend = ENDAUDIOADDR;
     audiobufend = ENDAUDIOADDR;
     codecbuf = ENDAUDIOADDR;
     pluginbuf = ENDCODECADDR;
-#endif
 
     /DISCARD/ :
     {

firmware/target/mips/ingenic_x1000/fiiom3k/spl-fiiom3k.c

@@ -56,8 +56,8 @@ const struct spl_boot_option spl_boot_options[] = {
          */
         .nand_addr = 0x6800,
         .nand_size = 0x19800,
-        .load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */
+        .load_addr = X1000_DRAM_BASE - 8, /* first 8 bytes are bootloader ID */
-        .exec_addr = 0x80004000,
+        .exec_addr = X1000_DRAM_BASE,
         .cmdline = NULL,
     },
     {

firmware/target/mips/ingenic_x1000/spl.lds

@@ -1,23 +1,22 @@
 #include "config.h"
+#include "cpu.h"
 
 OUTPUT_FORMAT("elf32-littlemips")
 OUTPUT_ARCH(MIPS)
 ENTRY(_start)
 STARTUP(target/mips/ingenic_x1000/crt0.o)
 
-#define DRAMORIG 0x80000000
-#define DRAMSIZE (MEMORYSIZE * 0x100000)
-#define USED_DRAM 16K
-
-/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
- *
- * The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
- * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
- * The maskrom will jump to that address (via jalr) after loading the SPL.
- */
 MEMORY {
-    TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800
+    /* First 4k of TCSM is used by mask ROM for stack + variables,
-    DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM
+     * and the next 2k are occupied by SPL header */
+    TCSM : ORIGIN = X1000_TCSM_BASE + 0x1800,
+           LENGTH = X1000_TCSM_SIZE - 0x1800
+
+    /* Small area of DRAM is required for NAND bounce buffers,
+     * though not strictly necessary as ECC isn't really practical
+     * this early in the boot */
+    DRAM : ORIGIN = X1000_DRAM_END - 16K,
+           LENGTH = 16K
 }
 
 SECTIONS

firmware/target/mips/ingenic_x1000/system-target.h

@@ -22,35 +22,23 @@
 #ifndef __SYSTEM_TARGET_H__
 #define __SYSTEM_TARGET_H__
 
-/* For the sake of system.h CACHEALIGN macros.
- * We need this to align DMA buffers, etc.
- */
-#define CACHEALIGN_BITS 5
-#define CACHE_SIZE      (16*1024)
-
 #ifdef DEBUG
 /* Define this to get CPU idle stats, visible in the debug menu. */
 # define X1000_CPUIDLE_STATS
 #endif
 
-#define OTGBASE 0xb3500000
+#include "cpu.h"
-#define USB_NUM_ENDPOINTS 9
-
 #include "mmu-mips.h"
 #include "mipsregs.h"
 #include "mipsr2-endian.h"
 #include <stdint.h>
 
-/* Get physical address for DMA */
-#define PHYSADDR(addr)  (((unsigned long)(addr)) & 0x1fffffff)
-
-#define HIGHEST_IRQ_LEVEL 0
-
 /* Rockbox API */
 #define enable_irq()        set_c0_status(ST0_IE)
 #define disable_irq()       clear_c0_status(ST0_IE)
 #define disable_irq_save()  set_irq_level(0)
 #define restore_irq(arg)    write_c0_status(arg)
+#define HIGHEST_IRQ_LEVEL   0
 
 static inline int set_irq_level(int lev)
 {