mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-14 15:42:28 -05:00
1) Set svn:keywords where they should've been set
2) Onda VX747 specific changes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18080 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
ccf4ce98fd
commit
1f692e5f55
10 changed files with 408 additions and 222 deletions
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@ -25,6 +25,10 @@ SECTIONS
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.text : {
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loadaddress = .;
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_loadaddress = .;
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_resetvectorsstart = .;
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KEEP(*(.resetvectors));
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*(.resetvectors);
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_resetvectorsend = .;
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*(.init.text);
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*(.text*);
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*(.glue_7);
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@ -92,16 +96,13 @@ SECTIONS
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. = ALIGN(4);
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.vectors IRAMORIG :
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.vectors :
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{
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_vectorsstart = .;
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KEEP(*(.resetvectors));
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*(.resetvectors);
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KEEP(*(.vectors));
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*(.vectors);
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_vectorsend = .;
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} AT > DRAM
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_vectorscopy = LOADADDR(.vectors);
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} > DRAM
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. = ALIGN(4);
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}
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@ -1,3 +1,24 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* init.S
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*
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@ -21,14 +42,10 @@
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.set mips3
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.extern main
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.extern system_main
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.global _start
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#ifdef BOOTLOADER
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.section .init.text,"ax",%progbits
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#else
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.section .resetvectors,"ax",%progbits
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#endif
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.set noreorder
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.set noat
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@ -80,6 +97,15 @@ _init_cache_loop:
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ori t0, 2
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mtc0 t0, C0_CONFIG
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nop
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//----------------------------------------------------
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// clear BSS section
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//----------------------------------------------------
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la t0, _edata
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la t1, _end
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1: sw zero, 0(t0)
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bne t0, t1, 1b
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addiu t0, 4
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//----------------------------------------------------
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// setup stack, jump to C code
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@ -93,14 +119,12 @@ _init_stack_loop:
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bne t0, sp, _init_stack_loop
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addiu t0, t0, 4
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la t0, main
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la t0, system_main
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jr t0
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nop
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#ifndef BOOTLOADER
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.section .vectors,"ax",%progbits
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#endif
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.extern exception_handler
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.global except_common_entry
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.type except_common_entry,@function
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@ -119,57 +143,57 @@ except_common_entry:
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exception_handler:
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addiu sp, -0x80 # Add Immediate Unsigned
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sw ra, 0(sp) # Store Word
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sw fp, 4(sp) # Store Word
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sw gp, 8(sp) # Store Word
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sw t9, 0xC(sp) # Store Word
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sw t8, 0x10(sp) # Store Word
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sw s7, 0x14(sp) # Store Word
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sw s6, 0x18(sp) # Store Word
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sw s5, 0x1C(sp) # Store Word
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sw s4, 0x20(sp) # Store Word
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sw s3, 0x24(sp) # Store Word
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sw s2, 0x28(sp) # Store Word
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sw s1, 0x2C(sp) # Store Word
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sw s0, 0x30(sp) # Store Word
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sw t7, 0x34(sp) # Store Word
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sw t6, 0x38(sp) # Store Word
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sw t5, 0x3C(sp) # Store Word
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sw t4, 0x40(sp) # Store Word
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sw t3, 0x44(sp) # Store Word
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sw t2, 0x48(sp) # Store Word
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sw t1, 0x4C(sp) # Store Word
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sw t0, 0x50(sp) # Store Word
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sw a3, 0x54(sp) # Store Word
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sw a2, 0x58(sp) # Store Word
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sw a1, 0x5C(sp) # Store Word
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sw a0, 0x60(sp) # Store Word
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sw v1, 0x64(sp) # Store Word
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sw v0, 0x68(sp) # Store Word
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sw $1, 0x6C(sp) # Store Word
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mflo t0 # Move F LO
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addiu sp, -0x80
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sw ra, 0(sp)
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sw fp, 4(sp)
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sw gp, 8(sp)
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sw t9, 0xC(sp)
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sw t8, 0x10(sp)
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sw s7, 0x14(sp)
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sw s6, 0x18(sp)
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sw s5, 0x1C(sp)
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sw s4, 0x20(sp)
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sw s3, 0x24(sp)
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sw s2, 0x28(sp)
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sw s1, 0x2C(sp)
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sw s0, 0x30(sp)
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sw t7, 0x34(sp)
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sw t6, 0x38(sp)
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sw t5, 0x3C(sp)
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sw t4, 0x40(sp)
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sw t3, 0x44(sp)
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sw t2, 0x48(sp)
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sw t1, 0x4C(sp)
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sw t0, 0x50(sp)
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sw a3, 0x54(sp)
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sw a2, 0x58(sp)
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sw a1, 0x5C(sp)
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sw a0, 0x60(sp)
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sw v1, 0x64(sp)
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sw v0, 0x68(sp)
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sw $1, 0x6C(sp)
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mflo t0 # Move From LO
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nop
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sw t0, 0x70(sp) # Store Word
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mfhi t0 # Move F HI
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sw t0, 0x70(sp)
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mfhi t0 # Move From HI
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nop
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sw t0, 0x74(sp) # Store Word
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sw t0, 0x74(sp)
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mfc0 t0, C0_STATUS # Status register
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sw t0, 0x78(sp) # Store Word
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sw t0, 0x78(sp)
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mfc0 t0, C0_EPC # Exception Program Counter
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sw t0, 0x7C(sp) # Store Word
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li k1, 0x7C # Load Immediate
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sw t0, 0x7C(sp)
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li k1, 0x7C
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mfc0 k0, C0_CAUSE # C0_CAUSE of last exception
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and k0, k1 # AND
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beq zero, k0, _int # Branch on Equal
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and k0, k1
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beq zero, k0, _int
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nop
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la k0, _exception
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jr k0
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@ -178,57 +202,57 @@ exception_handler:
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.global _int
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.type _int,@function
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_int:
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jal intr_handler # Jump And Link
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jal intr_handler
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nop
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lw ra, 0(sp) # Load Word
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lw fp, 4(sp) # Load Word
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sw gp, 8(sp) # Store Word
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lw t9, 0xC(sp) # Load Word
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lw t8, 0x10(sp) # Load Word
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lw s7, 0x14(sp) # Load Word
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lw s6, 0x18(sp) # Load Word
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lw s5, 0x1C(sp) # Load Word
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lw s4, 0x20(sp) # Load Word
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lw s3, 0x24(sp) # Load Word
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lw s2, 0x28(sp) # Load Word
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lw s1, 0x2C(sp) # Load Word
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lw s0, 0x30(sp) # Load Word
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lw t7, 0x34(sp) # Load Word
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lw t6, 0x38(sp) # Load Word
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lw t5, 0x3C(sp) # Load Word
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lw t4, 0x40(sp) # Load Word
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lw t3, 0x44(sp) # Load Word
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lw t2, 0x48(sp) # Load Word
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lw t1, 0x4C(sp) # Load Word
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lw t0, 0x50(sp) # Load Word
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lw a3, 0x54(sp) # Load Word
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lw a2, 0x58(sp) # Load Word
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lw a1, 0x5C(sp) # Load Word
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lw a0, 0x60(sp) # Load Word
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lw v1, 0x64(sp) # Load Word
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lw v0, 0x68(sp) # Load Word
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lw v1, 0x6C(sp) # Load Word
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lw k0, 0x70(sp) # Load Word
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lw ra, 0(sp)
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lw fp, 4(sp)
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sw gp, 8(sp)
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lw t9, 0xC(sp)
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lw t8, 0x10(sp)
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lw s7, 0x14(sp)
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lw s6, 0x18(sp)
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lw s5, 0x1C(sp)
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lw s4, 0x20(sp)
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lw s3, 0x24(sp)
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lw s2, 0x28(sp)
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lw s1, 0x2C(sp)
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lw s0, 0x30(sp)
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lw t7, 0x34(sp)
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lw t6, 0x38(sp)
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lw t5, 0x3C(sp)
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lw t4, 0x40(sp)
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lw t3, 0x44(sp)
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lw t2, 0x48(sp)
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lw t1, 0x4C(sp)
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lw t0, 0x50(sp)
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lw a3, 0x54(sp)
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lw a2, 0x58(sp)
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lw a1, 0x5C(sp)
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lw a0, 0x60(sp)
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lw v1, 0x64(sp)
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lw v0, 0x68(sp)
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lw v1, 0x6C(sp)
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lw k0, 0x70(sp)
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mtlo k0 # Move To LO
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nop
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lw k0, 0x74(sp) # Load Word
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lw k0, 0x74(sp)
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mthi k0 # Move To HI
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nop
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lw k0, 0x78(sp) # Load Word
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lw k0, 0x78(sp)
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nop
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mtc0 k0, C0_STATUS # Status register
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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lw k0, 0x7C(sp) # Load Word
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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lw k0, 0x7C(sp)
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nop
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mtc0 k0, C0_EPC # Exception Program Counter
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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sll zero, 1 # Shift Left Logical
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addiu sp, 0x80 # Add Immediate Unsigned
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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addiu sp, 0x80
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eret # Exception Return
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nop
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@ -239,8 +263,8 @@ _exception:
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move a0, sp
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mfc0 a1, C0_CAUSE # C0_CAUSE of last exception
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mfc0 a2, C0_EPC # Exception Program Counter
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la k0, except_handler # Load Address
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jr k0 # Jump Register
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la k0, except_handler
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jr k0
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nop
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.set reorder
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@ -71,7 +71,7 @@ void lcd_update_rect(int x, int y, int width, int height)
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| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
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REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
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jz_flush_dcache();
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__dcache_writeback_all();
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REG_DMAC_DMACR = DMAC_DMACR_DMAE;
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@ -37,7 +37,8 @@
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SADC_CFG_SNUM_5 | \
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(1 << SADC_CFG_CLKDIV_BIT) | \
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SADC_CFG_PBAT_HIGH | \
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SADC_CFG_CMD_INT_PEN )
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SADC_CFG_CMD_INT_PEN \
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)
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bool button_hold(void)
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{
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@ -102,7 +103,7 @@ int button_read_device(int *data)
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REG_SADC_CTRL |= (SADC_CTRL_PENDM);
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unsigned int dat;
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unsigned short xData,yData;
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short tsz1Data,tsz2Data;
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short tszData;
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dat = REG_SADC_TSDAT;
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@ -110,12 +111,11 @@ int button_read_device(int *data)
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yData = (dat >> 16) & 0xfff;
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dat = REG_SADC_TSDAT;
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tsz1Data = (dat >> 0) & 0xfff;
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tsz2Data = (dat >> 16) & 0xfff;
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tszData = (dat >> 0) & 0xfff;
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tszData = tszData - ((dat >> 16) & 0xfff);
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*data = touch_to_pixels(xData, yData);
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tsz1Data = tsz2Data - tsz1Data;
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}
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REG_SADC_STATE = 0;
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//__intc_unmask_irq(IRQ_SADC);
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@ -21,12 +21,16 @@
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#include "config.h"
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#include "jz4740.h"
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#include "mips.h"
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#include "mipsregs.h"
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#include "panic.h"
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#include "system-target.h"
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#include <string.h>
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#include "kernel.h"
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void intr_handler(void)
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{
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//printf("Interrupt!");
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printf("Interrupt!");
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return;
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}
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@ -35,35 +39,243 @@ void except_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
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panicf("Exception occurred: [0x%x] at 0x%x (stack at 0x%x)", cause, epc, (unsigned int)stack_ptr);
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}
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void system_reboot(void)
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static const int FR2n[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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static unsigned int iclk;
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static void detect_clock(void)
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{
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while(1);
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unsigned int cfcr, pllout;
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cfcr = REG_CPM_CPCCR;
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pllout = (__cpm_get_pllm() + 2)* JZ_EXTAL / (__cpm_get_plln() + 2);
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iclk = pllout / FR2n[__cpm_get_cdiv()];
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/*printf("EXTAL_CLK = %dM PLL = %d iclk = %d\r\n",EXTAL_CLK / 1000 /1000,pllout,iclk);*/
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}
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void udelay(unsigned int usec)
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{
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unsigned int i = usec * (iclk / 2000000);
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__asm__ __volatile__ (
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".set noreorder \n"
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"1: \n"
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"bne %0, $0, 1b \n"
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"addi %0, %0, -1 \n"
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".set reorder \n"
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: "=r" (i)
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: "0" (i)
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);
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}
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void mdelay(unsigned int msec)
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{
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unsigned int i;
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for(i=0; i<msec; i++)
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udelay(1000);
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}
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/* Core-level interrupt masking */
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void cli(void)
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{
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register unsigned int t;
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t = read_c0_status();
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t &= ~1;
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write_c0_status(t);
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register unsigned int t;
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t = read_c0_status();
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t &= ~1;
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write_c0_status(t);
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}
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unsigned int mips_get_sr(void)
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{
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unsigned int t = read_c0_status();
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return t;
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return read_c0_status();
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}
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void sti(void)
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{
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register unsigned int t;
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t = read_c0_status();
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t |= 1;
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t &= ~2;
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write_c0_status(t);
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register unsigned int t;
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t = read_c0_status();
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t |= 1;
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t &= ~2;
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write_c0_status(t);
|
||||
}
|
||||
|
||||
#define Index_Invalidate_I 0x00
|
||||
#define Index_Writeback_Inv_D 0x01
|
||||
#define Index_Load_Tag_I 0x04
|
||||
#define Index_Load_Tag_D 0x05
|
||||
#define Index_Store_Tag_I 0x08
|
||||
#define Index_Store_Tag_D 0x09
|
||||
#define Hit_Invalidate_I 0x10
|
||||
#define Hit_Invalidate_D 0x11
|
||||
#define Hit_Writeback_Inv_D 0x15
|
||||
#define Hit_Writeback_I 0x18
|
||||
#define Hit_Writeback_D 0x19
|
||||
|
||||
#define CACHE_SIZE 16*1024
|
||||
#define CACHE_LINE_SIZE 32
|
||||
#define KSEG0 0x80000000
|
||||
|
||||
#define SYNC_WB() __asm__ __volatile__ ("sync")
|
||||
|
||||
#define cache_op(op,addr) \
|
||||
__asm__ __volatile__( \
|
||||
" .set noreorder \n" \
|
||||
" .set mips32\n\t \n" \
|
||||
" cache %0, %1 \n" \
|
||||
" .set mips0 \n" \
|
||||
" .set reorder \n" \
|
||||
: \
|
||||
: "i" (op), "m" (*(unsigned char *)(addr)))
|
||||
|
||||
void __flush_dcache_line(unsigned long addr)
|
||||
{
|
||||
cache_op(Hit_Writeback_Inv_D, addr);
|
||||
SYNC_WB();
|
||||
}
|
||||
|
||||
void __icache_invalidate_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
do
|
||||
{
|
||||
unsigned long __k0_addr;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"la %0, 1f \n"
|
||||
"or %0, %0, %1 \n"
|
||||
"jr %0 \n"
|
||||
"nop \n"
|
||||
"1: nop \n"
|
||||
: "=&r"(__k0_addr)
|
||||
: "r" (0x20000000)
|
||||
);
|
||||
} while(0);
|
||||
|
||||
asm volatile (".set noreorder \n"
|
||||
".set mips32 \n"
|
||||
"mtc0 $0,$28 \n"
|
||||
"mtc0 $0,$29 \n"
|
||||
".set mips0 \n"
|
||||
".set reorder \n"
|
||||
);
|
||||
for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Store_Tag_I, i);
|
||||
|
||||
do
|
||||
{
|
||||
unsigned long __k0_addr;
|
||||
__asm__ __volatile__(
|
||||
"nop;nop;nop;nop;nop;nop;nop \n"
|
||||
"la %0, 1f \n"
|
||||
"jr %0 \n"
|
||||
"nop \n"
|
||||
"1: nop \n"
|
||||
: "=&r" (__k0_addr)
|
||||
);
|
||||
} while(0);
|
||||
|
||||
do
|
||||
{
|
||||
unsigned long tmp;
|
||||
__asm__ __volatile__(
|
||||
".set mips32 \n"
|
||||
"mfc0 %0, $16, 7 \n"
|
||||
"nop \n"
|
||||
"ori %0, 2 \n"
|
||||
"mtc0 %0, $16, 7 \n"
|
||||
"nop \n"
|
||||
".set mips0 \n"
|
||||
: "=&r" (tmp));
|
||||
} while(0);
|
||||
}
|
||||
|
||||
void __dcache_invalidate_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
asm volatile (".set noreorder \n"
|
||||
".set mips32 \n"
|
||||
"mtc0 $0,$28 \n"
|
||||
"mtc0 $0,$29 \n"
|
||||
".set mips0 \n"
|
||||
".set reorder \n"
|
||||
);
|
||||
for (i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Store_Tag_D, i);
|
||||
}
|
||||
|
||||
void __dcache_writeback_all(void)
|
||||
{
|
||||
unsigned int i;
|
||||
for(i=KSEG0; i<KSEG0+CACHE_SIZE; i+=CACHE_LINE_SIZE)
|
||||
cache_op(Index_Writeback_Inv_D, i);
|
||||
|
||||
SYNC_WB();
|
||||
}
|
||||
|
||||
extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
|
||||
|
||||
#define USE_RTC_CLOCK 0
|
||||
void tick_start(unsigned int interval_in_ms)
|
||||
{
|
||||
(void)interval_in_ms;
|
||||
unsigned int tps = interval_in_ms;
|
||||
unsigned int latch;
|
||||
__cpm_start_tcu();
|
||||
|
||||
__tcu_disable_pwm_output(0);
|
||||
__tcu_mask_half_match_irq(0);
|
||||
__tcu_unmask_full_match_irq(0);
|
||||
|
||||
#if USE_RTC_CLOCK
|
||||
__tcu_select_rtcclk(0);
|
||||
__tcu_select_clk_div1(0);
|
||||
latch = (__cpm_get_rtcclk() + (tps>>1)) / tps;
|
||||
#else
|
||||
__tcu_select_extalclk(0);
|
||||
__tcu_select_clk_div4(0);
|
||||
|
||||
latch = (JZ_EXTAL / 4 + (tps>>1)) / tps;
|
||||
#endif
|
||||
REG_TCU_TDFR(0) = latch;
|
||||
REG_TCU_TDHR(0) = latch;
|
||||
|
||||
__tcu_clear_full_match_flag(0);
|
||||
__tcu_start_counter(0);
|
||||
|
||||
//printf("TCSR = 0x%04x\r\n",*(volatile u16 *)0xb000204C);
|
||||
}
|
||||
|
||||
extern int main(void);
|
||||
extern unsigned int _loadaddress;
|
||||
extern unsigned int _resetvectorsstart;
|
||||
extern unsigned int _resetvectorsend;
|
||||
extern unsigned int _vectorsstart;
|
||||
extern unsigned int _vectorsend; /* see boot.lds/app.lds */
|
||||
|
||||
void system_main(void)
|
||||
{
|
||||
cli();
|
||||
write_c0_status(0x10000400);
|
||||
|
||||
memcpy((void *)A_K0BASE, (void *)&_loadaddress, 0x20);
|
||||
memcpy((void *)(A_K0BASE + 0x180), (void *)&_vectorsstart, 0x20);
|
||||
memcpy((void *)(A_K0BASE + 0x200), (void *)&_vectorsstart, 0x20);
|
||||
|
||||
__dcache_writeback_all();
|
||||
__icache_invalidate_all();
|
||||
|
||||
sti();
|
||||
|
||||
detect_clock();
|
||||
|
||||
main();
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
{
|
||||
REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
|
||||
REG_WDT_TCNT = 0;
|
||||
REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
|
||||
REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
|
||||
REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,13 +18,14 @@
|
|||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_TARGET_H_
|
||||
#define __SYSTEM_TARGET_H_
|
||||
|
||||
#include "config.h"
|
||||
#include "jz4740.h"
|
||||
#include "mipsregs.h"
|
||||
|
||||
/* Core-level interrupt masking */
|
||||
|
||||
/* This one returns the old status */
|
||||
#define HIGHEST_IRQ_LEVEL 0
|
||||
|
||||
|
|
@ -99,7 +100,14 @@ static inline void restore_interrupt(int status)
|
|||
#define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff)
|
||||
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
|
||||
|
||||
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
|
||||
|
||||
void __dcache_writeback_all(void);
|
||||
void __dcache_invalidate_all(void);
|
||||
void __icache_invalidate_all(void);
|
||||
void __flush_dcache_line(unsigned long addr);
|
||||
void sti(void);
|
||||
void cli(void);
|
||||
|
||||
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
|
||||
#endif /* __SYSTEM_TARGET_H_ */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue