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Onda VX747:

Browse source 
clean up's, bug fixes and reworks


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19007 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2008-11-04 20:30:01 +00:00
parent 059fff29ec
commit 1e8be6f6b0
9 changed files with 149 additions and 68 deletions
Download patch file Download diff file Expand all files Collapse all files

22
firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
View file

@ -59,27 +59,27 @@ void lcd_update_rect(int x, int y, int width, int height)
{
lcd_set_target(x, y, width, height);
REG_DMAC_DCCSR(0) = 0;
REG_DMAC_DRSR(0) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
REG_DMAC_DSAR(0) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF;
REG_DMAC_DTAR(0) = 0x130500B0; /* SLCD_FIFO */
REG_DMAC_DTCR(0) = width*height;
REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = 0;
REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
REG_DMAC_DSAR(DMA_LCD_CHANNEL) = ((unsigned int)&lcd_framebuffer[y][x]) & 0x1FFFFFFF;
REG_DMAC_DTAR(DMA_LCD_CHANNEL) = 0x130500B0; /* SLCD_FIFO */
REG_DMAC_DTCR(DMA_LCD_CHANNEL) = width*height;
REG_DMAC_DCMD(0) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
REG_DMAC_DCCSR(0) = (DMAC_DCCSR_NDES | DMAC_DCCSR_EN); /* (1 << 31) | (1 << 0) */
REG_DMAC_DCMD(DMA_LCD_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 /* (1 << 23) | (0 << 16) | (0 << 14) */
| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT); /* | (2 << 12) | (3 << 8) */
REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; /* (1 << 31) */
__dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size */
while(REG_SLCD_STATE & SLCD_STATE_BUSY);
REG_SLCD_CTRL = SLCD_CTRL_DMA_EN;
REG_DMAC_DMACR = DMAC_DMACR_DMAE;
REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN;
while( !(REG_DMAC_DCCSR(0) & DMAC_DCCSR_TT) )
while( !(REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) )
yield();
REG_DMAC_DMACR = 0;
REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN;
while(REG_SLCD_STATE & SLCD_STATE_BUSY);
REG_SLCD_CTRL = 0;

23
firmware/target/mips/ingenic_jz47xx/system-jz4740.c
View file

@ -389,6 +389,7 @@ void udelay(unsigned int usec)
: "0" (i)
);
}
void mdelay(unsigned int msec)
{
unsigned int i;
@ -437,7 +438,7 @@ void sti(void)
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define __CACHE_OP(op, addr) \
#define __CACHE_OP(op, addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
@ -632,6 +633,20 @@ static void tlb_call_refill(void)
);
}
static void dma_init(void)
{
__cpm_start_dmac();
REG_DMAC_DCCSR(0) = 0;
REG_DMAC_DCCSR(1) = 0;
REG_DMAC_DCCSR(2) = 0;
REG_DMAC_DCCSR(3) = 0;
REG_DMAC_DCCSR(4) = 0;
REG_DMAC_DCCSR(5) = 0;
REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE);
}
extern int main(void);
extern void except_common_entry(void);
@ -660,12 +675,14 @@ void system_main(void)
dis_irq(i);
tlb_init();
dma_init();
detect_clock();
/* Enable interrupts at core level */
sti();
main();
main(); /* Shouldn't return */
while(1);
}
@ -686,7 +703,7 @@ void power_off(void)
/* Put system into hibernate mode */
__rtc_clear_alarm_flag();
__rtc_clear_hib_stat_all();
//__rtc_set_scratch_pattern(0x12345678);
/* __rtc_set_scratch_pattern(0x12345678); */
__rtc_enable_alarm_wakeup();
__rtc_set_hrcr_val(0xfe0);
__rtc_set_hwfcr_val((0xFFFF << 4));

6
firmware/target/mips/ingenic_jz47xx/system-target.h
View file

@ -102,5 +102,9 @@ void mdelay(unsigned int msec);
void power_off(void);
void system_reboot(void);
#endif /* __SYSTEM_TARGET_H_ */
#define DMA_LCD_CHANNEL 0
#define DMA_NAND_CHANNEL 1
#define DMA_USB_CHANNEL 2
#define DMA_AIC_TX_CHANNEL 3
#endif /* __SYSTEM_TARGET_H_ */