mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-08 12:45:26 -05:00
as3525v2-usb: major code renaming
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26971 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly
parent
f9242c06d0
commit
19b3348656
2 changed files with 473 additions and 419 deletions
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@ -36,16 +36,16 @@
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#include "usb-drv-as3525v2.h"
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#include "usb-drv-as3525v2.h"
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#include "usb_core.h"
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#include "usb_core.h"
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static int __in_ep_list[USB_NUM_IN_EP] = {USB_IN_EP_LIST};
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static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST};
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static int __out_ep_list[USB_NUM_OUT_EP] = {USB_OUT_EP_LIST};
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static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST};
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/* iterate through each in/out ep except EP0
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/* iterate through each in/out ep except EP0
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* 'counter' is the counter, 'ep' is the actual value */
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* 'counter' is the counter, 'ep' is the actual value */
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#define FOR_EACH_IN_EP(counter, ep) \
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#define FOR_EACH_IN_EP(counter, ep) \
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for(counter = 0, ep = __in_ep_list[0]; counter < USB_NUM_IN_EP; counter++, ep = __in_ep_list[counter])
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for(counter = 0, ep = __in_ep_list[0]; counter < NUM_IN_EP; counter++, ep = __in_ep_list[counter])
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#define FOR_EACH_OUT_EP(counter, ep) \
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#define FOR_EACH_OUT_EP(counter, ep) \
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for(counter = 0, ep = __out_ep_list[0]; counter < USB_NUM_OUT_EP; counter++, ep = __out_ep_list[counter])
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for(counter = 0, ep = __out_ep_list[0]; counter < NUM_OUT_EP; counter++, ep = __out_ep_list[counter])
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struct usb_endpoint
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struct usb_endpoint
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{
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{
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@ -91,29 +91,29 @@ static void as3525v2_connect(void)
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CGU_USB |= 0x20;
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CGU_USB |= 0x20;
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usb_delay();
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usb_delay();
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/* 3) clear "stop pclk" */
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/* 3) clear "stop pclk" */
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USB_PCGCCTL &= ~0x1;
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PCGCCTL &= ~0x1;
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usb_delay();
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usb_delay();
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/* 4) clear "power clamp" */
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/* 4) clear "power clamp" */
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USB_PCGCCTL &= ~0x4;
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PCGCCTL &= ~0x4;
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usb_delay();
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usb_delay();
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/* 5) clear "reset power down module" */
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/* 5) clear "reset power down module" */
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USB_PCGCCTL &= ~0x8;
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PCGCCTL &= ~0x8;
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usb_delay();
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usb_delay();
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/* 6) set "power on program done" */
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/* 6) set "power on program done" */
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USB_DCTL |= USB_DCTL_pwronprgdone;
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DCTL |= DCTL_pwronprgdone;
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usb_delay();
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usb_delay();
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/* 7) core soft reset */
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/* 7) core soft reset */
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USB_GRSTCTL |= USB_GRSTCTL_csftrst;
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GRSTCTL |= GRSTCTL_csftrst;
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usb_delay();
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usb_delay();
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/* 8) hclk soft reset */
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/* 8) hclk soft reset */
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USB_GRSTCTL |= USB_GRSTCTL_hsftrst;
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GRSTCTL |= GRSTCTL_hsftrst;
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usb_delay();
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usb_delay();
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/* 9) flush and reset everything */
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/* 9) flush and reset everything */
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USB_GRSTCTL |= 0x3f;
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GRSTCTL |= 0x3f;
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usb_delay();
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usb_delay();
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/* 10) force device mode*/
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/* 10) force device mode*/
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USB_GUSBCFG &= ~USB_GUSBCFG_force_host_mode;
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GUSBCFG &= ~GUSBCFG_force_host_mode;
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USB_GUSBCFG |= USB_GUSBCFG_force_device_mode;
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GUSBCFG |= GUSBCFG_force_device_mode;
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usb_delay();
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usb_delay();
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/* 11) Do something that is probably CCU related but undocumented*/
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/* 11) Do something that is probably CCU related but undocumented*/
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CCU_USB_THINGY &= ~0x1000;
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CCU_USB_THINGY &= ~0x1000;
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@ -121,48 +121,48 @@ static void as3525v2_connect(void)
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CCU_USB_THINGY &= ~0x300000;
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CCU_USB_THINGY &= ~0x300000;
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usb_delay();
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usb_delay();
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/* 12) reset usb core parameters (dev addr, speed, ...) */
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/* 12) reset usb core parameters (dev addr, speed, ...) */
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USB_DCFG = 0;
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DCFG = 0;
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usb_delay();
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usb_delay();
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}
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}
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static void usb_enable_device_interrupts(void)
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static void enable_device_interrupts(void)
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{
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{
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/* Clear any pending interrupt */
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/* Clear any pending interrupt */
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USB_GINTSTS = 0xffffffff;
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GINTSTS = 0xffffffff;
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/* Clear any pending otg interrupt */
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/* Clear any pending otg interrupt */
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USB_GOTGINT = 0xffffffff;
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GOTGINT = 0xffffffff;
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/* Enable interrupts */
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/* Enable interrupts */
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USB_GINTMSK = USB_GINTMSK_usbreset
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GINTMSK = GINTMSK_usbreset
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| USB_GINTMSK_enumdone
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| GINTMSK_enumdone
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| USB_GINTMSK_inepintr
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| GINTMSK_inepintr
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| USB_GINTMSK_outepintr
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| GINTMSK_outepintr
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| USB_GINTMSK_otgintr
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| GINTMSK_otgintr
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| USB_GINTMSK_disconnect;
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| GINTMSK_disconnect;
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}
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}
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static void usb_flush_tx_fifos(int nums)
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static void flush_tx_fifos(int nums)
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{
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{
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unsigned int i = 0;
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unsigned int i = 0;
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USB_GRSTCTL = (USB_GRSTCTL & (~USB_GRSTCTL_txfnum_bits))
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GRSTCTL = (GRSTCTL & (~GRSTCTL_txfnum_bits))
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| (nums << USB_GRSTCTL_txfnum_bit_pos)
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| (nums << GRSTCTL_txfnum_bit_pos)
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| USB_GRSTCTL_txfflsh_flush;
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| GRSTCTL_txfflsh_flush;
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while(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush && i < 0x300)
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while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300)
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i++;
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i++;
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if(USB_GRSTCTL & USB_GRSTCTL_txfflsh_flush)
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if(GRSTCTL & GRSTCTL_txfflsh_flush)
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panicf("usb: hang of flush tx fifos (%x)", nums);
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panicf("usb: hang of flush tx fifos (%x)", nums);
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/* wait 3 phy clocks */
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/* wait 3 phy clocks */
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udelay(1);
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udelay(1);
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}
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}
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static void usb_flush_rx_fifo(void)
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static void flush_rx_fifo(void)
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{
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{
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unsigned int i = 0;
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unsigned int i = 0;
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USB_GRSTCTL = USB_GRSTCTL_rxfflsh_flush;
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GRSTCTL = GRSTCTL_rxfflsh_flush;
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while(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush && i < 0x300)
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while(GRSTCTL & GRSTCTL_rxfflsh_flush && i < 0x300)
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i++;
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i++;
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if(USB_GRSTCTL & USB_GRSTCTL_rxfflsh_flush)
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if(GRSTCTL & GRSTCTL_rxfflsh_flush)
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panicf("usb: hang of flush rx fifo");
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panicf("usb: hang of flush rx fifo");
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/* wait 3 phy clocks */
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/* wait 3 phy clocks */
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udelay(1);
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udelay(1);
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@ -172,15 +172,15 @@ static void core_reset(void)
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{
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{
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unsigned int i = 0;
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unsigned int i = 0;
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/* Wait for AHB master IDLE state. */
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/* Wait for AHB master IDLE state. */
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while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0)
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while((GRSTCTL & GRSTCTL_ahbidle) == 0)
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udelay(10);
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udelay(10);
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/* Core Soft Reset */
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/* Core Soft Reset */
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USB_GRSTCTL |= USB_GRSTCTL_csftrst;
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GRSTCTL |= GRSTCTL_csftrst;
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/* Waits for the hardware to clear reset bit */
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/* Waits for the hardware to clear reset bit */
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while(USB_GRSTCTL & USB_GRSTCTL_csftrst && i < 0x300)
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while(GRSTCTL & GRSTCTL_csftrst && i < 0x300)
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i++;
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i++;
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if(USB_GRSTCTL & USB_GRSTCTL_csftrst)
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if(GRSTCTL & GRSTCTL_csftrst)
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panicf("oops, usb core soft reset hang :(");
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panicf("oops, usb core soft reset hang :(");
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/* Wait for 3 PHY Clocks */
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/* Wait for 3 PHY Clocks */
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@ -192,16 +192,16 @@ static void reset_endpoints(void)
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int i, ep;
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int i, ep;
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/* disable all endpoints except EP0 */
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/* disable all endpoints except EP0 */
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FOR_EACH_IN_EP(i, ep)
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FOR_EACH_IN_EP(i, ep)
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if(USB_DIEPCTL(ep) & USB_DEPCTL_epena)
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if(DIEPCTL(ep) & DEPCTL_epena)
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USB_DIEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak;
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DIEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak;
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else
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else
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USB_DIEPCTL(ep) = 0;
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DIEPCTL(ep) = 0;
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FOR_EACH_OUT_EP(i, ep)
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FOR_EACH_OUT_EP(i, ep)
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if(USB_DOEPCTL(ep) & USB_DEPCTL_epena)
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if(DOEPCTL(ep) & DEPCTL_epena)
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USB_DOEPCTL(ep) = USB_DEPCTL_epdis | USB_DEPCTL_snak;
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DOEPCTL(ep) = DEPCTL_epdis | DEPCTL_snak;
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else
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else
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USB_DOEPCTL(ep) = 0;
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DOEPCTL(ep) = 0;
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/* Setup EP0 OUT with the following parameters:
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/* Setup EP0 OUT with the following parameters:
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* packet count = 1
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* packet count = 1
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* setup packet count = 1
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* setup packet count = 1
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@ -209,88 +209,90 @@ static void reset_endpoints(void)
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* Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT
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* Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT
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*/
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*/
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USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos)
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DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
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| (1 << USB_DEPTSIZ0_pkcnt_bit_pos)
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| (1 << DEPTSIZ0_pkcnt_bit_pos)
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| 8;
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| 8;
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/* setup DMA */
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/* setup DMA */
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clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */
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clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt); /* force write back */
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USB_DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */
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DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */
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/* Enable endpoint, clear nak */
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/* Enable endpoint, clear nak */
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USB_DOEPCTL(0) = USB_DEPCTL_epena | USB_DEPCTL_cnak | USB_DEPCTL_usbactep
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DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep
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| (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos);
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| (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos);
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/* 64 bytes packet size, active endpoint */
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/* 64 bytes packet size, active endpoint */
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USB_DIEPCTL(0) = (USB_DEPCTL_MPS_8 << USB_DEPCTL_mps_bit_pos)
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DIEPCTL(0) = (DEPCTL_MPS_8 << DEPCTL_mps_bit_pos)
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| USB_DEPCTL_usbactep;
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| DEPCTL_usbactep;
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USB_DCTL = USB_DCTL_cgnpinnak | USB_DCTL_cgoutnak;
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DCTL = DCTL_cgnpinnak | DCTL_cgoutnak;
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}
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}
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static void core_dev_init(void)
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static void core_dev_init(void)
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{
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{
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unsigned int usb_num_in_ep = 0;
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unsigned int num_in_ep = 0;
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unsigned int usb_num_out_ep = 0;
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unsigned int num_out_ep = 0;
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unsigned int i;
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unsigned int i;
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/* Restart the phy clock */
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/* Restart the phy clock */
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USB_PCGCCTL = 0;
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PCGCCTL = 0;
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/* Set phy speed : high speed */
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/* Set phy speed : high speed */
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USB_DCFG = (USB_DCFG & ~USB_DCFG_devspd_bits) | USB_DCFG_devspd_hs_phy_hs;
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DCFG = (DCFG & ~DCFG_devspd_bits) | DCFG_devspd_hs_phy_hs;
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/* Check hardware capabilities */
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/* Check hardware capabilities */
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if(USB_GHWCFG2_ARCH != USB_INT_DMA_ARCH)
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if(extract(GHWCFG2, ARCH) != INT_DMA_ARCH)
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panicf("usb: wrong architecture (%ld)", USB_GHWCFG2_ARCH);
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panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, ARCH));
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if(USB_GHWCFG2_HS_PHY_TYPE != USB_PHY_TYPE_UTMI)
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if(extract(GHWCFG2, HS_PHY_TYPE) != PHY_TYPE_UTMI)
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panicf("usb: wrong HS phy type (%ld)", USB_GHWCFG2_HS_PHY_TYPE);
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panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, HS_PHY_TYPE));
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if(USB_GHWCFG2_FS_PHY_TYPE != USB_PHY_TYPE_UNSUPPORTED)
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if(extract(GHWCFG2, FS_PHY_TYPE) != PHY_TYPE_UNSUPPORTED)
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panicf("usb: wrong FS phy type (%ld)", USB_GHWCFG2_FS_PHY_TYPE);
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panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, FS_PHY_TYPE));
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if(USB_GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2)
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if(GHWCFG4_UTMI_PHY_DATA_WIDTH != 0x2)
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panicf("usb: wrong utmi data width (%ld)", USB_GHWCFG4_UTMI_PHY_DATA_WIDTH);
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panicf("usb: wrong utmi data width (%ld)", GHWCFG4_UTMI_PHY_DATA_WIDTH);
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if(USB_GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */
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if(GHWCFG4_DED_FIFO_EN != 1) /* it seems to be multiple tx fifo support */
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panicf("usb: no multiple tx fifo");
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panicf("usb: no multiple tx fifo");
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#ifdef USB_USE_CUSTOM_FIFO_LAYOUT
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#ifdef USE_CUSTOM_FIFO_LAYOUT
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if(USB_GHWCFG2_DYN_FIFO != 1)
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if(!(GHWCFG2 & GHWCFG2_DYN_FIFO))
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panicf("usb: no dynamic fifo");
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panicf("usb: no dynamic fifo");
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if(USB_GRXFSIZ != USB_DATA_FIFO_DEPTH)
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if(GRXFSIZ != DATA_FIFO_DEPTH)
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panicf("usb: wrong data fifo size");
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panicf("usb: wrong data fifo size");
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#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */
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#endif /* USE_CUSTOM_FIFO_LAYOUT */
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/* do some logging */
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/* do some logging */
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logf("hwcfg1: %08lx", USB_GHWCFG1);
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logf("hwcfg1: %08lx", GHWCFG1);
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logf("hwcfg2: %08lx", USB_GHWCFG2);
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logf("hwcfg2: %08lx", GHWCFG2);
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logf("hwcfg3: %08lx", USB_GHWCFG3);
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logf("hwcfg3: %08lx", GHWCFG3);
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logf("hwcfg4: %08lx", USB_GHWCFG4);
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logf("hwcfg4: %08lx", GHWCFG4);
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logf("%ld endpoints", USB_GHWCFG2_NUM_EP);
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logf("%ld endpoints", extract(GHWCFG2, NUM_EP));
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usb_num_in_ep = 0;
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num_in_ep = 0;
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usb_num_out_ep = 0;
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num_out_ep = 0;
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for(i = 0; i < USB_GHWCFG2_NUM_EP; i++)
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for(i = 0; i < extract(GHWCFG2, NUM_EP); i++)
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{
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{
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if(USB_GHWCFG1_IN_EP(i))
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if(GHWCFG1 & GHWCFG1_IN_EP(i))
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usb_num_in_ep++;
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num_in_ep++;
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if(USB_GHWCFG1_OUT_EP(i))
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if(GHWCFG1 & GHWCFG1_OUT_EP(i))
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usb_num_out_ep++;
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num_out_ep++;
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logf(" EP%d: IN=%ld OUT=%ld", i, USB_GHWCFG1_IN_EP(i), USB_GHWCFG1_OUT_EP(i));
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logf(" EP%d: IN=%s OUT=%s", i,
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GHWCFG1 & GHWCFG1_IN_EP(i) ? "yes" : "no",
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GHWCFG1 & GHWCFG1_OUT_EP(i) ? "yes" : "no");
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}
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}
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if(usb_num_in_ep != USB_GHWCFG4_NUM_IN_EP)
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if(num_in_ep != GHWCFG4_NUM_IN_EP)
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panicf("usb: num in ep mismatch(%d,%lu)", usb_num_in_ep, USB_GHWCFG4_NUM_IN_EP);
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panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, GHWCFG4_NUM_IN_EP);
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if(usb_num_in_ep != USB_NUM_IN_EP)
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if(num_in_ep != NUM_IN_EP)
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panicf("usb: num in ep static mismatch(%u,%u)", usb_num_in_ep, USB_NUM_IN_EP);
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panicf("usb: num in ep static mismatch(%u,%u)", num_in_ep, NUM_IN_EP);
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if(usb_num_out_ep != USB_NUM_OUT_EP)
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if(num_out_ep != NUM_OUT_EP)
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panicf("usb: num out ep static mismatch(%u,%u)", usb_num_out_ep, USB_NUM_OUT_EP);
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panicf("usb: num out ep static mismatch(%u,%u)", num_out_ep, NUM_OUT_EP);
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logf("%d in ep, %d out ep", usb_num_in_ep, usb_num_out_ep);
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logf("%d in ep, %d out ep", num_in_ep, num_out_ep);
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logf("initial:");
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logf("initial:");
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logf(" tot fifo sz: %lx", USB_GHWCFG3_DFIFO_LEN);
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logf(" tot fifo sz: %lx", GHWCFG3_DFIFO_LEN);
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logf(" rx fifo: [%04x,+%4lx]", 0, USB_GRXFSIZ);
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logf(" rx fifo: [%04x,+%4lx]", 0, GRXFSIZ);
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logf(" nptx fifo: [%04lx,+%4lx]", USB_GET_FIFOSIZE_START_ADR(USB_GNPTXFSIZ),
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logf(" nptx fifo: [%04lx,+%4lx]", GET_FIFOSIZE_START_ADR(GNPTXFSIZ),
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USB_GET_FIFOSIZE_DEPTH(USB_GNPTXFSIZ));
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GET_FIFOSIZE_DEPTH(GNPTXFSIZ));
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|
||||||
#ifdef USB_USE_CUSTOM_FIFO_LAYOUT
|
#ifdef USE_CUSTOM_FIFO_LAYOUT
|
||||||
/* Setup FIFOs */
|
/* Setup FIFOs */
|
||||||
/* Organize FIFO as follow:
|
/* Organize FIFO as follow:
|
||||||
* 0 -> rxfsize : RX fifo
|
* 0 -> rxfsize : RX fifo
|
||||||
|
|
@ -301,38 +303,38 @@ static void core_dev_init(void)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
unsigned short adr = 0;
|
unsigned short adr = 0;
|
||||||
unsigned short depth = USB_RX_FIFO_SIZE;
|
unsigned short depth = RX_FIFO_SIZE;
|
||||||
USB_GRXFSIZ = depth;
|
GRXFSIZ = depth;
|
||||||
adr += depth;
|
adr += depth;
|
||||||
depth = USB_NPTX_FIFO_SIZE;
|
depth = NPTX_FIFO_SIZE;
|
||||||
USB_GNPTXFSIZ = USB_MAKE_FIFOSIZE_DATA(adr, depth);
|
GNPTXFSIZ = MAKE_FIFOSIZE_DATA(adr, depth);
|
||||||
adr += depth;
|
adr += depth;
|
||||||
|
|
||||||
for(i = 1; i <= USB_NUM_IN_EP; i++)
|
for(i = 1; i <= NUM_IN_EP; i++)
|
||||||
{
|
{
|
||||||
depth = USB_EPTX_FIFO_SIZE;
|
depth = EPTX_FIFO_SIZE;
|
||||||
USB_DIEPTXFSIZ(i) = USB_MAKE_FIFOSIZE_DATA(adr, depth);
|
DIEPTXFSIZ(i) = MAKE_FIFOSIZE_DATA(adr, depth);
|
||||||
adr += depth;
|
adr += depth;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(adr > USB_DATA_FIFO_DEPTH)
|
if(adr > DATA_FIFO_DEPTH)
|
||||||
panicf("usb: total data fifo size exceeded");
|
panicf("usb: total data fifo size exceeded");
|
||||||
#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */
|
#endif /* USE_CUSTOM_FIFO_LAYOUT */
|
||||||
|
|
||||||
for(i = 1; i <= USB_NUM_IN_EP; i++)
|
for(i = 1; i <= NUM_IN_EP; i++)
|
||||||
{
|
{
|
||||||
logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i,
|
logf(" dieptx fifo(%2u): [%04lx,+%4lx]", i,
|
||||||
USB_GET_FIFOSIZE_START_ADR(USB_DIEPTXFSIZ(i)),
|
GET_FIFOSIZE_START_ADR(DIEPTXFSIZ(i)),
|
||||||
USB_GET_FIFOSIZE_DEPTH(USB_DIEPTXFSIZ(i)));
|
GET_FIFOSIZE_DEPTH(DIEPTXFSIZ(i)));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Setup interrupt masks for endpoints */
|
/* Setup interrupt masks for endpoints */
|
||||||
/* Setup interrupt masks */
|
/* Setup interrupt masks */
|
||||||
USB_DOEPMSK = USB_DOEPINT_setup | USB_DOEPINT_xfercompl | USB_DOEPINT_ahberr
|
DOEPMSK = DOEPINT_setup | DOEPINT_xfercompl | DOEPINT_ahberr
|
||||||
| USB_DOEPINT_epdisabled;
|
| DOEPINT_epdisabled;
|
||||||
USB_DIEPMSK = USB_DIEPINT_xfercompl | USB_DIEPINT_timeout
|
DIEPMSK = DIEPINT_xfercompl | DIEPINT_timeout
|
||||||
| USB_DIEPINT_epdisabled | USB_DIEPINT_ahberr;
|
| DIEPINT_epdisabled | DIEPINT_ahberr;
|
||||||
USB_DAINTMSK = 0xffffffff;
|
DAINTMSK = 0xffffffff;
|
||||||
|
|
||||||
reset_endpoints();
|
reset_endpoints();
|
||||||
|
|
||||||
|
|
@ -340,50 +342,50 @@ static void core_dev_init(void)
|
||||||
/* only dump them for now, leave threshold disabled */
|
/* only dump them for now, leave threshold disabled */
|
||||||
/*
|
/*
|
||||||
logf("threshold control:");
|
logf("threshold control:");
|
||||||
logf(" non_iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_non_iso_thr_en) ? 1 : 0);
|
logf(" non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0);
|
||||||
logf(" iso_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_iso_thr_en) ? 1 : 0);
|
logf(" iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0);
|
||||||
logf(" tx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_tx_thr_len_bits) >> USB_DTHRCTL_tx_thr_len_bit_pos);
|
logf(" tx_thr_len: %lu", (DTHRCTL & DTHRCTL_tx_thr_len_bits) >> DTHRCTL_tx_thr_len_bit_pos);
|
||||||
logf(" rx_thr_en: %d", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_en) ? 1 : 0);
|
logf(" rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0);
|
||||||
logf(" rx_thr_len: %lu", (USB_DTHRCTL & USB_DTHRCTL_rx_thr_len_bits) >> USB_DTHRCTL_rx_thr_len_bit_pos);
|
logf(" rx_thr_len: %lu", (DTHRCTL & DTHRCTL_rx_thr_len_bits) >> DTHRCTL_rx_thr_len_bit_pos);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
USB_DTHRCTL = 0;
|
DTHRCTL = 0;
|
||||||
|
|
||||||
/* enable USB interrupts */
|
/* enable USB interrupts */
|
||||||
usb_enable_device_interrupts();
|
enable_device_interrupts();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void core_init(void)
|
static void core_init(void)
|
||||||
{
|
{
|
||||||
/* Disconnect */
|
/* Disconnect */
|
||||||
USB_DCTL |= USB_DCTL_sftdiscon;
|
DCTL |= DCTL_sftdiscon;
|
||||||
/* Select UTMI+ 16 */
|
/* Select UTMI+ 16 */
|
||||||
USB_GUSBCFG |= USB_GUSBCFG_phy_if;
|
GUSBCFG |= GUSBCFG_phy_if;
|
||||||
|
|
||||||
/* fixme: the current code is for internal DMA only, the clip+ architecture
|
/* fixme: the current code is for internal DMA only, the clip+ architecture
|
||||||
* define the internal DMA model */
|
* define the internal DMA model */
|
||||||
/* Set burstlen and enable DMA*/
|
/* Set burstlen and enable DMA*/
|
||||||
USB_GAHBCFG = (USB_GAHBCFG_INT_DMA_BURST_INCR4 << USB_GAHBCFG_hburstlen_bit_pos)
|
GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bit_pos)
|
||||||
| USB_GAHBCFG_dma_enable;
|
| GAHBCFG_dma_enable;
|
||||||
/* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
|
/* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
|
||||||
USB_GUSBCFG &= ~(USB_GUSBCFG_srpcap | USB_GUSBCFG_hnpcapp);
|
GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp);
|
||||||
|
|
||||||
/* perform device model specific init */
|
/* perform device model specific init */
|
||||||
core_dev_init();
|
core_dev_init();
|
||||||
|
|
||||||
/* Reconnect */
|
/* Reconnect */
|
||||||
USB_DCTL &= ~USB_DCTL_sftdiscon;
|
DCTL &= ~DCTL_sftdiscon;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void usb_enable_global_interrupts(void)
|
static void enable_global_interrupts(void)
|
||||||
{
|
{
|
||||||
VIC_INT_ENABLE = INTERRUPT_USB;
|
VIC_INT_ENABLE = INTERRUPT_USB;
|
||||||
USB_GAHBCFG |= USB_GAHBCFG_glblintrmsk;
|
GAHBCFG |= GAHBCFG_glblintrmsk;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void usb_disable_global_interrupts(void)
|
static void disable_global_interrupts(void)
|
||||||
{
|
{
|
||||||
USB_GAHBCFG &= ~USB_GAHBCFG_glblintrmsk;
|
GAHBCFG &= ~GAHBCFG_glblintrmsk;
|
||||||
VIC_INT_EN_CLEAR = INTERRUPT_USB;
|
VIC_INT_EN_CLEAR = INTERRUPT_USB;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -392,11 +394,11 @@ void usb_drv_init(void)
|
||||||
logf("usb_drv_init");
|
logf("usb_drv_init");
|
||||||
/* Enable PHY and clocks (but leave pullups disabled) */
|
/* Enable PHY and clocks (but leave pullups disabled) */
|
||||||
as3525v2_connect();
|
as3525v2_connect();
|
||||||
logf("usb: synopsis id: %lx", USB_GSNPSID);
|
logf("usb: synopsis id: %lx", GSNPSID);
|
||||||
/* Core init */
|
/* Core init */
|
||||||
core_init();
|
core_init();
|
||||||
/* Enable global interrupts */
|
/* Enable global interrupts */
|
||||||
usb_enable_global_interrupts();
|
enable_global_interrupts();
|
||||||
}
|
}
|
||||||
|
|
||||||
void usb_drv_exit(void)
|
void usb_drv_exit(void)
|
||||||
|
|
@ -404,23 +406,23 @@ void usb_drv_exit(void)
|
||||||
logf("usb_drv_exit");
|
logf("usb_drv_exit");
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool handle_usb_reset(void)
|
static bool handle_reset(void)
|
||||||
{
|
{
|
||||||
logf("usb: bus reset");
|
logf("usb: bus reset");
|
||||||
|
|
||||||
/* Clear the Remote Wakeup Signalling */
|
/* Clear the Remote Wakeup Signalling */
|
||||||
USB_DCTL &= ~USB_DCTL_rmtwkupsig;
|
DCTL &= ~DCTL_rmtwkupsig;
|
||||||
|
|
||||||
/* Flush FIFOs */
|
/* Flush FIFOs */
|
||||||
usb_flush_tx_fifos(0x10);
|
flush_tx_fifos(0x10);
|
||||||
|
|
||||||
/* Flush the Learning Queue */
|
/* Flush the Learning Queue */
|
||||||
USB_GRSTCTL = USB_GRSTCTL_intknqflsh;
|
GRSTCTL = GRSTCTL_intknqflsh;
|
||||||
|
|
||||||
reset_endpoints();
|
reset_endpoints();
|
||||||
|
|
||||||
/* Reset Device Address */
|
/* Reset Device Address */
|
||||||
USB_DCFG &= ~USB_DCFG_devadr_bits;
|
DCFG &= ~DCFG_devadr_bits;
|
||||||
|
|
||||||
usb_core_bus_reset();
|
usb_core_bus_reset();
|
||||||
|
|
||||||
|
|
@ -432,51 +434,51 @@ static bool handle_enum_done(void)
|
||||||
logf("usb: enum done");
|
logf("usb: enum done");
|
||||||
|
|
||||||
/* read speed */
|
/* read speed */
|
||||||
logf("DSTS: %lx", USB_DSTS);
|
logf("DSTS: %lx", DSTS);
|
||||||
logf("DOEPCTL0=%lx", USB_DOEPCTL(0));
|
logf("DOEPCTL0=%lx", DOEPCTL(0));
|
||||||
logf("DOEPTSIZ=%lx", USB_DOEPTSIZ(0));
|
logf("DOEPTSIZ=%lx", DOEPTSIZ(0));
|
||||||
logf("DIEPCTL0=%lx", USB_DIEPCTL(0));
|
logf("DIEPCTL0=%lx", DIEPCTL(0));
|
||||||
logf("DOEPMSK=%lx", USB_DOEPMSK);
|
logf("DOEPMSK=%lx", DOEPMSK);
|
||||||
logf("DIEPMSK=%lx", USB_DIEPMSK);
|
logf("DIEPMSK=%lx", DIEPMSK);
|
||||||
logf("DAINTMSK=%lx", USB_DAINTMSK);
|
logf("DAINTMSK=%lx", DAINTMSK);
|
||||||
logf("DAINT=%lx", USB_DAINT);
|
logf("DAINT=%lx", DAINT);
|
||||||
logf("GINTSTS=%lx", USB_GINTSTS);
|
logf("GINTSTS=%lx", GINTSTS);
|
||||||
logf("GINTMSK=%lx", USB_GINTMSK);
|
logf("GINTMSK=%lx", GINTMSK);
|
||||||
logf("DCTL=%lx", USB_DCTL);
|
logf("DCTL=%lx", DCTL);
|
||||||
logf("GAHBCFG=%lx", USB_GAHBCFG);
|
logf("GAHBCFG=%lx", GAHBCFG);
|
||||||
logf("GUSBCFG=%lx", USB_GUSBCFG);
|
logf("GUSBCFG=%lx", GUSBCFG);
|
||||||
logf("DCFG=%lx", USB_DCFG);
|
logf("DCFG=%lx", DCFG);
|
||||||
logf("DTHRCTL=%lx", USB_DTHRCTL);
|
logf("DTHRCTL=%lx", DTHRCTL);
|
||||||
|
|
||||||
switch((USB_DSTS & USB_DSTS_enumspd_bits) >> USB_DSTS_enumspd_bit_pos)
|
switch((DSTS & DSTS_enumspd_bits) >> DSTS_enumspd_bit_pos)
|
||||||
{
|
{
|
||||||
case USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
|
case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
|
||||||
logf("usb: HS");
|
logf("usb: HS");
|
||||||
break;
|
break;
|
||||||
case USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
|
case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
|
||||||
case USB_DSTS_ENUMSPD_FS_PHY_48MHZ:
|
case DSTS_ENUMSPD_FS_PHY_48MHZ:
|
||||||
logf("usb: FS");
|
logf("usb: FS");
|
||||||
break;
|
break;
|
||||||
case USB_DSTS_ENUMSPD_LS_PHY_6MHZ:
|
case DSTS_ENUMSPD_LS_PHY_6MHZ:
|
||||||
panicf("usb: LS is not supported");
|
panicf("usb: LS is not supported");
|
||||||
}
|
}
|
||||||
|
|
||||||
USB_DOEPCTL(0) = (USB_DOEPCTL(0) & ~USB_DEPCTL_mps_bits)
|
DOEPCTL(0) = (DOEPCTL(0) & ~DEPCTL_mps_bits)
|
||||||
| (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos);
|
| (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
|
||||||
USB_DIEPCTL(0) = (USB_DIEPCTL(0) & ~USB_DEPCTL_mps_bits)
|
DIEPCTL(0) = (DIEPCTL(0) & ~DEPCTL_mps_bits)
|
||||||
| (USB_DEPCTL_MPS_64 << USB_DEPCTL_mps_bit_pos);
|
| (DEPCTL_MPS_64 << DEPCTL_mps_bit_pos);
|
||||||
|
|
||||||
unsigned i, ep;
|
unsigned i, ep;
|
||||||
FOR_EACH_IN_EP(i, ep)
|
FOR_EACH_IN_EP(i, ep)
|
||||||
USB_DIEPCTL(ep) = (USB_DIEPCTL(ep) & ~USB_DEPCTL_mps_bits)
|
DIEPCTL(ep) = (DIEPCTL(ep) & ~DEPCTL_mps_bits)
|
||||||
| (512 << USB_DEPCTL_mps_bit_pos);
|
| (512 << DEPCTL_mps_bit_pos);
|
||||||
|
|
||||||
FOR_EACH_OUT_EP(i, ep)
|
FOR_EACH_OUT_EP(i, ep)
|
||||||
USB_DOEPCTL(ep) = (USB_DOEPCTL(ep) & ~USB_DEPCTL_mps_bits)
|
DOEPCTL(ep) = (DOEPCTL(ep) & ~DEPCTL_mps_bits)
|
||||||
| (512 << USB_DEPCTL_mps_bit_pos);
|
| (512 << DEPCTL_mps_bit_pos);
|
||||||
|
|
||||||
USB_DOEPTSIZ(0) = (1 << USB_DEPTSIZ0_supcnt_bit_pos)
|
DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bit_pos)
|
||||||
| (1 << USB_DEPTSIZ0_pkcnt_bit_pos)
|
| (1 << DEPTSIZ0_pkcnt_bit_pos)
|
||||||
| 64;
|
| 64;
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
|
|
@ -499,7 +501,7 @@ static void dump_intsts(char *buffer, size_t size, unsigned long sts)
|
||||||
(void) size;
|
(void) size;
|
||||||
buffer[0] = 0;
|
buffer[0] = 0;
|
||||||
#define DUMP_CASE(name) \
|
#define DUMP_CASE(name) \
|
||||||
if(sts & USB_GINTMSK_##name) strcat(buffer, #name " ");
|
if(sts & GINTMSK_##name) strcat(buffer, #name " ");
|
||||||
|
|
||||||
DUMP_CASE(modemismatch)
|
DUMP_CASE(modemismatch)
|
||||||
DUMP_CASE(otgintr)
|
DUMP_CASE(otgintr)
|
||||||
|
|
@ -536,7 +538,7 @@ void INT_USB(void)
|
||||||
{
|
{
|
||||||
/* some bits in GINTSTS can be set even though we didn't enable the interrupt source
|
/* some bits in GINTSTS can be set even though we didn't enable the interrupt source
|
||||||
* so AND it with the actual mask */
|
* so AND it with the actual mask */
|
||||||
unsigned long sts = USB_GINTSTS & USB_GINTMSK;
|
unsigned long sts = GINTSTS & GINTMSK;
|
||||||
unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */
|
unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */
|
||||||
|
|
||||||
#define HANDLED_CASE(bitmask, callfn) \
|
#define HANDLED_CASE(bitmask, callfn) \
|
||||||
|
|
@ -553,25 +555,25 @@ void INT_USB(void)
|
||||||
goto Lunhandled;
|
goto Lunhandled;
|
||||||
|
|
||||||
/* device part */
|
/* device part */
|
||||||
HANDLED_CASE(USB_GINTMSK_usbreset, handle_usb_reset)
|
HANDLED_CASE(GINTMSK_usbreset, handle_reset)
|
||||||
HANDLED_CASE(USB_GINTMSK_enumdone, handle_enum_done)
|
HANDLED_CASE(GINTMSK_enumdone, handle_enum_done)
|
||||||
/*
|
/*
|
||||||
HANDLED_CASE(USB_GINTMSK_inepintr, handle_in_ep_int)
|
HANDLED_CASE(GINTMSK_inepintr, handle_in_ep_int)
|
||||||
HANDLED_CASE(USB_GINTMSK_outepintr, handle_out_ep_int)
|
HANDLED_CASE(GINTMSK_outepintr, handle_out_ep_int)
|
||||||
*/
|
*/
|
||||||
UNHANDLED_CASE(USB_GINTMSK_outepintr)
|
UNHANDLED_CASE(GINTMSK_outepintr)
|
||||||
UNHANDLED_CASE(USB_GINTMSK_inepintr)
|
UNHANDLED_CASE(GINTMSK_inepintr)
|
||||||
|
|
||||||
/* common part */
|
/* common part */
|
||||||
UNHANDLED_CASE(USB_GINTMSK_otgintr)
|
UNHANDLED_CASE(GINTMSK_otgintr)
|
||||||
UNHANDLED_CASE(USB_GINTMSK_conidstschng)
|
UNHANDLED_CASE(GINTMSK_conidstschng)
|
||||||
UNHANDLED_CASE(USB_GINTMSK_disconnect)
|
UNHANDLED_CASE(GINTMSK_disconnect)
|
||||||
|
|
||||||
/* unlisted ones */
|
/* unlisted ones */
|
||||||
if(sts & ~handled_one)
|
if(sts & ~handled_one)
|
||||||
goto Lunhandled;
|
goto Lunhandled;
|
||||||
|
|
||||||
USB_GINTSTS = USB_GINTSTS;
|
GINTSTS = GINTSTS;
|
||||||
|
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -23,254 +23,306 @@
|
||||||
|
|
||||||
#include "as3525v2.h"
|
#include "as3525v2.h"
|
||||||
|
|
||||||
|
/* All multi-bit fields in the driver use the following convention.
|
||||||
|
* If the register name is NAME, then there is one define NAME_bit_pos
|
||||||
|
* which holds the bit position and one define NAME_bits which holds
|
||||||
|
* a mask of the bits within the register.
|
||||||
|
* These macros allow easy access and construction of such fields */
|
||||||
|
/* Usage:
|
||||||
|
* - extract(reg_name,field_name)
|
||||||
|
note: the field_name must not be prefix with the reg name */
|
||||||
|
#define extract(reg_name, field_name) \
|
||||||
|
((reg_name & reg_name##_##field_name##_bits) >> reg_name##_##field_name##_bit_pos)
|
||||||
|
|
||||||
#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
|
#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Core Global Registers
|
* Core Global Registers
|
||||||
*/
|
*/
|
||||||
#define USB_BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
|
#define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
|
||||||
|
|
||||||
#define USB_GOTGCTL USB_BASE_REG(0x000) /** OTG Control and Status Register */
|
/** OTG Control and Status Register */
|
||||||
#define USB_GOTGINT USB_BASE_REG(0x004) /** OTG Interrupt Register */
|
#define GOTGCTL BASE_REG(0x000)
|
||||||
#define USB_GAHBCFG USB_BASE_REG(0x008) /** Core AHB Configuration Register */
|
|
||||||
#define USB_GUSBCFG USB_BASE_REG(0x00C) /** Core USB Configuration Register */
|
/** OTG Interrupt Register */
|
||||||
#define USB_GRSTCTL USB_BASE_REG(0x010) /** Core Reset Register */
|
#define GOTGINT BASE_REG(0x004)
|
||||||
#define USB_GINTSTS USB_BASE_REG(0x014) /** Core Interrupt Register */
|
|
||||||
#define USB_GINTMSK USB_BASE_REG(0x018) /** Core Interrupt Mask Register */
|
/** Core AHB Configuration Register */
|
||||||
#define USB_GRXSTSR USB_BASE_REG(0x01C) /** Receive Status Debug Read Register (Read Only) */
|
#define GAHBCFG BASE_REG(0x008)
|
||||||
#define USB_GRXSTSP USB_BASE_REG(0x020) /** Receive Status Read /Pop Register (Read Only) */
|
#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
|
||||||
#define USB_GRXFSIZ USB_BASE_REG(0x024) /** Receive FIFO Size Register */
|
#define GAHBCFG_hburstlen_bit_pos 1
|
||||||
#define USB_GNPTXFSIZ USB_BASE_REG(0x028) /** Periodic Transmit FIFO Size Register */
|
#define GAHBCFG_INT_DMA_BURST_SINGLE 0
|
||||||
#define USB_GNPTXSTS USB_BASE_REG(0x02C) /** Non-Periodic Transmit FIFO/Queue Status Register */
|
#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
|
||||||
#define USB_GI2CCTL USB_BASE_REG(0x030) /** I2C Access Register */
|
#define GAHBCFG_INT_DMA_BURST_INCR4 3
|
||||||
#define USB_GPVNDCTL USB_BASE_REG(0x034) /** PHY Vendor Control Register */
|
#define GAHBCFG_INT_DMA_BURST_INCR8 5
|
||||||
#define USB_GGPIO USB_BASE_REG(0x038) /** General Purpose Input/Output Register */
|
#define GAHBCFG_INT_DMA_BURST_INCR16 7
|
||||||
#define USB_GUID USB_BASE_REG(0x03C) /** User ID Register */
|
#define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
|
||||||
#define USB_GSNPSID USB_BASE_REG(0x040) /** Synopsys ID Register */
|
|
||||||
#define USB_GHWCFG1 USB_BASE_REG(0x044) /** User HW Config1 Register */
|
/** Core USB Configuration Register */
|
||||||
#define USB_GHWCFG2 USB_BASE_REG(0x048) /** User HW Config2 Register */
|
#define GUSBCFG BASE_REG(0x00C)
|
||||||
#define USB_GHWCFG3 USB_BASE_REG(0x04C) /** User HW Config3 Register */
|
#define GUSBCFG_toutcal_bit_pos 0
|
||||||
#define USB_GHWCFG4 USB_BASE_REG(0x050) /** User HW Config4 Register */
|
#define GUSBCFG_toutcal_bits (0x7 << GUSBCFG_toutcal_bit_pos)
|
||||||
|
#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
|
||||||
|
#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
|
||||||
|
#define GUSBCFG_fsintf (1 << 5)
|
||||||
|
#define GUSBCFG_physel (1 << 6)
|
||||||
|
#define GUSBCFG_ddrsel (1 << 7)
|
||||||
|
#define GUSBCFG_srpcap (1 << 8)
|
||||||
|
#define GUSBCFG_hnpcapp (1 << 9)
|
||||||
|
#define GUSBCFG_usbtrdtim_bit_pos 10
|
||||||
|
#define GUSBCFG_usbtrdtim_bits (0xf << GUSBCFG_usbtrdtim_bit_pos)
|
||||||
|
#define GUSBCFG_nptxfrwnden (1 << 14)
|
||||||
|
#define GUSBCFG_phylpwrclksel (1 << 15)
|
||||||
|
#define GUSBCFG_otgutmifssel (1 << 16)
|
||||||
|
#define GUSBCFG_ulpi_fsls (1 << 17)
|
||||||
|
#define GUSBCFG_ulpi_auto_res (1 << 18)
|
||||||
|
#define GUSBCFG_ulpi_clk_sus_m (1 << 19)
|
||||||
|
#define GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
|
||||||
|
#define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
|
||||||
|
#define GUSBCFG_term_sel_dl_pulse (1 << 22)
|
||||||
|
#define GUSBCFG_force_host_mode (1 << 29)
|
||||||
|
#define GUSBCFG_force_device_mode (1 << 30)
|
||||||
|
#define GUSBCFG_corrupt_tx_packet (1 << 31)
|
||||||
|
|
||||||
|
/** Core Reset Register */
|
||||||
|
#define GRSTCTL BASE_REG(0x010)
|
||||||
|
#define GRSTCTL_csftrst (1 << 0) /** Core soft reset */
|
||||||
|
#define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
|
||||||
|
#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
|
||||||
|
#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
|
||||||
|
#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
|
||||||
|
#define GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */
|
||||||
|
#define GRSTCTL_txfnum_bits (0x1f << 6)
|
||||||
|
#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
|
||||||
|
|
||||||
|
/** Core Interrupt Register */
|
||||||
|
#define GINTSTS BASE_REG(0x014)
|
||||||
|
/* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
|
||||||
|
#define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */
|
||||||
|
|
||||||
|
/** Core Interrupt Mask Register */
|
||||||
|
#define GINTMSK BASE_REG(0x018)
|
||||||
|
#define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
|
||||||
|
#define GINTMSK_otgintr (1 << 2)
|
||||||
|
#define GINTMSK_sofintr (1 << 3)
|
||||||
|
#define GINTMSK_rxstsqlvl (1 << 4)
|
||||||
|
#define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
|
||||||
|
#define GINTMSK_ginnakeff (1 << 6)
|
||||||
|
#define GINTMSK_goutnakeff (1 << 7)
|
||||||
|
#define GINTMSK_i2cintr (1 << 9)
|
||||||
|
#define GINTMSK_erlysuspend (1 << 10)
|
||||||
|
#define GINTMSK_usbsuspend (1 << 11) /** USB suspend */
|
||||||
|
#define GINTMSK_usbreset (1 << 12) /** USB reset */
|
||||||
|
#define GINTMSK_enumdone (1 << 13) /** Enumeration done */
|
||||||
|
#define GINTMSK_isooutdrop (1 << 14)
|
||||||
|
#define GINTMSK_eopframe (1 << 15)
|
||||||
|
#define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
|
||||||
|
#define GINTMSK_inepintr (1 << 18) /** in pending ? */
|
||||||
|
#define GINTMSK_outepintr (1 << 19) /** out pending ? */
|
||||||
|
#define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
|
||||||
|
#define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
|
||||||
|
#define GINTMSK_portintr (1 << 24) /** Port status change ? */
|
||||||
|
#define GINTMSK_hcintr (1 << 25)
|
||||||
|
#define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
|
||||||
|
#define GINTMSK_conidstschng (1 << 28)
|
||||||
|
#define GINTMSK_disconnect (1 << 29) /** Disconnect */
|
||||||
|
#define GINTMSK_sessreqintr (1 << 30) /** Session request */
|
||||||
|
#define GINTMSK_wkupintr (1 << 31) /** Wake up */
|
||||||
|
|
||||||
|
/** Receive Status Debug Read Register (Read Only) */
|
||||||
|
#define GRXSTSR BASE_REG(0x01C)
|
||||||
|
|
||||||
|
/** Receive Status Read /Pop Register (Read Only) */
|
||||||
|
#define GRXSTSP BASE_REG(0x020)
|
||||||
|
|
||||||
|
/** Receive FIFO Size Register */
|
||||||
|
#define GRXFSIZ BASE_REG(0x024)
|
||||||
|
|
||||||
|
/** Periodic Transmit FIFO Size Register */
|
||||||
|
#define GNPTXFSIZ BASE_REG(0x028)
|
||||||
|
|
||||||
|
/** Non-Periodic Transmit FIFO/Queue Status Register */
|
||||||
|
#define GNPTXSTS BASE_REG(0x02C)
|
||||||
|
|
||||||
|
/** I2C Access Register */
|
||||||
|
#define GI2CCTL BASE_REG(0x030)
|
||||||
|
|
||||||
|
/** PHY Vendor Control Register */
|
||||||
|
#define GPVNDCTL BASE_REG(0x034)
|
||||||
|
|
||||||
|
/** General Purpose Input/Output Register */
|
||||||
|
#define GGPIO BASE_REG(0x038)
|
||||||
|
|
||||||
|
/** User ID Register */
|
||||||
|
#define GUID BASE_REG(0x03C)
|
||||||
|
|
||||||
|
/** Synopsys ID Register */
|
||||||
|
#define GSNPSID BASE_REG(0x040)
|
||||||
|
|
||||||
|
/** User HW Config1 Register */
|
||||||
|
#define GHWCFG1 BASE_REG(0x044)
|
||||||
|
#define GHWCFG1_IN_EP(ep) (1 << (2 * (ep))) /** 1 if EP(ep) has in cap */
|
||||||
|
#define GHWCFG1_OUT_EP(ep) (1 << (1 + 2 * (ep))) /** same for out */
|
||||||
|
|
||||||
|
/** User HW Config2 Register */
|
||||||
|
#define GHWCFG2 BASE_REG(0x048)
|
||||||
|
#define GHWCFG2_ARCH_bit_pos 3 /** Architecture */
|
||||||
|
#define GHWCFG2_ARCH_bits (0x3 << GHWCFG2_ARCH_bit_pos)
|
||||||
|
#define GHWCFG2_HS_PHY_TYPE_bit_pos 6 /** High speed PHY type */
|
||||||
|
#define GHWCFG2_HS_PHY_TYPE_bits (0x3 << GHWCFG2_HS_PHY_TYPE_bit_pos)
|
||||||
|
#define GHWCFG2_FS_PHY_TYPE_bit_pos 8 /** Full speed PHY type */
|
||||||
|
#define GHWCFG2_FS_PHY_TYPE_bits (0x3 << GHWCFG2_FS_PHY_TYPE_bit_pos)
|
||||||
|
#define GHWCFG2_NUM_EP_bit_pos 10 /** Number of endpoints */
|
||||||
|
#define GHWCFG2_NUM_EP_bits (0xf << GHWCFG2_NUM_EP_bit_pos)
|
||||||
|
#define GHWCFG2_DYN_FIFO (1 << 19) /** Dynamic FIFO */
|
||||||
|
/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_SS_PHY_TYPE */
|
||||||
|
#define PHY_TYPE_UNSUPPORTED 0
|
||||||
|
#define PHY_TYPE_UTMI 1
|
||||||
|
#define INT_DMA_ARCH 2
|
||||||
|
|
||||||
|
/** User HW Config3 Register */
|
||||||
|
#define GHWCFG3 BASE_REG(0x04C)
|
||||||
|
|
||||||
|
/** User HW Config4 Register */
|
||||||
|
#define GHWCFG4 BASE_REG(0x050)
|
||||||
|
|
||||||
/* 1<=ep<=15, don't use ep=0 !!! */
|
/* 1<=ep<=15, don't use ep=0 !!! */
|
||||||
/** Device IN Endpoint Transmit FIFO (ep) Size Register */
|
/** Device IN Endpoint Transmit FIFO (ep) Size Register */
|
||||||
#define USB_DIEPTXFSIZ(ep) USB_BASE_REG(0x100 + 4 * (ep))
|
#define DIEPTXFSIZ(ep) BASE_REG(0x100 + 4 * (ep))
|
||||||
|
|
||||||
/** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/
|
/** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/
|
||||||
#define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \
|
#define MAKE_FIFOSIZE_DATA(startadr, depth) \
|
||||||
(((startadr) & 0xffff) | ((depth) << 16))
|
(((startadr) & 0xffff) | ((depth) << 16))
|
||||||
|
|
||||||
/** Retrieve fifo size for such registers */
|
/** Retrieve fifo size for such registers */
|
||||||
#define USB_GET_FIFOSIZE_DEPTH(data) \
|
#define GET_FIFOSIZE_DEPTH(data) \
|
||||||
((data) >> 16)
|
((data) >> 16)
|
||||||
|
|
||||||
/** Retrieve fifo start address for such registers */
|
/** Retrieve fifo start address for such registers */
|
||||||
#define USB_GET_FIFOSIZE_START_ADR(data) \
|
#define GET_FIFOSIZE_START_ADR(data) \
|
||||||
((data) & 0xffff)
|
((data) & 0xffff)
|
||||||
|
|
||||||
#define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */
|
|
||||||
#define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
|
|
||||||
#define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
|
|
||||||
#define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
|
|
||||||
#define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
|
|
||||||
#define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */
|
|
||||||
#define USB_GRSTCTL_txfnum_bits (0x1f << 6)
|
|
||||||
#define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
|
|
||||||
|
|
||||||
#define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */
|
|
||||||
#define USB_GHWCFG1_OUT_EP(ep) ((USB_GHWCFG1 >> ((ep) *2 + 1)) & 0x1)/** 1 if EP(ep) has out cap */
|
|
||||||
|
|
||||||
#define USB_GHWCFG2_ARCH ((USB_GHWCFG2 >> 3) & 0x3) /** Architecture */
|
|
||||||
#define USB_GHWCFG2_HS_PHY_TYPE ((USB_GHWCFG2 >> 6) & 0x3) /** High speed PHY type */
|
|
||||||
#define USB_GHWCFG2_FS_PHY_TYPE ((USB_GHWCFG2 >> 8) & 0x3) /** Full speed PHY type */
|
|
||||||
#define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */
|
|
||||||
#define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */
|
|
||||||
|
|
||||||
/* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */
|
|
||||||
#define USB_PHY_TYPE_UNSUPPORTED 0
|
|
||||||
#define USB_PHY_TYPE_UTMI 1
|
|
||||||
#define USB_INT_DMA_ARCH 2
|
|
||||||
|
|
||||||
#define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */
|
#define GHWCFG3_DFIFO_LEN (GHWCFG3 >> 16) /** Total fifo size */
|
||||||
|
|
||||||
#define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */
|
#define GHWCFG4_UTMI_PHY_DATA_WIDTH ((GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */
|
||||||
#define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */
|
#define GHWCFG4_DED_FIFO_EN ((GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */
|
||||||
#define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
|
#define GHWCFG4_NUM_IN_EP ((GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
|
||||||
|
|
||||||
#define USB_GUSBCFG_toutcal_bit_pos 0
|
|
||||||
#define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos)
|
|
||||||
#define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
|
|
||||||
#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
|
|
||||||
#define USB_GUSBCFG_fsintf (1 << 5)
|
|
||||||
#define USB_GUSBCFG_physel (1 << 6)
|
|
||||||
#define USB_GUSBCFG_ddrsel (1 << 7)
|
|
||||||
#define USB_GUSBCFG_srpcap (1 << 8)
|
|
||||||
#define USB_GUSBCFG_hnpcapp (1 << 9)
|
|
||||||
#define USB_GUSBCFG_usbtrdtim_bit_pos 10
|
|
||||||
#define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos)
|
|
||||||
#define USB_GUSBCFG_nptxfrwnden (1 << 14)
|
|
||||||
#define USB_GUSBCFG_phylpwrclksel (1 << 15)
|
|
||||||
#define USB_GUSBCFG_otgutmifssel (1 << 16)
|
|
||||||
#define USB_GUSBCFG_ulpi_fsls (1 << 17)
|
|
||||||
#define USB_GUSBCFG_ulpi_auto_res (1 << 18)
|
|
||||||
#define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19)
|
|
||||||
#define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
|
|
||||||
#define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
|
|
||||||
#define USB_GUSBCFG_term_sel_dl_pulse (1 << 22)
|
|
||||||
#define USB_GUSBCFG_force_host_mode (1 << 29)
|
|
||||||
#define USB_GUSBCFG_force_device_mode (1 << 30)
|
|
||||||
#define USB_GUSBCFG_corrupt_tx_packet (1 << 31)
|
|
||||||
|
|
||||||
#define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
|
|
||||||
#define USB_GAHBCFG_hburstlen_bit_pos 1
|
|
||||||
#define USB_GAHBCFG_INT_DMA_BURST_SINGLE 0
|
|
||||||
#define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
|
|
||||||
#define USB_GAHBCFG_INT_DMA_BURST_INCR4 3
|
|
||||||
#define USB_GAHBCFG_INT_DMA_BURST_INCR8 5
|
|
||||||
#define USB_GAHBCFG_INT_DMA_BURST_INCR16 7
|
|
||||||
#define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
|
|
||||||
|
|
||||||
/* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */
|
|
||||||
#define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */
|
|
||||||
|
|
||||||
#define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
|
|
||||||
#define USB_GINTMSK_otgintr (1 << 2)
|
|
||||||
#define USB_GINTMSK_sofintr (1 << 3)
|
|
||||||
#define USB_GINTMSK_rxstsqlvl (1 << 4)
|
|
||||||
#define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
|
|
||||||
#define USB_GINTMSK_ginnakeff (1 << 6)
|
|
||||||
#define USB_GINTMSK_goutnakeff (1 << 7)
|
|
||||||
#define USB_GINTMSK_i2cintr (1 << 9)
|
|
||||||
#define USB_GINTMSK_erlysuspend (1 << 10)
|
|
||||||
#define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */
|
|
||||||
#define USB_GINTMSK_usbreset (1 << 12) /** USB reset */
|
|
||||||
#define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */
|
|
||||||
#define USB_GINTMSK_isooutdrop (1 << 14)
|
|
||||||
#define USB_GINTMSK_eopframe (1 << 15)
|
|
||||||
#define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
|
|
||||||
#define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */
|
|
||||||
#define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */
|
|
||||||
#define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
|
|
||||||
#define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
|
|
||||||
#define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */
|
|
||||||
#define USB_GINTMSK_hcintr (1 << 25)
|
|
||||||
#define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
|
|
||||||
#define USB_GINTMSK_conidstschng (1 << 28)
|
|
||||||
#define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */
|
|
||||||
#define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */
|
|
||||||
#define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Device Registers Base Addresses
|
* Device Registers Base Addresses
|
||||||
*/
|
*/
|
||||||
#define USB_DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
|
#define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
|
||||||
|
|
||||||
#define USB_DCFG USB_DEV_REG(0x00) /** Device Configuration Register */
|
#define DCFG DEV_REG(0x00) /** Device Configuration Register */
|
||||||
#define USB_DCTL USB_DEV_REG(0x04) /** Device Control Register */
|
#define DCTL DEV_REG(0x04) /** Device Control Register */
|
||||||
#define USB_DSTS USB_DEV_REG(0x08) /** Device Status Register */
|
#define DSTS DEV_REG(0x08) /** Device Status Register */
|
||||||
#define USB_DIEPMSK USB_DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
|
#define DIEPMSK DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
|
||||||
#define USB_DOEPMSK USB_DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
|
#define DOEPMSK DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
|
||||||
#define USB_DAINT USB_DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
|
#define DAINT DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
|
||||||
#define USB_DAINTMSK USB_DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
|
#define DAINTMSK DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
|
||||||
#define USB_DTKNQR1 USB_DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
|
#define DTKNQR1 DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
|
||||||
#define USB_DTKNQR2 USB_DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
|
#define DTKNQR2 DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
|
||||||
#define USB_DTKNQP USB_DEV_REG(0x28) /** Device IN Token Queue Pop register */
|
#define DTKNQP DEV_REG(0x28) /** Device IN Token Queue Pop register */
|
||||||
/* fixme: those registers are not present in usb_registers.h but are in dwc_otgh_regs.h.
|
/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
|
||||||
* the previous registers exists but has a different name :( */
|
* the previous registers exists but has a different name :( */
|
||||||
#define USB_DVBUSDIS USB_DEV_REG(0x28) /** Device VBUS discharge register*/
|
#define DVBUSDIS DEV_REG(0x28) /** Device VBUS discharge register*/
|
||||||
#define USB_DVBUSPULSE USB_DEV_REG(0x2C) /** Device VBUS pulse register */
|
#define DVBUSPULSE DEV_REG(0x2C) /** Device VBUS pulse register */
|
||||||
#define USB_DTKNQR3 USB_DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
|
#define DTKNQR3 DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
|
||||||
#define USB_DTHRCTL USB_DEV_REG(0x30) /** Device Thresholding control register */
|
#define DTHRCTL DEV_REG(0x30) /** Device Thresholding control register */
|
||||||
#define USB_DTKNQR4 USB_DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
|
#define DTKNQR4 DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
|
||||||
#define USB_FFEMPTYMSK USB_DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
|
#define FFEMPTYMSK DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
|
||||||
|
|
||||||
#define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
|
#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
|
||||||
#define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
|
#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
|
||||||
#define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
|
#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
|
||||||
#define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
|
#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
|
||||||
#define USB_DCTL_tstctl_bit_pos 4 /** Test Control */
|
#define DCTL_tstctl_bit_pos 4 /** Test Control */
|
||||||
#define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos)
|
#define DCTL_tstctl_bits (0x7 << DCTL_tstctl_bit_pos)
|
||||||
#define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
|
#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
|
||||||
#define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
|
#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
|
||||||
#define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
|
#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
|
||||||
#define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
|
#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
|
||||||
/* "documented" in usb_constants.h only */
|
/* "documented" in constants.h only */
|
||||||
#define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
|
#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
|
||||||
|
|
||||||
#define USB_DCFG_devspd_bits 0x3 /** Device Speed */
|
#define DCFG_devspd_bits 0x3 /** Device Speed */
|
||||||
#define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
|
#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
|
||||||
#define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
|
#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
|
||||||
#define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
|
#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
|
||||||
#define USB_DCFG_devadr_bit_pos 4 /** Device Address */
|
#define DCFG_devadr_bit_pos 4 /** Device Address */
|
||||||
#define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos)
|
#define DCFG_devadr_bits (0x7f << DCFG_devadr_bit_pos)
|
||||||
#define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */
|
#define DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */
|
||||||
#define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos)
|
#define DCFG_perfrint_bits (0x3 << DCFG_perfrint_bit_pos)
|
||||||
#define USB_DCFG_FRAME_INTERVAL_80 0
|
#define DCFG_FRAME_INTERVAL_80 0
|
||||||
#define USB_DCFG_FRAME_INTERVAL_85 1
|
#define DCFG_FRAME_INTERVAL_85 1
|
||||||
#define USB_DCFG_FRAME_INTERVAL_90 2
|
#define DCFG_FRAME_INTERVAL_90 2
|
||||||
#define USB_DCFG_FRAME_INTERVAL_95 3
|
#define DCFG_FRAME_INTERVAL_95 3
|
||||||
|
|
||||||
#define USB_DSTS_suspsts (1 << 0) /** Suspend status */
|
#define DSTS_suspsts (1 << 0) /** Suspend status */
|
||||||
#define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */
|
#define DSTS_enumspd_bit_pos 1 /** Enumerated speed */
|
||||||
#define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos)
|
#define DSTS_enumspd_bits (0x3 << DSTS_enumspd_bit_pos)
|
||||||
#define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
|
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
|
||||||
#define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
|
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
|
||||||
#define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2
|
#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
|
||||||
#define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3
|
#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
|
||||||
#define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */
|
#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
|
||||||
#define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */
|
#define DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */
|
||||||
#define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos)
|
#define DSTS_soffn_bits (0x3fff << DSTS_soffn_bit_pos)
|
||||||
|
|
||||||
#define USB_DTHRCTL_non_iso_thr_en (1 << 0)
|
#define DTHRCTL_non_iso_thr_en (1 << 0)
|
||||||
#define USB_DTHRCTL_iso_thr_en (1 << 1)
|
#define DTHRCTL_iso_thr_en (1 << 1)
|
||||||
#define USB_DTHRCTL_tx_thr_len_bit_pos 2
|
#define DTHRCTL_tx_thr_len_bit_pos 2
|
||||||
#define USB_DTHRCTL_tx_thr_len_bits (0x1FF << USB_DTHRCTL_tx_thr_len_bit_pos)
|
#define DTHRCTL_tx_thr_len_bits (0x1FF << DTHRCTL_tx_thr_len_bit_pos)
|
||||||
#define USB_DTHRCTL_rx_thr_en (1 << 16)
|
#define DTHRCTL_rx_thr_en (1 << 16)
|
||||||
#define USB_DTHRCTL_rx_thr_len_bit_pos 17
|
#define DTHRCTL_rx_thr_len_bit_pos 17
|
||||||
#define USB_DTHRCTL_rx_thr_len_bits (0x1FF << USB_DTHRCTL_rx_thr_len_bit_pos)
|
#define DTHRCTL_rx_thr_len_bits (0x1FF << DTHRCTL_rx_thr_len_bit_pos)
|
||||||
|
|
||||||
/* 0<=ep<=15, you can use ep=0 */
|
/* 0<=ep<=15, you can use ep=0 */
|
||||||
/** Device IN Endpoint (ep) Control Register */
|
/** Device IN Endpoint (ep) Control Register */
|
||||||
#define USB_DIEPCTL(ep) USB_DEV_REG(0x100 + (ep) * 0x20)
|
#define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20)
|
||||||
/** Device IN Endpoint (ep) Interrupt Register */
|
/** Device IN Endpoint (ep) Interrupt Register */
|
||||||
#define USB_DIEPINT(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x8)
|
#define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8)
|
||||||
/** Device IN Endpoint (ep) Transfer Size Register */
|
/** Device IN Endpoint (ep) Transfer Size Register */
|
||||||
#define USB_DIEPTSIZ(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x10)
|
#define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10)
|
||||||
/** Device IN Endpoint (ep) DMA Address Register */
|
/** Device IN Endpoint (ep) DMA Address Register */
|
||||||
#define USB_DIEPDMA(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x14)
|
#define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14)
|
||||||
/** Device IN Endpoint (ep) Transmit FIFO Status Register */
|
/** Device IN Endpoint (ep) Transmit FIFO Status Register */
|
||||||
#define USB_DTXFSTS(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x18)
|
#define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18)
|
||||||
|
|
||||||
/* the following also apply to DIEPMSK */
|
/* the following also apply to DIEPMSK */
|
||||||
#define USB_DIEPINT_xfercompl (1 << 0) /** Transfer complete */
|
#define DIEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||||
#define USB_DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
#define DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||||
#define USB_DIEPINT_ahberr (1 << 2) /** AHB error */
|
#define DIEPINT_ahberr (1 << 2) /** AHB error */
|
||||||
#define USB_DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
|
#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
|
||||||
#define USB_DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
|
#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
|
||||||
#define USB_DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
|
#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
|
||||||
#define USB_DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
|
#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
|
||||||
#define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
|
#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
|
||||||
#define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
|
#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
|
||||||
|
|
||||||
/* the following also apply to DOEPMSK */
|
/* the following also apply to DOEPMSK */
|
||||||
#define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */
|
#define DOEPINT_xfercompl (1 << 0) /** Transfer complete */
|
||||||
#define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
#define DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
|
||||||
#define USB_DOEPINT_ahberr (1 << 2) /** AHB error */
|
#define DOEPINT_ahberr (1 << 2) /** AHB error */
|
||||||
#define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
|
#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
|
||||||
|
|
||||||
/* 0<=ep<=15, you can use ep=0 */
|
/* 0<=ep<=15, you can use ep=0 */
|
||||||
/** Device OUT Endpoint (ep) Control Register */
|
/** Device OUT Endpoint (ep) Control Register */
|
||||||
#define USB_DOEPCTL(ep) USB_DEV_REG(0x300 + (ep) * 0x20)
|
#define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20)
|
||||||
/** Device OUT Endpoint (ep) Frame number Register */
|
/** Device OUT Endpoint (ep) Frame number Register */
|
||||||
#define USB_DOEPFN(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x4)
|
#define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4)
|
||||||
/** Device Endpoint (ep) Interrupt Register */
|
/** Device Endpoint (ep) Interrupt Register */
|
||||||
#define USB_DOEPINT(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x8)
|
#define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8)
|
||||||
/** Device OUT Endpoint (ep) Transfer Size Register */
|
/** Device OUT Endpoint (ep) Transfer Size Register */
|
||||||
#define USB_DOEPTSIZ(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x10)
|
#define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10)
|
||||||
/** Device Endpoint (ep) DMA Address Register */
|
/** Device Endpoint (ep) DMA Address Register */
|
||||||
#define USB_DOEPDMA(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x14)
|
#define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14)
|
||||||
|
|
||||||
#define USB_PCGCCTL USB_BASE_REG(0xE00) /** Power and Clock Gating Control Register */
|
#define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */
|
||||||
|
|
||||||
|
|
||||||
/** Maximum Packet Size
|
/** Maximum Packet Size
|
||||||
|
|
@ -280,18 +332,18 @@
|
||||||
* 2'b01: 32
|
* 2'b01: 32
|
||||||
* 2'b10: 16
|
* 2'b10: 16
|
||||||
* 2'b11: 8 */
|
* 2'b11: 8 */
|
||||||
#define USB_DEPCTL_mps_bits 0x7ff
|
#define DEPCTL_mps_bits 0x7ff
|
||||||
#define USB_DEPCTL_mps_bit_pos 0
|
#define DEPCTL_mps_bit_pos 0
|
||||||
#define USB_DEPCTL_MPS_64 0
|
#define DEPCTL_MPS_64 0
|
||||||
#define USB_DEPCTL_MPS_32 1
|
#define DEPCTL_MPS_32 1
|
||||||
#define USB_DEPCTL_MPS_16 2
|
#define DEPCTL_MPS_16 2
|
||||||
#define USB_DEPCTL_MPS_8 3
|
#define DEPCTL_MPS_8 3
|
||||||
/** Next Endpoint
|
/** Next Endpoint
|
||||||
* IN EPn/IN EP0
|
* IN EPn/IN EP0
|
||||||
* OUT EPn/OUT EP0 - reserved */
|
* OUT EPn/OUT EP0 - reserved */
|
||||||
#define USB_DEPCTL_nextep_bit_pos 11
|
#define DEPCTL_nextep_bit_pos 11
|
||||||
#define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos)
|
#define DEPCTL_nextep_bits (0xf << DEPCTL_nextep_bit_pos)
|
||||||
#define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
|
#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
|
||||||
/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
|
/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
|
||||||
* This field contains the PID of the packet going to
|
* This field contains the PID of the packet going to
|
||||||
* be received or transmitted on this endpoint. The
|
* be received or transmitted on this endpoint. The
|
||||||
|
|
@ -306,28 +358,28 @@
|
||||||
* - 0: D0
|
* - 0: D0
|
||||||
* - 1: D1
|
* - 1: D1
|
||||||
*/
|
*/
|
||||||
#define USB_DEPCTL_dpid (1 << 16)
|
#define DEPCTL_dpid (1 << 16)
|
||||||
#define USB_DEPCTL_naksts (1 << 17) /** NAK Status */
|
#define DEPCTL_naksts (1 << 17) /** NAK Status */
|
||||||
/** Endpoint Type
|
/** Endpoint Type
|
||||||
* 2'b00: Control
|
* 2'b00: Control
|
||||||
* 2'b01: Isochronous
|
* 2'b01: Isochronous
|
||||||
* 2'b10: Bulk
|
* 2'b10: Bulk
|
||||||
* 2'b11: Interrupt */
|
* 2'b11: Interrupt */
|
||||||
#define USB_DEPCTL_eptype_bit_pos 18
|
#define DEPCTL_eptype_bit_pos 18
|
||||||
#define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos)
|
#define DEPCTL_eptype_bits (0x3 << DEPCTL_eptype_bit_pos)
|
||||||
/** Snoop Mode
|
/** Snoop Mode
|
||||||
* OUT EPn/OUT EP0
|
* OUT EPn/OUT EP0
|
||||||
* IN EPn/IN EP0 - reserved */
|
* IN EPn/IN EP0 - reserved */
|
||||||
#define USB_DEPCTL_snp (1 << 20)
|
#define DEPCTL_snp (1 << 20)
|
||||||
#define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */
|
#define DEPCTL_stall (1 << 21) /** Stall Handshake */
|
||||||
/** Tx Fifo Number
|
/** Tx Fifo Number
|
||||||
* IN EPn/IN EP0
|
* IN EPn/IN EP0
|
||||||
* OUT EPn/OUT EP0 - reserved */
|
* OUT EPn/OUT EP0 - reserved */
|
||||||
#define USB_DEPCTL_txfnum_bit_pos 22
|
#define DEPCTL_txfnum_bit_pos 22
|
||||||
#define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos)
|
#define DEPCTL_txfnum_bits (0xf << DEPCTL_txfnum_bit_pos)
|
||||||
|
|
||||||
#define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */
|
#define DEPCTL_cnak (1 << 26) /** Clear NAK */
|
||||||
#define USB_DEPCTL_snak (1 << 27) /** Set NAK */
|
#define DEPCTL_snak (1 << 27) /** Set NAK */
|
||||||
/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
|
/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
|
||||||
* Writing to this field sets the Endpoint DPID (DPID)
|
* Writing to this field sets the Endpoint DPID (DPID)
|
||||||
* field in this register to DATA0. Set Even
|
* field in this register to DATA0. Set Even
|
||||||
|
|
@ -336,7 +388,7 @@
|
||||||
* (micro)frame (EO_FrNum) field to even (micro)
|
* (micro)frame (EO_FrNum) field to even (micro)
|
||||||
* frame.
|
* frame.
|
||||||
*/
|
*/
|
||||||
#define USB_DEPCTL_setd0pid (1 << 28)
|
#define DEPCTL_setd0pid (1 << 28)
|
||||||
/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
|
/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
|
||||||
* Writing to this field sets the Endpoint DPID (DPID)
|
* Writing to this field sets the Endpoint DPID (DPID)
|
||||||
* field in this register to DATA1 Set Odd
|
* field in this register to DATA1 Set Odd
|
||||||
|
|
@ -344,52 +396,52 @@
|
||||||
* Writing to this field sets the Even/Odd
|
* Writing to this field sets the Even/Odd
|
||||||
* (micro)frame (EO_FrNum) field to odd (micro) frame.
|
* (micro)frame (EO_FrNum) field to odd (micro) frame.
|
||||||
*/
|
*/
|
||||||
#define USB_DEPCTL_setd1pid (1 << 29)
|
#define DEPCTL_setd1pid (1 << 29)
|
||||||
#define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */
|
#define DEPCTL_epdis (1 << 30) /** Endpoint disable */
|
||||||
#define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */
|
#define DEPCTL_epena (1 << 31) /** Endpoint enable */
|
||||||
|
|
||||||
|
|
||||||
/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
|
/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
|
||||||
#define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */
|
#define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */
|
||||||
#define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */
|
#define DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */
|
||||||
#define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos)
|
#define DEPTSIZ_pkcnt_bits (0x3ff << DEPTSIZ_pkcnt_bit_pos)
|
||||||
#define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */
|
#define DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */
|
||||||
#define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos)
|
#define DEPTSIZ_mc_bits (0x3 << DEPTSIZ_mc_bit_pos)
|
||||||
|
|
||||||
/* idem but for i=0 */
|
/* idem but for i=0 */
|
||||||
#define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */
|
#define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */
|
||||||
#define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */
|
#define DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */
|
||||||
#define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos)
|
#define DEPTSIZ0_pkcnt_bits (0x1 << DEPTSIZ0_pkcnt_bit_pos)
|
||||||
#define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
|
#define DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
|
||||||
#define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos)
|
#define DEPTSIZ0_supcnt_bits (0x3 << DEPTSIZ0_supcnt_bit_pos)
|
||||||
|
|
||||||
/* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */
|
/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
|
||||||
#define USB_DAINT_IN_EP(i) (1 << (i))
|
#define DAINT_IN_EP(i) (1 << (i))
|
||||||
#define USB_DAINT_OUT_EP(i) (1 << ((i) + 16))
|
#define DAINT_OUT_EP(i) (1 << ((i) + 16))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Parameters
|
* Parameters
|
||||||
*/
|
*/
|
||||||
#define USB_USE_CUSTOM_FIFO_LAYOUT
|
#define USE_CUSTOM_FIFO_LAYOUT
|
||||||
|
|
||||||
#ifdef USB_USE_CUSTOM_FIFO_LAYOUT
|
#ifdef USE_CUSTOM_FIFO_LAYOUT
|
||||||
/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
|
/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
|
||||||
* NOTE: this is a hardware parameter, it cannot be changed ! */
|
* NOTE: this is a hardware parameter, it cannot be changed ! */
|
||||||
#define USB_DATA_FIFO_DEPTH 0x535
|
#define DATA_FIFO_DEPTH 0x535
|
||||||
/* size of the FX fifo */
|
/* size of the FX fifo */
|
||||||
#define USB_RX_FIFO_SIZE 0x100
|
#define RX_FIFO_SIZE 0x100
|
||||||
/* size of the non periodic TX fifo */
|
/* size of the non periodic TX fifo */
|
||||||
#define USB_NPTX_FIFO_SIZE 0x100
|
#define NPTX_FIFO_SIZE 0x100
|
||||||
/* size of each TX ep fifo size */
|
/* size of each TX ep fifo size */
|
||||||
#define USB_EPTX_FIFO_SIZE 0x100
|
#define EPTX_FIFO_SIZE 0x100
|
||||||
#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */
|
#endif /* USE_CUSTOM_FIFO_LAYOUT */
|
||||||
|
|
||||||
/* Number of IN/OUT endpoints */
|
/* Number of IN/OUT endpoints */
|
||||||
#define USB_NUM_IN_EP 3
|
#define NUM_IN_EP 3
|
||||||
#define USB_NUM_OUT_EP 2
|
#define NUM_OUT_EP 2
|
||||||
|
|
||||||
/* List of IN enpoints */
|
/* List of IN enpoints */
|
||||||
#define USB_IN_EP_LIST 1, 3, 5
|
#define IN_EP_LIST 1, 3, 5
|
||||||
#define USB_OUT_EP_LIST 2, 4
|
#define OUT_EP_LIST 2, 4
|
||||||
|
|
||||||
#endif /* __USB_DRV_AS3525v2_H__ */
|
#endif /* __USB_DRV_AS3525v2_H__ */
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue