D2: Enable ARM cache coherency functions (eg. during codec load), which should eliminate data aborts/freezes on track changes. NOTE: The linker script reserves space at the end of DRAM for the TTB, but this is not currently used.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22595 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase 2009-09-01 21:35:37 +00:00
parent 166606cea0
commit 19a5dfea28
5 changed files with 13 additions and 1 deletions

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@ -61,6 +61,10 @@ OUTPUT_FORMAT(elf32-littlemips)
#define TTB_SIZE (0x4000)
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE
#elif CONFIG_CPU==TCC7801
#include "cpu.h"
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE
#elif CONFIG_CPU==AS3525
#include "cpu.h"
#define DRAMORIG DRAM_ORIG

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@ -1264,6 +1264,7 @@ target/arm/tcc780x/cowond2/power-cowond2.c
target/arm/tcc780x/cowond2/powermgmt-cowond2.c
target/arm/tcc780x/cowond2/backlight-cowond2.c
target/arm/usb-tcc.c
target/arm/mmu-arm.S
#ifndef BOOTLOADER
target/arm/tcc780x/timer-tcc780x.c
target/arm/wmcodec-telechips.c

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@ -21,6 +21,11 @@
#ifndef __TCC780X_H__
#define __TCC780X_H__
#define TTB_SIZE (0x4000)
/* must be 16Kb (0x4000) aligned */
#define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)
#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) /* End of memory */
/* General-purpose IO */
#define PORTCFG0 (*(volatile unsigned long *)0xF005A000)

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@ -15,7 +15,8 @@ STARTUP(target/arm/tcc780x/crt0.o)
#define STUBOFFSET 0
#endif
#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
#include "cpu.h"
#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE - TTB_SIZE
#define DRAMORIG 0x20000000 + STUBOFFSET
#define ITCMORIG 0x00000000

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@ -22,6 +22,7 @@
#define SYSTEM_TARGET_H
#include "system-arm.h"
#include "mmu-arm.h"
#define CPUFREQ_DEFAULT 32000000
#define CPUFREQ_NORMAL 48000000