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x1000: internal codec audio driver
Change-Id: I2eb551ec6b593951c33ae6b93df2a23dc6612c43
This commit is contained in:
Aidan MacDonald
parent
15e3d37110
commit
18b3e91707
4 changed files with 481 additions and 0 deletions
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@ -1669,6 +1669,10 @@ target/mips/ingenic_x1000/spl-start.S
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target/mips/ingenic_x1000/spl-x1000.c
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common/ucl_decompress.c
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#endif
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#if (defined(HAVE_X1000_ICODEC_PLAY) || defined(HAVE_X1000_ICODEC_REC)) \
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&& !defined(BOOTLOADER)
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drivers/audio/x1000-codec.c
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#endif
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#endif /* CONFIG_CPU == X1000 */
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#if defined(ONDA_VX747) || defined(ONDA_VX747P) || defined(ONDA_VX777)
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286
firmware/drivers/audio/x1000-codec.c
Normal file
286
firmware/drivers/audio/x1000-codec.c
Normal file
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@ -0,0 +1,286 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021-2022 Aidan MacDonald
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* Copyright 2014 Ingenic Semiconductor Co.,Ltd
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* cscheng <shicheng.cheng@ingenic.com>
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* sound/soc/ingenic/icodec/icdc_d3.c
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* ALSA SoC Audio driver -- ingenic internal codec (icdc_d3) driver
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "x1000-codec.h"
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#include "audiohw.h"
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#include "pcm_sampr.h"
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#include "kernel.h"
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#include "x1000/aic.h"
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static const uint8_t fsel_to_hw[HW_NUM_FREQ] = {
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[0 ... HW_NUM_FREQ-1] = 0,
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HW_HAVE_8_([HW_FREQ_8] = 0,)
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HW_HAVE_11_([HW_FREQ_11] = 1,)
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HW_HAVE_12_([HW_FREQ_12] = 2,)
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HW_HAVE_16_([HW_FREQ_16] = 3,)
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HW_HAVE_22_([HW_FREQ_22] = 4,)
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HW_HAVE_24_([HW_FREQ_24] = 5,)
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HW_HAVE_32_([HW_FREQ_32] = 6,)
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HW_HAVE_44_([HW_FREQ_44] = 7,)
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HW_HAVE_48_([HW_FREQ_48] = 8,)
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HW_HAVE_88_([HW_FREQ_88] = 9,)
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HW_HAVE_96_([HW_FREQ_96] = 10,)
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HW_HAVE_176_([HW_FREQ_176] = 11,)
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HW_HAVE_192_([HW_FREQ_192] = 12,)
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};
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void x1000_icodec_open(void)
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{
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/* Ingenic does not specify any timing constraints for reset,
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* let's do a 1ms delay for fun */
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jz_writef(AIC_RGADW, ICRST(1));
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mdelay(1);
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jz_writef(AIC_RGADW, ICRST(0));
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/* Power-up and initial config sequence */
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static const uint8_t init_config[] = {
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JZCODEC_CR_VIC, 0x03, /* ensure codec is powered off */
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JZCODEC_CR_CK, 0x40, /* MCLK_DIV=1, SHUTDOWN_CLK=0, CRYSTAL=12Mhz */
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JZCODEC_AICR_DAC, 0x13, /* ADWL=0 (16bit word length)
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* SLAVE=0 (i2s master mode)
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* SB_DAC=1 (power down DAC)
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* AUDIOIF=3 (i2s mode) */
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JZCODEC_AICR_ADC, 0x13, /* ADWL=0 (16bit word length)
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* SB_ADC=1 (power down ADC)
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* AUDIOIF=3 (i2s mode)
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*/
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JZCODEC_CR_DAC, 0x91, /* DAC mute, power down */
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JZCODEC_CR_DAC2, 0x38, /* DAC power down */
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JZCODEC_CR_DMIC, 0x00, /* DMIC clock off */
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JZCODEC_CR_MIC1, 0x30, /* MIC1 power down */
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JZCODEC_CR_MIC2, 0x30, /* MIC2 power down */
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JZCODEC_CR_ADC, 0x90, /* ADC mute, power down */
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JZCODEC_ICR, 0x00, /* INT_FORM=0 (high level IRQ) */
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JZCODEC_IMR, 0xff, /* Mask all interrupts */
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JZCODEC_IMR2, 0xff,
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JZCODEC_IFR, 0xff, /* Clear all interrupt flags */
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JZCODEC_IFR2, 0xff,
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};
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for(size_t i = 0; i < ARRAYLEN(init_config); i += 2)
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x1000_icodec_write(init_config[i], init_config[i+1]);
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/* SB -> 0 (power up) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
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mdelay(250);
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/* Initial gain setting. Apparently we need to set one gain and
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* then set another after 10ms; afterward it can be changed freely. */
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static const uint8_t gain_regs[] = {
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JZCODEC_GCR_DACL,
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JZCODEC_GCR_DACR,
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JZCODEC_GCR_DACL2,
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JZCODEC_GCR_DACR2,
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JZCODEC_GCR_MIC1,
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JZCODEC_GCR_MIC2,
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JZCODEC_GCR_ADCL,
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JZCODEC_GCR_ADCR,
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};
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for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
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x1000_icodec_write(gain_regs[i], 0);
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mdelay(10);
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for(size_t i = 0; i < ARRAYLEN(gain_regs); ++i)
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x1000_icodec_write(gain_regs[i], 1);
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/* SB_SLEEP -> 0 (exit sleep/standby mode) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x00);
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mdelay(200);
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}
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void x1000_icodec_close(void)
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{
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/* SB_SLEEP -> 1 (enable sleep mode) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x02);
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/* SB -> 1 (power down) */
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x1000_icodec_write(JZCODEC_CR_VIC, 0x03);
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}
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/*
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* DAC configuration
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*/
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void x1000_icodec_dac_frequency(int fsel)
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{
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x1000_icodec_update(JZCODEC_FCR_DAC, 0x0f, fsel_to_hw[fsel]);
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}
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/*
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* ADC configuration
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*/
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void x1000_icodec_adc_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_AICR_ADC, 0x10, en ? 0x00 : 0x10);
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x1000_icodec_update(JZCODEC_CR_ADC, 0x10, en ? 0x00 : 0x10);
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}
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void x1000_icodec_adc_mute(bool muted)
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{
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x1000_icodec_update(JZCODEC_CR_ADC, 0x80, muted ? 0x80 : 0x00);
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}
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void x1000_icodec_adc_mic_sel(int sel)
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{
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x1000_icodec_update(JZCODEC_CR_ADC, 0x40,
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sel == JZCODEC_MIC_SEL_DIGITAL ? 0x40 : 0x00);
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}
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void x1000_icodec_adc_frequency(int fsel)
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{
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x1000_icodec_update(JZCODEC_FCR_ADC, 0x0f, fsel_to_hw[fsel]);
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}
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void x1000_icodec_adc_highpass_filter(bool en)
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{
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x1000_icodec_update(JZCODEC_FCR_ADC, 0x40, en ? 0x40 : 0x00);
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}
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void x1000_icodec_adc_gain(int gain_dB)
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{
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if(gain_dB < X1000_ICODEC_ADC_GAIN_MIN)
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gain_dB = X1000_ICODEC_ADC_GAIN_MIN;
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else if(gain_dB > X1000_ICODEC_ADC_GAIN_MAX)
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gain_dB = X1000_ICODEC_ADC_GAIN_MAX;
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/* bit 7 = use the same gain for both channels */
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x1000_icodec_write(JZCODEC_GCR_ADCL, 0x80 | gain_dB);
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}
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/*
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* MIC1 configuration
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*/
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void x1000_icodec_mic1_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, 0x10, en ? 0x00 : 0x10);
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}
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void x1000_icodec_mic1_bias_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, 0x20, en ? 0x00 : 0x20);
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}
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void x1000_icodec_mic1_configure(int settings)
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{
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x1000_icodec_update(JZCODEC_CR_MIC1, JZCODEC_MIC1_CONFIGURE_MASK,
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settings & JZCODEC_MIC1_CONFIGURE_MASK);
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}
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void x1000_icodec_mic1_gain(int gain_dB)
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{
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if(gain_dB < X1000_ICODEC_MIC_GAIN_MIN)
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gain_dB = X1000_ICODEC_MIC_GAIN_MIN;
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else if(gain_dB > X1000_ICODEC_MIC_GAIN_MAX)
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gain_dB = X1000_ICODEC_MIC_GAIN_MAX;
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x1000_icodec_write(JZCODEC_GCR_MIC1, gain_dB/X1000_ICODEC_MIC_GAIN_STEP);
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}
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/*
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* Mixer configuration
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*/
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void x1000_icodec_mixer_enable(bool en)
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{
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x1000_icodec_update(JZCODEC_CR_MIX, 0x80, en ? 0x80 : 0x00);
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}
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/*
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* Register access
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*/
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static int x1000_icodec_read_direct(int reg)
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{
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jz_writef(AIC_RGADW, ADDR(reg));
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return jz_readf(AIC_RGDATA, DATA);
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}
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static void x1000_icodec_write_direct(int reg, int value)
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{
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jz_writef(AIC_RGADW, ADDR(reg), DATA(value));
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jz_writef(AIC_RGADW, RGWR(1));
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while(jz_readf(AIC_RGADW, RGWR));
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}
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static void x1000_icodec_update_direct(int reg, int mask, int value)
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{
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int x = x1000_icodec_read_direct(reg) & ~mask;
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x |= value;
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x1000_icodec_write_direct(reg, x);
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}
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static int x1000_icodec_read_indirect(int c_reg, int index)
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{
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x1000_icodec_update_direct(c_reg, 0x7f, index & 0x3f);
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return x1000_icodec_read_direct(c_reg+1);
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}
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static void x1000_icodec_write_indirect(int c_reg, int index, int value)
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{
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/* NB: The X1000 programming manual says we should write the data
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* register first, but in fact the control register needs to be
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* written first (following Ingenic's Linux driver). */
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x1000_icodec_update_direct(c_reg, 0x7f, 0x40 | (index & 0x3f));
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x1000_icodec_write_direct(c_reg+1, value);
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}
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static void x1000_icodec_update_indirect(int c_reg, int index, int mask, int value)
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{
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int x = x1000_icodec_read_indirect(c_reg, index) & ~mask;
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x |= value;
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x1000_icodec_write_indirect(c_reg, index, x);
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}
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int x1000_icodec_read(int reg)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_read_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg));
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else
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return x1000_icodec_read_direct(reg);
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}
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void x1000_icodec_write(int reg, int value)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_write_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg), value);
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else
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return x1000_icodec_write_direct(reg, value);
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}
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void x1000_icodec_update(int reg, int mask, int value)
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{
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if(reg & JZCODEC_INDIRECT_BIT)
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return x1000_icodec_update_indirect(JZCODEC_INDIRECT_CREG(reg),
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JZCODEC_INDIRECT_INDEX(reg),
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mask, value);
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else
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return x1000_icodec_update_direct(reg, mask, value);
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}
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@ -192,6 +192,8 @@ struct sound_settings_info
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#include "tsc2100.h"
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#elif defined(HAVE_JZ4740_CODEC)
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#include "jz4740-codec.h"
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#elif defined(HAVE_X1000_ICODEC_PLAY)
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#include "x1000-codec.h"
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#elif defined(HAVE_AK4537)
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#include "ak4537.h"
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#elif defined(HAVE_AK4376)
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@ -237,6 +239,11 @@ struct sound_settings_info
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#include "erosqlinux_codec.h"
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#endif
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#if defined(HAVE_X1000_ICODEC_REC) && !defined(HAVE_X1000_ICODEC_PLAY)
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/* Targets may have an external DAC above, but use icodec for recording only */
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#include "x1000-codec.h"
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#endif
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/* convert caps into defines */
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#ifdef AUDIOHW_CAPS
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/* Tone controls */
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184
firmware/export/x1000-codec.h
Normal file
184
firmware/export/x1000-codec.h
Normal file
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@ -0,0 +1,184 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021-2022 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __X1000_CODEC_H__
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#define __X1000_CODEC_H__
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#include "config.h"
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#include <stdbool.h>
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/* Note: the internal X1000 codec supports playback and record, but devices
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* can employ an external codec for one and the internal codec for the other.
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* The caveat, in this case, is that only one codec can be used at a time
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* because the HW cannot mux playback/record independently.
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*
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* At present only recording is implemented, since all X1000 ports use an
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* external DAC for playback.
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*/
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#ifdef HAVE_X1000_ICODEC_PLAY
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# error "X1000 icodec playback not implemented"
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#endif
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#define X1000_ICODEC_ADC_GAIN_MIN 0
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#define X1000_ICODEC_ADC_GAIN_MAX 43
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#define X1000_ICODEC_ADC_GAIN_STEP 1
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#define X1000_ICODEC_MIC_GAIN_MIN 0
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#define X1000_ICODEC_MIC_GAIN_MAX 20
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#define X1000_ICODEC_MIC_GAIN_STEP 4
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#ifdef HAVE_X1000_ICODEC_REC
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AUDIOHW_SETTING(MIC_GAIN, "dB", 0, 1, 0, 63, 12)
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#endif
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#define JZCODEC_INDIRECT_CREG(r) ((r) & 0xff)
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#define JZCODEC_INDIRECT_INDEX(r) (((r) >> 8) & 0x7)
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#define JZCODEC_INDIRECT_BIT 0x800
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#define JZCODEC_INDIRECT(c, i) (JZCODEC_INDIRECT_BIT | ((i) << 8) | (c))
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/* Codec registers from Ingenic's kernel sources. The datasheet is badly
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* screwed up and the addresses listed cannot be trusted. */
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enum {
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JZCODEC_SR = 0,
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JZCODEC_SR2,
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JZCODEC_SIGR,
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JZCODEC_SIGR2,
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JZCODEC_SIGR3,
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JZCODEC_SIGR5,
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JZCODEC_SIGR7,
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JZCODEC_MR,
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JZCODEC_AICR_DAC,
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JZCODEC_AICR_ADC,
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JZCODEC_CR_DMIC,
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JZCODEC_CR_MIC1,
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JZCODEC_CR_MIC2,
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JZCODEC_CR_DAC,
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JZCODEC_CR_DAC2,
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JZCODEC_CR_ADC,
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JZCODEC_CR_MIX,
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JZCODEC_DR_MIX,
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JZCODEC_CR_VIC,
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JZCODEC_CR_CK,
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JZCODEC_FCR_DAC,
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JZCODEC_SFCCR_DAC,
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JZCODEC_SFFCR_DAC,
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JZCODEC_FCR_ADC,
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JZCODEC_CR_TIMER_MSB,
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JZCODEC_CR_TIMER_LSB,
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JZCODEC_ICR,
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JZCODEC_IMR,
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JZCODEC_IFR,
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JZCODEC_IMR2,
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JZCODEC_IFR2,
|
||||
JZCODEC_GCR_DACL,
|
||||
JZCODEC_GCR_DACR,
|
||||
JZCODEC_GCR_DACL2,
|
||||
JZCODEC_GCR_DACR2,
|
||||
JZCODEC_GCR_MIC1,
|
||||
JZCODEC_GCR_MIC2,
|
||||
JZCODEC_GCR_ADCL,
|
||||
JZCODEC_GCR_ADCR,
|
||||
JZCODEC_GCR_MIXDACL,
|
||||
JZCODEC_GCR_MIXDACR,
|
||||
JZCODEC_GCR_MIXADCL,
|
||||
JZCODEC_GCR_MIXADCR,
|
||||
JZCODEC_CR_DAC_AGC,
|
||||
JZCODEC_DR_DAC_AGC,
|
||||
JZCODEC_CR_DAC2_AGC,
|
||||
JZCODEC_DR_DAC2_AGC,
|
||||
JZCODEC_CR_ADC_AGC,
|
||||
JZCODEC_DR_ADC_AGC,
|
||||
JZCODEC_SR_ADC_AGCDGL,
|
||||
JZCODEC_SR_ADC_AGCDGR,
|
||||
JZCODEC_SR_ADC_AGCAGL,
|
||||
JZCODEC_SR_ADC_AGCAGR,
|
||||
JZCODEC_CR_TR,
|
||||
JZCODEC_DR_TR,
|
||||
JZCODEC_SR_TR1,
|
||||
JZCODEC_SR_TR2,
|
||||
JZCODEC_SR_TR_SRCDAC,
|
||||
|
||||
JZCODEC_MIX0 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 0),
|
||||
JZCODEC_MIX1 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 1),
|
||||
JZCODEC_MIX2 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 2),
|
||||
JZCODEC_MIX3 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 3),
|
||||
JZCODEC_MIX4 = JZCODEC_INDIRECT(JZCODEC_CR_MIX, 4),
|
||||
|
||||
JZCODEC_DAC_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 0),
|
||||
JZCODEC_DAC_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 1),
|
||||
JZCODEC_DAC_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 2),
|
||||
JZCODEC_DAC_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_DAC_AGC, 3),
|
||||
|
||||
JZCODEC_DAC2_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 0),
|
||||
JZCODEC_DAC2_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 1),
|
||||
JZCODEC_DAC2_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 2),
|
||||
JZCODEC_DAC2_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_DAC2_AGC, 3),
|
||||
|
||||
JZCODEC_ADC_AGC0 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 0),
|
||||
JZCODEC_ADC_AGC1 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 1),
|
||||
JZCODEC_ADC_AGC2 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 2),
|
||||
JZCODEC_ADC_AGC3 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 3),
|
||||
JZCODEC_ADC_AGC4 = JZCODEC_INDIRECT(JZCODEC_CR_ADC_AGC, 4),
|
||||
};
|
||||
|
||||
/* for use with x1000_icodec_mic1_configure() */
|
||||
enum {
|
||||
JZCODEC_MIC1_SINGLE_ENDED = (0 << 6),
|
||||
JZCODEC_MIC1_DIFFERENTIAL = (1 << 6),
|
||||
|
||||
JZCODEC_MIC1_BIAS_2_08V = (0 << 3),
|
||||
JZCODEC_MIC1_BIAS_1_66V = (1 << 3),
|
||||
|
||||
JZCODEC_MIC1_CONFIGURE_MASK = (1 << 6) | (1 << 3),
|
||||
};
|
||||
|
||||
/* for use with x1000_icodec_adc_mic_sel() */
|
||||
enum {
|
||||
JZCODEC_MIC_SEL_ANALOG,
|
||||
JZCODEC_MIC_SEL_DIGITAL,
|
||||
};
|
||||
|
||||
extern void x1000_icodec_open(void);
|
||||
extern void x1000_icodec_close(void);
|
||||
|
||||
extern void x1000_icodec_dac_frequency(int fsel);
|
||||
|
||||
extern void x1000_icodec_adc_enable(bool en);
|
||||
extern void x1000_icodec_adc_mute(bool muted);
|
||||
extern void x1000_icodec_adc_mic_sel(int sel);
|
||||
extern void x1000_icodec_adc_frequency(int fsel);
|
||||
extern void x1000_icodec_adc_highpass_filter(bool en);
|
||||
extern void x1000_icodec_adc_gain(int gain_dB);
|
||||
|
||||
extern void x1000_icodec_mic1_enable(bool en);
|
||||
extern void x1000_icodec_mic1_bias_enable(bool en);
|
||||
extern void x1000_icodec_mic1_configure(int settings);
|
||||
extern void x1000_icodec_mic1_gain(int gain_dB);
|
||||
|
||||
extern void x1000_icodec_mixer_enable(bool en);
|
||||
|
||||
extern int x1000_icodec_read(int reg);
|
||||
extern void x1000_icodec_write(int reg, int value);
|
||||
extern void x1000_icodec_update(int reg, int mask, int value);
|
||||
|
||||
#endif /* __X1000_CODEC_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue