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https://github.com/Rockbox/rockbox.git
synced 2025-12-09 13:15:18 -05:00
Finally a click, pop and other distortion free PCM driver for that fishy bufferless S5L870x I2S controller.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23324 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
92737a3877
commit
16a956c4f3
2 changed files with 106 additions and 51 deletions
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@ -28,7 +28,6 @@
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#include "audiohw.h"
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#include "pcm.h"
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#include "pcm_sampr.h"
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#include "dma-target.h"
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#include "mmu-target.h"
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/* Driver for the IIS/PCM part of the s5l8700 using DMA
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@ -41,8 +40,10 @@
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- recording is not implemented
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*/
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static void dma_callback(void);
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static volatile int locked = 0;
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static volatile int locked = 0;
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size_t nextsize;
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int dmamode;
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unsigned char* dblbuf;
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/* table of recommended PLL/MCLK dividers for mode 256Fs from the datasheet */
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static const struct div_entry {
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@ -54,10 +55,9 @@ static const struct div_entry {
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[HW_FREQ_44] = { 2, 41, 3, 4},
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[HW_FREQ_88] = { 2, 41, 2, 4},
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#if 0 /* disabled because the codec driver does not support it (yet) */
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[HW_FREQ_8 ] = { 2, 12, 3, 9}
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[HW_FREQ_8 ] = { 2, 12, 3, 9},
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[HW_FREQ_16] = { 2, 12, 2, 9},
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[HW_FREQ_32] = { 2, 12, 1, 9},
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[HW_FREQ_12] = { 2, 12, 4, 3},
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[HW_FREQ_24] = { 2, 12, 3, 3},
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[HW_FREQ_48] = { 2, 12, 2, 3},
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@ -69,10 +69,9 @@ static const struct div_entry {
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[HW_FREQ_44] = { 37, 151, 1, 9},
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[HW_FREQ_88] = { 50, 98, 1, 4},
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#if 0 /* disabled because the codec driver does not support it (yet) */
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[HW_FREQ_8 ] = { 28, 192, 3, 12}
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[HW_FREQ_8 ] = { 28, 192, 3, 12},
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[HW_FREQ_16] = { 28, 192, 3, 6},
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[HW_FREQ_32] = { 28, 192, 2, 6},
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[HW_FREQ_12] = { 28, 192, 3, 8},
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[HW_FREQ_24] = { 28, 192, 2, 8},
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[HW_FREQ_48] = { 28, 192, 2, 4},
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@ -97,50 +96,109 @@ void pcm_play_unlock(void)
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}
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}
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static void play_next(void *addr, size_t size)
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static void* dma_callback(void) ICODE_ATTR;
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static void* dma_callback(void)
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{
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/* setup DMA */
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dma_setup_channel(DMA_IISOUT_CHANNEL, DMA_IISOUT_SELECT, DMA_MEM_TO_IO,
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DMA_IISOUT_DSIZE, DMA_IISOUT_BLEN, addr, size / 2,
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dma_callback);
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/* DMA channel on */
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// clean_dcache();
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dma_enable_channel(DMA_IISOUT_CHANNEL);
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}
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static void dma_callback(void)
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{
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unsigned char *dma_start_addr;
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size_t dma_size;
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register pcm_more_callback_type get_more = pcm_callback_for_more;
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if (get_more) {
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get_more(&dma_start_addr, &dma_size);
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if (dma_size == 0) {
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pcm_play_dma_stop();
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pcm_play_dma_stopped_callback();
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if (dmamode)
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{
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unsigned char *dma_start_addr;
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register pcm_more_callback_type get_more = pcm_callback_for_more;
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if (get_more)
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{
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get_more(&dma_start_addr, &nextsize);
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if (nextsize > 4096)
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{
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nextsize = nextsize - 2048;
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dblbuf = dma_start_addr + nextsize;
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dmamode = 0;
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}
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nextsize = (nextsize >> 1) - 1;
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clean_dcache();
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return dma_start_addr;
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}
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else {
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play_next(dma_start_addr, dma_size);
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else
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{
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nextsize = -1;
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return 0;
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}
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}
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else
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{
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dmamode = 1;
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nextsize = 1023;
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return dblbuf;
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}
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}
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)) ICODE_ATTR;
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void fiq_handler(void)
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{
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asm volatile (
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"cmn r11, #1 \n"
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"strne r10, [r8] \n" /* DMABASE0 */
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"strne r11, [r8,#0x08] \n" /* DMATCNT0 */
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"strne r9, [r8,#0x14] \n" /* DMACOM0 */
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"moveq r10, #5 \n" /* STOP DMA */
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"streq r10, [r8,#0x14] \n" /* DMACOM0 */
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"mov r10, #7 \n" /* CLEAR IRQ */
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"str r10, [r8,#0x14] \n" /* DMACOM0 */
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"mov r11, #0x39C00000 \n" /* SRCPND */
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"mov r10, #0x00000400 \n" /* INT_DMA */
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"str r10, [r11] \n" /* ACK FIQ */
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"stmfd sp!, {r0-r3,lr} \n"
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"ldreq r0, =pcm_play_dma_stopped_callback \n"
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"ldrne r0, =dma_callback \n"
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"mov lr, pc \n"
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"bx r0 \n"
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"mov r10, r0 \n"
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"ldmfd sp!, {r0-r3,lr} \n"
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"ldr r11, =nextsize \n"
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"ldr r11, [r11] \n"
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"subs pc, lr, #4 \n"
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);
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}
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void bootstrap_fiq(const void* addr, size_t tcnt) __attribute__((naked,noinline));
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void bootstrap_fiq(const void* addr, size_t tcnt)
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{
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(void)addr;
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(void)tcnt;
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asm volatile (
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"add r2, lr, #4 \n"
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"mrs r3, cpsr \n"
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"msr cpsr_c, #0xD1 \n" /* FIQ mode, IRQ/FIQ disabled */
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"mov r8, #0x38400000 \n" /* DMA BASE */
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"mov r9, #4 \n" /* START DMA */
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"mov r10, r0 \n"
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"mov r11, r1 \n"
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"mov r0, #0 \n"
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"ldr r12, =fiq_handler \n"
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"ldr sp, =_fiqstackend \n"
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"mov lr, r2 \n"
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"msr spsr_all, r3 \n"
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"bx r12 \n"
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);
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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/* S1: DMA channel 0 set */
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dma_setup_channel(DMA_IISOUT_CHANNEL, DMA_IISOUT_SELECT, DMA_MEM_TO_IO,
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DMA_IISOUT_DSIZE, DMA_IISOUT_BLEN, (void *)addr, size / 2,
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dma_callback);
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DMACON0 = (0 << 30) | /* DEVSEL */
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(1 << 29) | /* DIR */
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(0 << 24) | /* SCHCNT */
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(1 << 22) | /* DSIZE */
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(0 << 19) | /* BLEN */
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(0 << 18) | /* RELOAD */
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(0 << 17) | /* HCOMINT */
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(1 << 16) | /* WCOMINT */
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(0 << 0); /* OFFSET */
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#ifdef IPOD_NANO2G
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PCON5 = (PCON5 & ~(0xFFFF0000)) | 0x77720000;
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PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
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I2STXCON = (1 << 20) | /* undocumented */
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(DMA_IISOUT_BLEN << 16) | /* burst length */
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(0 << 16) | /* burst length */
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(0 << 15) | /* 0 = falling edge */
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(0 << 13) | /* 0 = basic I2S format */
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(0 << 12) | /* 0 = MSB first */
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@ -163,8 +221,10 @@ void pcm_play_dma_start(const void *addr, size_t size)
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#endif
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/* S3: DMA channel 0 on */
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// clean_dcache();
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dma_enable_channel(DMA_IISOUT_CHANNEL);
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clean_dcache();
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dmamode = 0;
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dblbuf = (unsigned char*)addr + size - 2048;
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bootstrap_fiq(addr, (size >> 1) - 1025);
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/* S4: IIS Tx clock on */
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I2SCLKCON = (1 << 0); /* 1 = power on */
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@ -179,7 +239,7 @@ void pcm_play_dma_start(const void *addr, size_t size)
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void pcm_play_dma_stop(void)
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{
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/* DMA channel off */
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dma_disable_channel(DMA_IISOUT_CHANNEL);
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DMACOM0 = 5;
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/* TODO Some time wait */
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/* LRCK half cycle wait */
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@ -214,6 +274,10 @@ void pcm_play_dma_init(void)
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/* enable clock to the IIS module */
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PWRCON &= ~(1 << 6);
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/* Enable the DMA FIQ */
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INTMOD |= (1 << 10);
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INTMSK |= (1 << 10);
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audiohw_preinit();
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}
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@ -248,20 +312,20 @@ void pcm_dma_apply_settings(void)
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/* configure MCLK */
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CLKCON = (CLKCON & ~(0xFF)) |
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(0 << 7) | /* MCLK_MASK */
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(2 << 5) | /* MCLK_SEL = PLL2 */
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(2 << 5) | /* MCLK_SEL = PLL1 */
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(1 << 4) | /* MCLK_DIV_ON */
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(div.cdiv - 1); /* MCLK_DIV_VAL */
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return DMACTCNT0 * 2;
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return (DMACTCNT0 + 1) << 1;
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}
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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*count = DMACTCNT0 >> 1;
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return (void *)((DMACADDR0 + 2) & ~3);
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return (void *)(((DMACADDR0 + 2) & ~3) | 0x40000000);
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}
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#ifdef HAVE_PCM_DMA_ADDRESS
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@ -30,7 +30,6 @@
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(EXT0);
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default_interrupt(EXT1);
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@ -142,14 +141,6 @@ void irq_handler(void)
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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void system_init(void)
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{
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}
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