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regtools: update v2 specification, library and tools
A v2 register description file can now include register variants and instances addresses can now be a list (previously it could only be a stride or a formula). Update the library to deal with that. The convert option of swiss_knife was updated and one incompatible change was introduce: if a v1 device has several addresses, those are converted to a single v2 instance with list (instead of several single instances). This should have been the behaviour from the start. Swiss_knife can now also convert regdumps, in which case it needs to be given both the dump and register description file. Also introduce two register descriptions files (vsoc1000 and vsoc2000) which give more complicated examples of v2 register description files. Change-Id: Id9415b8363269ffaf9216abfc6dd1bd1adbfcf8d
This commit is contained in:
Amaury Pouly
parent
16c915ec18
commit
0f701a64be
9 changed files with 1491 additions and 211 deletions
396
utils/regtools/desc/regs-vsoc2000.xml
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396
utils/regtools/desc/regs-vsoc2000.xml
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@ -0,0 +1,396 @@
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<?xml version="1.0"?>
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<soc version="2">
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<name>vsoc2000</name>
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<title>Virtual SOC 2000</title>
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<desc>Virtual SoC 2000 is a nice chip. Its quad-core architecture with trustzone makes it super powerful.</desc>
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<author>Amaury Pouly</author>
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<isa>ARM</isa>
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<version>0.5</version>
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<node>
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<name>int</name>
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<title>Interrupt Collector</title>
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<desc>The interrupt collector controls the routing of the interrupts to the processors. It has 32 interrupts sources, which can be routed as FIQ or IRQ to the either processor.</desc>
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<instance>
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<name>ICOLL</name>
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<title>Interrupt collector</title>
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<address>0x80000000</address>
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</instance>
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<node>
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<name>ctrl</name>
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<title>Control register</title>
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<instance>
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<name>CTRL</name>
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<address>0x0</address>
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</instance>
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<register>
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<width>8</width>
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<field>
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<name>CLKGATE</name>
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<desc>Clock gating control. This bit can be protected by TZ lock.</desc>
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<position>7</position>
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</field>
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<field>
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<name>SFTRST</name>
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<desc>Soft reset, the bit will automatically reset to 0 when reset is completed. This bit can be protected by TZ lock.</desc>
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<position>6</position>
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</field>
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<field>
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<name>TZ_LOCK</name>
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<desc>Trust Zone lock</desc>
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<position>5</position>
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<enum>
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<name>UNLOCKED</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>LOCKED</name>
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<desc>When the interrupt collector is locked, only a secured processor can modify protected fields.</desc>
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<value>0x1</value>
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</enum>
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</field>
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<variant>
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<type>set</type>
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<offset>4</offset>
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</variant>
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<variant>
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<type>clr</type>
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<offset>8</offset>
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</variant>
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</register>
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</node>
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<node>
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<name>status</name>
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<title>Interrupt status register</title>
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<instance>
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<name>STATUS</name>
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<address>0x10</address>
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</instance>
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<register>
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<field>
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<name>STATUS</name>
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<desc>Bit is set to 1 is the interrupt is pending, write a 1 to the clear variant to clear it. Secured interrupts can only be cleared or polled by secured processors (non-secure will always read 0 for those).</desc>
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<position>0</position>
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<width>32</width>
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</field>
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<variant>
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<type>clr</type>
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<offset>8</offset>
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</variant>
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</register>
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</node>
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<node>
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<name>enable</name>
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<title>Interrupt enable register</title>
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<instance>
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<name>ENABLE</name>
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<range>
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<first>0</first>
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<count>32</count>
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<base>0x20</base>
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<stride>0x10</stride>
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</range>
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</instance>
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<register>
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<width>16</width>
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<desc>This register controls the routing of the interrupt</desc>
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<field>
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<name>CPU3_PRIO</name>
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<desc>Interrupt priority</desc>
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<position>14</position>
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<width>2</width>
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<enum>
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<name>MASKED</name>
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<desc>Interrupt is masked</desc>
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<value>0x0</value>
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</enum>
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<enum>
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<name>LOW</name>
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<value>0x1</value>
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</enum>
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<enum>
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<name>HIGH</name>
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<value>0x2</value>
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</enum>
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<enum>
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<name>NMI</name>
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<desc>Interrupt is non maskable</desc>
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<value>0x3</value>
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</enum>
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</field>
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<field>
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<name>CPU3_TYPE</name>
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<desc>Interrupt type</desc>
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<position>13</position>
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<enum>
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<name>IRQ</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>FIQ</name>
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<value>0x1</value>
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</enum>
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</field>
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<field>
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<name>CPU3_TZ</name>
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<desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
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<position>12</position>
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</field>
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<field>
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<name>CPU2_PRIO</name>
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<position>10</position>
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<width>2</width>
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<enum>
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<name>MASKED</name>
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<desc>Interrupt is masked</desc>
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<value>0x0</value>
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</enum>
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<enum>
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<name>LOW</name>
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<value>0x1</value>
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</enum>
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<enum>
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<name>HIGH</name>
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<value>0x2</value>
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</enum>
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<enum>
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<name>NMI</name>
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<desc>Interrupt is non maskable</desc>
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<value>0x3</value>
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</enum>
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</field>
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<field>
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<name>CPU2_TYPE</name>
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<desc>Interrupt type</desc>
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<position>9</position>
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<enum>
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<name>IRQ</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>FIQ</name>
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<value>0x1</value>
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</enum>
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</field>
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<field>
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<name>CPU2_TZ</name>
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<desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
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<position>8</position>
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</field>
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<field>
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<name>CPU1_PRIO</name>
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<desc>Interrupt priority</desc>
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<position>6</position>
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<width>2</width>
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<enum>
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<name>MASKED</name>
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<desc>Interrupt is masked</desc>
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<value>0x0</value>
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</enum>
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<enum>
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<name>LOW</name>
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<value>0x1</value>
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</enum>
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<enum>
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<name>HIGH</name>
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<value>0x2</value>
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</enum>
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<enum>
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<name>NMI</name>
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<desc>Interrupt is non maskable</desc>
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<value>0x3</value>
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</enum>
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</field>
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<field>
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<name>CPU1_TYPE</name>
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<desc>Interrupt type</desc>
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<position>5</position>
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<enum>
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<name>IRQ</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>FIQ</name>
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<value>0x1</value>
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</enum>
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</field>
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<field>
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<name>CPU1_TZ</name>
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<desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
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<position>4</position>
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</field>
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<field>
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<name>CPU0_PRIO</name>
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<desc>Interrupt priority</desc>
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<position>2</position>
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<width>2</width>
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<enum>
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<name>MASKED</name>
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<desc>Interrupt will never be sent to the CPU</desc>
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<value>0x0</value>
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</enum>
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<enum>
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<name>LOW</name>
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<value>0x1</value>
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</enum>
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<enum>
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<name>HIGH</name>
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<value>0x2</value>
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</enum>
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<enum>
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<name>NMI</name>
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<desc>Interrupt is non maskable</desc>
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<value>0x3</value>
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</enum>
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</field>
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<field>
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<name>CPU0_TYPE</name>
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<desc>Interrupt type</desc>
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<position>1</position>
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<enum>
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<name>IRQ</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>FIQ</name>
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<value>0x1</value>
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</enum>
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</field>
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<field>
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<name>CPU0_TZ</name>
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<desc>Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts.</desc>
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<position>0</position>
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</field>
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<variant>
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<type>set</type>
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<offset>4</offset>
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</variant>
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<variant>
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<type>clr</type>
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<offset>8</offset>
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</variant>
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</register>
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</node>
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</node>
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<node>
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<name>gpio</name>
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<title>GPIO controller</title>
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<desc>A GPIO controller manages several ports.</desc>
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<instance>
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<name>CPU_GPIO</name>
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<title>CPU GPIO controllers 1 through 7</title>
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<range>
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<first>1</first>
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<count>8</count>
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<formula variable="n">0x80001000+(n-1)*0x1000</formula>
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</range>
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</instance>
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<node>
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<name>port</name>
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<title>GPIO port</title>
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<instance>
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<name>PORT</name>
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<range>
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<first>0</first>
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<count>2</count>
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<base>0x0</base>
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<stride>0x100</stride>
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</range>
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</instance>
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<node>
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<name>input</name>
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<title>Input register</title>
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<instance>
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<name>IN</name>
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<address>0x0</address>
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</instance>
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<register>
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<width>8</width>
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<field>
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<name>VALUE</name>
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<position>0</position>
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<width>8</width>
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</field>
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</register>
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</node>
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<node>
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<name>output_enable</name>
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<title>Output enable register</title>
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<instance>
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<name>OE</name>
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<address>0x10</address>
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</instance>
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<register>
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<width>8</width>
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<field>
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<name>ENABLE</name>
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<position>0</position>
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<width>8</width>
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</field>
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<variant>
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<type>set</type>
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<offset>4</offset>
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</variant>
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<variant>
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<type>clr</type>
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<offset>8</offset>
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</variant>
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<variant>
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<type>mask</type>
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<offset>12</offset>
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</variant>
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</register>
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</node>
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</node>
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</node>
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<node>
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<name>tz</name>
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<title>Trust Zone</title>
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<instance>
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<name>TZ</name>
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<address>0xa0000000</address>
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</instance>
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<node>
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<name>ctrl</name>
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<title>Control Register</title>
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<instance>
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<name>CTRL</name>
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<address>0x0</address>
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</instance>
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<register>
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<width>8</width>
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<field>
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<name>SCRATCH</name>
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<desc>TZ protected scratch value</desc>
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<position>4</position>
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<width>4</width>
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</field>
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<field>
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<name>DISABLE</name>
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<desc>One bit per CPU: set to 1 to prevent the processor from being able to enter TZ mode. Can only be set by a secured processor. By default all processors can enter TZ mode.</desc>
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<position>0</position>
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<width>4</width>
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</field>
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</register>
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</node>
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<node>
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<name>debug</name>
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<title>Debug register</title>
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<instance>
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<name>DEBUG</name>
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<title>Debug register</title>
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<desc>Don't touch it!</desc>
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<range>
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<first>42</first>
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<address>0x50</address>
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<address>0x60</address>
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<address>0x90</address>
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<address>0x110</address>
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<address>0x130</address>
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</range>
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</instance>
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<register>
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<width>8</width>
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</register>
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</node>
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</node>
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</soc>
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