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mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
This commit is contained in:
Solomon Peachy
parent
1ae8213a64
commit
0cb162a76b
16 changed files with 188 additions and 129 deletions
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@ -5,9 +5,9 @@
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Maurus Cuelenaere
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* Copyright (C) 2015 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -25,8 +25,16 @@
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#include "system.h"
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#include "mmu-mips.h"
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#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
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/* XBurst core has 32 JTLB entries */
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#define NR_TLB_ENTRIES 32
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#else
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#error please define NR_TLB_ENTRIES
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#endif
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#define BARRIER \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" nop \n" \
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" nop \n" \
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@ -34,7 +42,7 @@
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n");
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" .set pop \n");
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#define DEFAULT_PAGE_SHIFT PL_4K
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#define DEFAULT_PAGE_MASK PM_4K
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@ -43,6 +51,7 @@
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#define VPN2_SHIFT S_EntryHiVPN2
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#define PFN_SHIFT S_EntryLoPFN
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#define PFN_MASK 0xffffff
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static void local_flush_tlb_all(void)
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{
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unsigned long old_ctx;
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@ -55,10 +64,11 @@ static void local_flush_tlb_all(void)
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write_c0_entrylo1(0);
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BARRIER;
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/* Blast 'em all away. */
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for(entry = 0; entry < 32; entry++)
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/* blast all entries except the wired one */
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for(entry = read_c0_wired(); entry < NR_TLB_ENTRIES; entry++)
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{
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/* Make sure all entries differ. */
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/* Make sure all entries differ and are in unmapped space, making them
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* impossible to match */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry, DEFAULT_PAGE_SHIFT));
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write_c0_index(entry);
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BARRIER;
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@ -119,84 +129,133 @@ void mmu_init(void)
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write_c0_framemask(0);
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local_flush_tlb_all();
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/*
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map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC);
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map_address(0x80004000, 0x80004000, MEMORYSIZE * 0x100000, K_CacheAttrC);
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*/
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}
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#define SYNC_WB() __asm__ __volatile__ ("sync")
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/* Target specific operations:
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* - invalidate BTB (Branch Table Buffer)
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* - sync barrier after cache operations */
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#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
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#define INVALIDATE_BTB() \
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do { \
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unsigned long tmp; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips32 \n" \
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" mfc0 %0, $16, 7 \n" \
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" nop \n" \
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" ori %0, 2 \n" \
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" mtc0 %0, $16, 7 \n" \
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" nop \n" \
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" .set pop \n" \
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: "=&r"(tmp)); \
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} while (0)
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#define cache_op(base,op) \
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__asm__ __volatile__(" \
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.set noreorder; \
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.set mips3; \
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cache %1, (%0); \
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.set mips0; \
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.set reorder" \
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: \
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: "r" (base), \
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"i" (op));
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#define SYNC_WB() __asm__ __volatile__ ("sync":::"memory")
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#else /* !JZ4732 */
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#define INVALIDATE_BTB() do { } while(0)
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#define SYNC_WB() do { } while(0)
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#endif /* CONFIG_CPU */
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void __icache_invalidate_all(void)
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#define __CACHE_OP(op, addr) \
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__asm__ __volatile__( \
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" .set push\n\t \n" \
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" .set noreorder \n" \
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" .set mips32\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "m"(*(unsigned char *)(addr)))
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/* rockbox cache api */
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/* Writeback whole D-cache
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* Alias to commit_discard_dcache() as there is no index type
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* variant of writeback-only operation
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*/
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void commit_dcache(void) __attribute__((alias("commit_discard_dcache")));
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/* Writeback whole D-cache and invalidate D-cache lines */
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void commit_discard_dcache(void)
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{
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unsigned long start;
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unsigned long end;
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unsigned int i;
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/* Use index type operation and iterate whole cache */
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for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
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__CACHE_OP(DCIndexWBInv, i);
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start = A_K0BASE;
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end = start + CACHE_SIZE;
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while(start < end)
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{
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cache_op(start,ICIndexInv);
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start += CACHE_LINE_SIZE;
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}
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SYNC_WB();
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}
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void __dcache_invalidate_all(void)
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/* Writeback lines of D-cache corresponding to address range and
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* invalidate those D-cache lines
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*/
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void commit_discard_dcache_range(const void *base, unsigned int size)
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{
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unsigned long start;
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unsigned long end;
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char *s;
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for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
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__CACHE_OP(DCHitWBInv, s);
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start = A_K0BASE;
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end = start + CACHE_SIZE;
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while (start < end)
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{
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cache_op(start,DCIndexWBInv);
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start += CACHE_LINE_SIZE;
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}
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SYNC_WB();
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}
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void __idcache_invalidate_all(void)
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/* Writeback lines of D-cache corresponding to address range
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*/
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void commit_dcache_range(const void *base, unsigned int size)
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{
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__dcache_invalidate_all();
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__icache_invalidate_all();
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}
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char *s;
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void __dcache_writeback_all(void)
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{
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__dcache_invalidate_all();
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}
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for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
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__CACHE_OP(DCHitWB, s);
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void dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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if (size >= CACHE_SIZE*2) {
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__dcache_writeback_all();
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}
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else {
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unsigned long dc_lsize = CACHE_LINE_SIZE;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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while (1) {
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cache_op(a,DCHitWBInv);
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if (a == end)
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break;
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a += dc_lsize;
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}
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}
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SYNC_WB();
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}
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/* Invalidate D-cache lines corresponding to address range
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* WITHOUT writeback
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*/
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void discard_dcache_range(const void *base, unsigned int size)
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{
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char *s;
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if (((int)base & CACHEALIGN_SIZE - 1) ||
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(((int)base + size) & CACHEALIGN_SIZE - 1)) {
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/* Overlapping sections, so we need to write back instead */
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commit_discard_dcache_range(base, size);
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return;
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};
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for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
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__CACHE_OP(DCHitInv, s);
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SYNC_WB();
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}
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/* Invalidate whole I-cache */
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static void discard_icache(void)
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{
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unsigned int i;
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asm volatile (".set push \n"
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".set noreorder \n"
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".set mips32 \n"
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"mtc0 $0, $28 \n" /* TagLo */
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"mtc0 $0, $29 \n" /* TagHi */
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".set pop \n"
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);
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/* Use index type operation and iterate whole cache */
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for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
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__CACHE_OP(ICIndexStTag, i);
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INVALIDATE_BTB();
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}
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/* Invalidate the entire I-cache
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* and writeback + invalidate the entire D-cache
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*/
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void commit_discard_idcache(void)
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{
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commit_discard_dcache();
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discard_icache();
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}
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