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mips: Heavily rework DMA & caching code

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Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
This commit is contained in:
Solomon Peachy 2020-08-28 21:45:58 -04:00
parent 1ae8213a64
commit 0cb162a76b
16 changed files with 188 additions and 129 deletions
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3
firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c
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@ -69,6 +69,8 @@ static inline void set_dma(const void *addr, size_t size)
int burst_size;
logf("%x %d %x", (unsigned int)addr, size, REG_AIC_SR);
commit_discard_dcache_range(addr, size);
if(size % 16)
{
if(size % 4)
@ -88,7 +90,6 @@ static inline void set_dma(const void *addr, size_t size)
burst_size = DMAC_DCMD_DS_16BYTE;
}
__dcache_writeback_all();
REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES;
REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr);
REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR);