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https://github.com/Rockbox/rockbox.git
synced 2025-12-08 20:55:17 -05:00
jz4760: SD driver enhancements:
* Check to see if clock is [not] running prior to [en|dis]abling it * Stop clock _prior_ to resetting controller * Stop clock after transaction is completed, not before initiating it * Use controller's low power mode (disables clocks when idle) * Fix, and enable, interrupt-driven DMA transfers * Fixes for full interrupt-driven operation (WIP, still broken) Change-Id: I723ffa6450fc85f97898c8a8b3e538ae31c4858e
This commit is contained in:
Solomon Peachy
parent
1b31101fdd
commit
0aa2197d93
1 changed files with 91 additions and 42 deletions
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@ -29,10 +29,12 @@
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#include "logf.h"
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#include "storage.h"
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#include "string.h"
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#include "panic.h"
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#define SD_INTERRUPT 0
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#define SD_INTERRUPT 0 // COMPLETELY BROKEN!
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#define SD_DMA_ENABLE 1
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#define SD_DMA_INTERRUPT 0
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#define SD_DMA_INTERRUPT 1 // HANGS RANDOMLY!
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#define SD_AUTO_CLOCK 1
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#if NUM_DRIVES > 2
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#error "JZ4760 SD driver supports NUM_DRIVES <= 2 only"
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@ -267,6 +269,14 @@ static inline int jz_sd_stop_clock(const int drive)
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register int timeout = 1000;
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//DEBUG("stop MMC clock");
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#if SD_AUTO_CLOCK
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REG_MSC_LPM(drive) = 0; /* disable auto clock stop */
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#endif
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/* only stop if necessary */
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if (!(REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_CLK_EN))
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return SD_NO_ERROR;
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REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_STOP;
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while (timeout && (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_CLK_EN))
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@ -279,6 +289,7 @@ static inline int jz_sd_stop_clock(const int drive)
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}
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udelay(1);
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}
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//DEBUG("clock off time is %d microsec", timeout);
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return SD_NO_ERROR;
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}
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@ -286,7 +297,11 @@ static inline int jz_sd_stop_clock(const int drive)
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/* Start the MMC clock and operation */
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static inline int jz_sd_start_clock(const int drive)
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{
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REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
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int reg = MSC_STRPCL_START_OP;
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#if !SD_AUTO_CLOCK
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reg |= (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_CLK_EN) ? 0 : MSC_STRPCL_CLOCK_CONTROL_START;
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#endif
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REG_MSC_STRPCL(MSC_CHN(drive)) = reg;
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return SD_NO_ERROR;
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}
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@ -588,91 +603,88 @@ void DMA_CALLBACK(DMA_SD_RX_CHANNEL0)(void)
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{
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_AR)
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{
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logf("SD RX DMA address error");
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_AR;
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panicf("SD RX DMA address error");
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}
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_HLT)
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{
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logf("SD RX DMA halt");
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_HLT;
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panicf("SD RX DMA halt");
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}
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_TT)
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{
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_TT;
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//sd_rx_dma_callback();
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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void DMA_CALLBACK(DMA_SD_RX_CHANNEL1)(void)
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{
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_AR)
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{
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logf("SD RX DMA address error");
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_AR;
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panicf("SD RX DMA address error");
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}
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_HLT)
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{
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logf("SD RX DMA halt");
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_HLT;
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panicf("SD RX DMA halt");
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}
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if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_TT)
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{
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_TT;
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//sd_rx_dma_callback();
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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void DMA_CALLBACK(DMA_SD_TX_CHANNEL0)(void)
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{
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_AR)
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{
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logf("SD TX DMA address error: %x, %x, %x", var1, var2, var3);
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_AR;
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panicf("SD TX DMA address error");
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}
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_HLT)
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{
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logf("SD TX DMA halt");
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_HLT;
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panicf("SD TX DMA halt");
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}
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) & DMAC_DCCSR_TT)
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{
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_1)) &= ~DMAC_DCCSR_TT;
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//sd_tx_dma_callback();
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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void DMA_CALLBACK(DMA_SD_TX_CHANNEL1)(void)
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{
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_AR)
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{
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logf("SD TX DMA address error: %x, %x, %x", var1, var2, var3);
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_AR;
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panicf("SD TX DMA address error");
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}
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_HLT)
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{
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logf("SD TX DMA halt");
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_HLT;
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panicf("SD TX DMA halt");
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}
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if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) & DMAC_DCCSR_TT)
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{
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL(SD_SLOT_2)) &= ~DMAC_DCCSR_TT;
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//sd_tx_dma_callback();
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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#endif /* SD_DMA_INTERRUPT */
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#endif /* SD_DMA_ENABLE */
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@ -715,8 +727,6 @@ static void jz_sd_set_clock(const int drive, unsigned int rate)
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{
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int clkrt;
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jz_sd_stop_clock(drive);
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/* select clock source from CPM */
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cpm_select_msc_clk();
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@ -747,28 +757,27 @@ static int jz_sd_exec_cmd(const int drive, struct sd_request *request)
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/* On reset, 1-bit bus width */
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use_4bit[drive] = 0;
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/* On reset, stop SD clock */
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jz_sd_stop_clock(drive);
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/* Reset MMC/SD controller */
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__msc_reset(MSC_CHN(drive));
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/* On reset, drop SD clock down */
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/* Drop SD clock down to lowest speed */
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jz_sd_set_clock(drive, MMC_CLOCK_SLOW);
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/* On reset, stop SD clock */
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jz_sd_stop_clock(drive);
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#if SD_AUTO_CLOCK
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/* Re-enable clocks */
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REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_START;
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REG_MSC_LPM(drive) = MSC_SET_LPM;
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#endif
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}
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/* stop clock */
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jz_sd_stop_clock(drive);
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/* mask all interrupts and clear status */
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SD_IRQ_MASK(MSC_CHN(drive));
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/* open interrupt */
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#if SD_INTERRUPT
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REG_MSC_IMASK(MSC_CHN(drive)) = ~(MSC_IMASK_DATA_TRAN_DONE | MSC_IMASK_PRG_DONE);
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#else
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REG_MSC_IMASK(MSC_CHN(drive)) = ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_DATA_TRAN_DONE | MSC_IMASK_PRG_DONE);
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#endif
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/* Set command type and events */
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switch (request->cmd)
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@ -926,8 +935,8 @@ static int jz_sd_exec_cmd(const int drive, struct sd_request *request)
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return SD_ERROR_TIMEOUT;
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yield();
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}
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#endif
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REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_END_CMD_RES; /* clear flag */
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#endif
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/* Check for status */
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retval = jz_sd_check_status(drive, request);
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@ -964,8 +973,8 @@ static int jz_sd_exec_cmd(const int drive, struct sd_request *request)
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/* Wait for Data Done */
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while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_DATA_TRAN_DONE))
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yield();
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#endif
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REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_DATA_TRAN_DONE; /* clear status */
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#endif
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}
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/* Wait for Prog Done event */
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@ -976,11 +985,14 @@ static int jz_sd_exec_cmd(const int drive, struct sd_request *request)
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#else
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while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_PRG_DONE))
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yield();
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#endif
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REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_PRG_DONE; /* clear status */
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#endif
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}
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/* Command completed */
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#if !SD_AUTO_CLOCK
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jz_sd_stop_clock(drive); /* stop SD clock */
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#endif
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return SD_NO_ERROR; /* return successfully */
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}
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@ -996,18 +1008,45 @@ static int jz_sd_chkcard(const int drive)
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return (__gpio_get_pin((drive == SD_SLOT_1) ? PIN_SD1_CD : PIN_SD2_CD) == 0 ? 1 : 0);
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}
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/* MSC interrupt handler */
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void MSC(void)
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{
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/* MSC interrupt handlers */
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#if SD_INTERRUPT
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) & MSC_IREG_DATA_TRAN_DONE)
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void MSC2(void) /* SD_SLOT_1 */
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{
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logf("MSC2 interrupt");
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) & MSC_IREG_END_CMD_RES) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) = MSC_IREG_END_CMD_RES; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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else if (REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) & MSC_IREG_DATA_TRAN_DONE)
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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#endif
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logf("MSC interrupt");
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}
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) & MSC_IREG_PRG_DONE) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) = MSC_IREG_PRG_DONE; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) & MSC_IREG_DATA_TRAN_DONE) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_1)) = MSC_IREG_DATA_TRAN_DONE; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_1]);
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}
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}
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/* MSC interrupt handlers */
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void MSC1(void) /* SD_SLOT_2 */
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{
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logf("MSC1 interrupt");
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) & MSC_IREG_END_CMD_RES) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) = MSC_IREG_END_CMD_RES; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) & MSC_IREG_PRG_DONE) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) = MSC_IREG_PRG_DONE; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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if (REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) & MSC_IREG_DATA_TRAN_DONE) {
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REG_MSC_IREG(MSC_CHN(SD_SLOT_2)) = MSC_IREG_DATA_TRAN_DONE; /* clear flag */
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semaphore_release(&sd_wakeup[SD_SLOT_2]);
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}
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}
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#endif
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#ifdef HAVE_HOTSWAP
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static void sd_gpio_setup_irq(const int drive, bool inserted)
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{
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@ -1038,7 +1077,12 @@ static void jz_sd_hardware_init(const int drive)
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#endif
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__msc_reset(MSC_CHN(drive)); /* reset mmc/sd controller */
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SD_IRQ_MASK(MSC_CHN(drive)); /* mask all IRQs */
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#if SD_AUTO_CLOCK
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REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_START; /* Enable clocks */
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REG_MSC_LPM(drive) = MSC_SET_LPM; /* enable auto clock stop */
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#else
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jz_sd_stop_clock(drive); /* stop SD clock */
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#endif
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}
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static void sd_send_cmd(const int drive, struct sd_request *request, int cmd, unsigned int arg,
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@ -1315,6 +1359,11 @@ int sd_init(void)
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mutex_init(&sd_mtx[SD_SLOT_1]);
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mutex_init(&sd_mtx[SD_SLOT_2]);
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#if SD_INTERRUPT
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system_enable_irq(IRQ_MSC2);
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system_enable_irq(IRQ_MSC1);
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#endif
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#if SD_DMA_ENABLE && SD_DMA_INTERRUPT
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system_enable_irq(DMA_IRQ(DMA_SD_RX_CHANNEL(SD_SLOT_1)));
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system_enable_irq(DMA_IRQ(DMA_SD_RX_CHANNEL(SD_SLOT_2)));
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