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Further ARMv6 imdct optimisation, ~5.5% speedup.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21884 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
be54b7f6a2
commit
0a2197b846
1 changed files with 63 additions and 104 deletions
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@ -75,15 +75,17 @@
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add r11, r11, r3 @ a1 = a1' + a2'
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sub r3, r11, r3, lsl #1 @ a2 = a1 - 2 * a2'
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@ Special store order for making the column pass calculate columns in
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@ the order 0-2-1-3-4-6-5-7, allowing for uxtab16 use in later stages.
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sub r2, r10, r6 @ block[7] = (a0 - b0)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #7*16]
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sub r2, r11, r7 @ block[6] = (a1 - b1)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #6*16]
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strh r2, [r1, #5*16]
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sub r2, r3, r8 @ block[5] = (a2 - b2)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #5*16]
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strh r2, [r1, #6*16]
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sub r2, r12, r9 @ block[4] = (a3 - b3)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #4*16]
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@ -92,10 +94,10 @@
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strh r2, [r1, #3*16]
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add r2, r3, r8 @ block[2] = (a2 + b2)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #2*16]
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strh r2, [r1, #1*16]
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add r2, r11, r7 @ block[1] = (a1 + b1)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1, #1*16]
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strh r2, [r1, #2*16]
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add r2, r10, r6 @ block[0] = (a0 + b0)
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mov r2, r2, asr #12 @ >> 12
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strh r2, [r1], #2 @ advance to next temp column
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@ -200,34 +202,23 @@ mpeg2_idct_copy:
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bl .idct
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ldmfd sp!, {r1-r2}
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add r12, r0, #128
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ldrd r4, [r0]
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add r3, r0, #128
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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1:
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ldrd r6, [r0, #8]
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usat16 r4, #8, r4
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strb r4, [r1, #0]
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mov r4, r4, lsr #16
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strb r4, [r1, #1]
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usat16 r5, #8, r5
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strb r5, [r1, #2]
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mov r5, r5, lsr #16
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strb r5, [r1, #3]
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ldrd r4, [r0, #16]
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usat16 r6, #8, r6
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strb r6, [r1, #4]
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mov r6, r6, lsr #16
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strb r6, [r1, #5]
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usat16 r7, #8, r7
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strb r7, [r1, #6]
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mov r7, r7, lsr #16
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strb r7, [r1, #7]
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1: @ idct data is in order 0-2-1-3-4-6-5-7,
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ldmia r0, {r4-r7} @ see above
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stmia r0!, {r8-r11}
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usat16 r4, #8, r4
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usat16 r5, #8, r5
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orr r4, r4, r5, lsl #8
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usat16 r6, #8, r6
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usat16 r7, #8, r7
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orr r5, r6, r7, lsl #8
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strd r4, [r1] @ r4, r5
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add r1, r1, r2
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cmp r0, r12
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cmp r0, r3
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blo 1b
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ldmfd sp!, {r4-r11, pc}
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@ -244,93 +235,61 @@ mpeg2_idct_add:
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stmfd sp!, {r2-r11, lr}
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bl .idct
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ldmfd sp!, {r1-r2}
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add r3, r0, #128
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mov r10, #0
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mov r11, #0
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add r12, r0, #128
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2:
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ldmia r0, {r3-r6}
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ldrb r7, [r1, #0]
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ldrb r8, [r1, #1]
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ldrb r9, [r1, #2]
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ldrb r10, [r1, #3]
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str r11, [r0], #4
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orr r7, r7, r8, lsl #16
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sadd16 r3, r3, r7
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usat16 r3, #8, r3
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strb r3, [r1, #0]
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mov r3, r3, lsr #16
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strb r3, [r1, #1]
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str r11, [r0], #4
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orr r9, r9, r10, lsl #16
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sadd16 r4, r4, r9
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mov r12, #0
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mov lr, #0
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ldrd r8, [r1] @ r8, r9
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2: @ idct data is in order 0-2-1-3-4-6-5-7,
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ldmia r0, {r4-r7} @ see above
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stmia r0!, {r10-r12, lr}
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uxtab16 r4, r4, r8
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uxtab16 r5, r5, r8, ror #8
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usat16 r4, #8, r4
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strb r4, [r1, #2]
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mov r4, r4, lsr #16
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strb r4, [r1, #3]
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ldrb r7, [r1, #4]
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ldrb r8, [r1, #5]
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ldrb r9, [r1, #6]
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ldrb r10, [r1, #7]
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str r11, [r0], #4
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orr r7, r7, r8, lsl #16
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sadd16 r5, r5, r7
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usat16 r5, #8, r5
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strb r5, [r1, #4]
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mov r5, r5, lsr #16
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strb r5, [r1, #5]
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str r11, [r0], #4
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orr r9, r9, r10, lsl #16
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sadd16 r6, r6, r9
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orr r4, r4, r5, lsl #8
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uxtab16 r6, r6, r9
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uxtab16 r7, r7, r9, ror #8
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usat16 r6, #8, r6
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strb r6, [r1, #6]
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mov r6, r6, lsr #16
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strb r6, [r1, #7]
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usat16 r7, #8, r7
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orr r5, r6, r7, lsl #8
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strd r4, [r1] @ r4, r5
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add r1, r1, r2
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cmp r0, r12
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cmp r0, r3
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ldrlod r8, [r1] @ r8, r9
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blo 2b
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ldmfd sp!, {r4-r11, pc}
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3:
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stmfd sp!, {r4-r5, lr}
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ldrsh r1, [r0, #0] /* r1 = block[0] */
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mov r4, #0
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strh r4, [r0, #0] /* block[0] = 0 */
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strh r4, [r0, #126] /* block[63] = 0 */
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add r1, r1, #64 /* r1 = DC << 7 */
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add r0, r2, r3, asl #3
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stmfd sp!, {r4, lr}
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ldrsh r4, [r0, #0] @ r4 = block[0]
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mov r12, #0
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strh r12, [r0, #0] @ block[0] = 0
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strh r12, [r0, #126] @ block[63] = 0
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add r4, r4, #64
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mov r4, r4, asr #7 @ r4 = DC
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mov r4, r4, lsl #16 @ spread to 2 halfwords
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orr r4, r4, r4, lsr #16
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ldrd r0, [r2] @ r0, r1
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add r12, r2, r3, asl #3
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4:
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ldrb r4, [r2, #0]
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ldrb r5, [r2, #1]
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ldrb r12, [r2, #2]
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ldrb lr, [r2, #3]
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add r4, r4, r1, asr #7
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usat r4, #8, r4
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strb r4, [r2, #0]
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add r5, r5, r1, asr #7
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usat r5, #8, r5
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strb r5, [r2, #1]
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add r12, r12, r1, asr #7
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usat r12, #8, r12
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strb r12, [r2, #2]
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add lr, lr, r1, asr #7
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usat lr, #8, lr
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strb lr, [r2, #3]
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ldrb r4, [r2, #4]
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ldrb r5, [r2, #5]
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ldrb r12, [r2, #6]
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ldrb lr, [r2, #7]
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add r4, r4, r1, asr #7
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usat r4, #8, r4
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strb r4, [r2, #4]
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add r5, r5, r1, asr #7
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usat r5, #8, r5
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strb r5, [r2, #5]
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add r12, r12, r1, asr #7
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usat r12, #8, r12
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strb r12, [r2, #6]
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add lr, lr, r1, asr #7
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usat lr, #8, lr
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strb lr, [r2, #7]
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uxtab16 lr, r4, r0, ror #8
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uxtab16 r0, r4, r0
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usat16 lr, #8, lr
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usat16 r0, #8, r0
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orr r0, r0, lr, lsl #8
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uxtab16 lr, r4, r1, ror #8
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uxtab16 r1, r4, r1
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usat16 lr, #8, lr
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usat16 r1, #8, r1
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orr r1, r1, lr, lsl #8
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strd r0, [r2] @ r0, r1
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add r2, r2, r3
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cmp r2, r0
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cmp r2, r12
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ldrlod r0, [r2] @ r0, r1
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blo 4b
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ldmfd sp!, {r4-r5, pc}
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ldmfd sp!, {r4, pc}
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