len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-08 12:45:26 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

Port greylib blitting optimisation to clipv1.

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26557 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2010-06-04 21:12:06 +00:00
parent b91fa04250
commit 081bda8ab2
1 changed files with 16 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

44
firmware/target/arm/as3525/sansa-clip/lcd-as-clip.S
View file

@ -56,42 +56,30 @@ lcd_grey_data:
ldr lr, =DBOP_BASE
.greyloop:
ldmia r1, {r3-r4} /* Fetch 8 pixel phases */
ldmia r0!, {r5-r6} /* Fetch 8 pixel values */
mov r7, #0
ldmia r1, {r3-r4}
and r5, r12, r3 @ r5 = 3.......2.......1.......0.......
and r6, r12, r4 @ r6 = 7.......6.......5.......4.......
orr r5, r5, r6, lsr #4 @ r5 = 3...7...2...6...1...5...0...4...
orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..12..56..01..45..
orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.012.456.
orr r5, r5, r5, lsr #9 @ r5 = 3...7...23..67..123.567.01234567
and r5, r5, #0xff
orr r5, r5, r5, lsl #8 @ post processing for clipv1 LCD */
/* set bits 15..12 */
tst r3, #0x80
orrne r7, r7, #0x8000
tst r3, #0x8000
orrne r7, r7, #0x4000
tst r3, #0x800000
orrne r7, r7, #0x2000
tst r3, #0x80000000
orrne r7, r7, #0x1000
ldmia r0!, {r6-r7}
bic r3, r3, r12
add r3, r3, r5
/* set bits 3..0 */
tst r4, #0x80
orrne r7, r7, #0x08
tst r4, #0x8000
orrne r7, r7, #0x04
tst r4, #0x800000
orrne r7, r7, #0x02
tst r4, #0x80000000
orrne r7, r7, #0x01
add r3, r3, r6
bic r4, r4, r12
add r4, r4, r6
add r4, r4, r7
stmia r1!, {r3-r4}
strh r7, [lr, #0x10] @ DBOP_DOUT
strh r5, [lr, #0x10] @ DBOP_DOUT
1:
ldr r5, [lr, #0xC] @ DBOP_STAT
ands r5, r5, #(1<<6) @ wait until push fifo is full
ldr r6, [lr, #0xC] @ DBOP_STAT
ands r6, r6, #(1<<6) @ wait until push fifo is full
bne 1b
subs r2, r2, #1