mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-10-14 02:27:39 -04:00
iPod G4, Color/Photo and Nano audio driver rework: Fix playback after recording (FS #7402). Implement recording gain adjustment. * Fix slightly off Bass/Treble scale.
git-svn-id: svn://svn.rockbox.org/rockbox/branches/v3_0@18491 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
8739c8bb96
commit
079043fa3e
5 changed files with 444 additions and 184 deletions
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@ -34,9 +34,6 @@
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#include "audiohw.h"
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#include "i2s.h"
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/* use zero crossing to reduce clicks during volume changes */
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#define VOLUME_ZC_WAIT (1<<7)
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const struct sound_settings_info audiohw_settings[] = {
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[SOUND_VOLUME] = {"dB", 0, 1, -74, 6, -25},
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[SOUND_BASS] = {"dB", 0, 1, -6, 9, 0},
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@ -45,12 +42,38 @@ const struct sound_settings_info audiohw_settings[] = {
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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#ifdef HAVE_RECORDING
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[SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0},
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[SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16},
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[SOUND_LEFT_GAIN] = {"dB", 1, 1, 0, 63, 23},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1, 0, 63, 23},
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[SOUND_MIC_GAIN] = {"dB", 1, 1, 0, 63, 0},
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#endif
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};
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static unsigned short wm8975_regs[] =
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{
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[LINVOL] = LINVOL_LZCEN | 23, /* 0dB */
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[RINVOL] = RINVOL_RIVU | RINVOL_RZCEN | 23, /* 0dB */
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[DAPCTRL] = DAPCTRL_DACMU,
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[PWRMGMT1] = PWRMGMT1_VMIDSEL_5K | PWRMGMT1_VREF,
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[PWRMGMT2] = PWRMGMT2_DACL | PWRMGMT2_DACR | PWRMGMT2_LOUT1
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| PWRMGMT2_ROUT1 | PWRMGMT2_LOUT2 | PWRMGMT2_ROUT2,
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};
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static void wm8975_write(int reg, unsigned val)
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{
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wm8975_regs[reg] = val;
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wmcodec_write(reg, val);
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}
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static void wm8975_write_and(int reg, unsigned bits)
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{
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wm8975_write(reg, wm8975_regs[reg] & bits);
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}
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static void wm8975_write_or(int reg, unsigned bits)
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{
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wm8975_write(reg, wm8975_regs[reg] | bits);
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}
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/* convert tenth of dB volume (-730..60) to master volume register value */
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int tenthdb2master(int db)
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{
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@ -67,65 +90,83 @@ int tenthdb2master(int db)
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}
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}
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#define IPOD_PCM_LEVEL 0x65 /* -6dB */
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/* Silently enable / disable audio output */
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void audiohw_enable_output(bool enable)
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int sound_val2phys(int setting, int value)
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{
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if (enable)
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int result;
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switch(setting)
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{
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/* reset the I2S controller into known state */
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i2s_reset();
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#ifdef HAVE_RECORDING
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case SOUND_LEFT_GAIN:
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case SOUND_RIGHT_GAIN:
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result = ((value - 23) * 15) / 2;
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break;
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case SOUND_MIC_GAIN:
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result = ((value - 23) * 15) / 2 + 200;
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break;
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#endif
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default:
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result = value;
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break;
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}
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/*
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* 1. Switch on power supplies.
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* By default the WM8750L is in Standby Mode, the DAC is
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* digitally muted and the Audio Interface, Line outputs
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* and Headphone outputs are all OFF (DACMU = 1 Power
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* Management registers 1 and 2 are all zeros).
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*/
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wmcodec_write(RESET, 0x1ff); /*Reset*/
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wmcodec_write(RESET, 0x0);
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return result;
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}
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/* 2. Enable Vmid and VREF. */
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wmcodec_write(PWRMGMT1, 0xc0); /*Pwr Mgmt(1)*/
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/* From app notes: allow Vref to stabilize to reduce clicks */
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sleep(HZ/4);
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/* 3. Enable DACs as required. */
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wmcodec_write(PWRMGMT2, 0x180); /*Pwr Mgmt(2)*/
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/* 4. Enable line and / or headphone output buffers as required. */
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wmcodec_write(PWRMGMT2, 0x1f8); /*Pwr Mgmt(2)*/
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/* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */
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/* IWL=00(16 bit) FORMAT=10(I2S format) */
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wmcodec_write(AINTFCE, 0x42);
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/* The iPod can handle multiple frequencies, but fix at 44.1KHz for now */
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audiohw_set_sample_rate(WM8975_44100HZ);
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/* set the volume to -6dB */
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wmcodec_write(LOUT1VOL, VOLUME_ZC_WAIT | IPOD_PCM_LEVEL);
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wmcodec_write(ROUT1VOL, VOLUME_ZC_WAIT | 0x100 | IPOD_PCM_LEVEL);
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wmcodec_write(LOUTMIX1, 0x150); /* Left out Mix(def) */
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wmcodec_write(LOUTMIX2, 0x50);
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wmcodec_write(ROUTMIX1, 0x50); /* Right out Mix(def) */
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wmcodec_write(ROUTMIX2, 0x150);
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wmcodec_write(MOUTMIX1, 0x0); /* Mono out Mix */
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wmcodec_write(MOUTMIX2, 0x0);
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audiohw_mute(0);
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void audiohw_mute(bool mute)
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{
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if (mute) {
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/* Set DACMU = 1 to soft-mute the audio DACs. */
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wm8975_write_or(DAPCTRL, DAPCTRL_DACMU);
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} else {
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audiohw_mute(1);
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/* Set DACMU = 0 to soft-un-mute the audio DACs. */
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wm8975_write_and(DAPCTRL, ~DAPCTRL_DACMU);
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}
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}
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#define IPOD_PCM_LEVEL 0x65 /* -6dB */
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void audiohw_preinit(void)
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{
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i2s_reset();
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/* POWER UP SEQUENCE */
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wmcodec_write(RESET, RESET_RESET);
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/* 2. Enable Vmid and VREF, quick startup. */
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wm8975_write(PWRMGMT1, wm8975_regs[PWRMGMT1]);
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sleep(HZ/50);
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wm8975_regs[PWRMGMT1] &= ~PWRMGMT1_VMIDSEL_MASK;
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wm8975_write(PWRMGMT1, wm8975_regs[PWRMGMT1] | PWRMGMT1_VMIDSEL_50K);
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/* 4. Enable DACs, line and headphone output buffers as required. */
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wm8975_write(PWRMGMT2, wm8975_regs[PWRMGMT2]);
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wmcodec_write(AINTFCE, AINTFCE_MS | AINTFCE_LRP_I2S_RLO
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| AINTFCE_IWL_16BIT | AINTFCE_FORMAT_I2S);
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wm8975_write(DAPCTRL, wm8975_regs[DAPCTRL] );
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audiohw_set_sample_rate(WM8975_44100HZ);
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/* set the volume to -6dB */
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wmcodec_write(LOUT1VOL, LOUT1VOL_LO1ZC | IPOD_PCM_LEVEL);
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wmcodec_write(ROUT1VOL, ROUT1VOL_RO1VU | ROUT1VOL_RO1ZC | IPOD_PCM_LEVEL);
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wmcodec_write(LOUTMIX1, LOUTMIX1_LD2LO| LOUTMIX1_LI2LOVOL(5));
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wmcodec_write(LOUTMIX2, LOUTMIX2_RI2LOVOL(5));
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wmcodec_write(ROUTMIX1, ROUTMIX1_LI2ROVOL(5));
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wmcodec_write(ROUTMIX2, ROUTMIX2_RD2RO| ROUTMIX2_RI2ROVOL(5));
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wmcodec_write(MOUTMIX1, 0);
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wmcodec_write(MOUTMIX2, 0);
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}
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void audiohw_postinit(void)
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{
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audiohw_mute(false);
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}
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void audiohw_set_master_vol(int vol_l, int vol_r)
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@ -137,163 +178,137 @@ void audiohw_set_master_vol(int vol_l, int vol_r)
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/* 0101111 == mute (0x2f) */
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/* OUT1 */
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wmcodec_write(LOUT1VOL, VOLUME_ZC_WAIT | vol_l);
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wmcodec_write(ROUT1VOL, VOLUME_ZC_WAIT | 0x100 | vol_r);
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wmcodec_write(LOUT1VOL, LOUT1VOL_LO1ZC | vol_l);
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wmcodec_write(ROUT1VOL, ROUT1VOL_RO1VU | ROUT1VOL_RO1ZC | vol_r);
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}
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void audiohw_set_lineout_vol(int vol_l, int vol_r)
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{
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/* OUT2 */
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wmcodec_write(LOUT2VOL, VOLUME_ZC_WAIT | vol_l);
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wmcodec_write(ROUT2VOL, VOLUME_ZC_WAIT | 0x100 | vol_r);
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wmcodec_write(LOUT2VOL, LOUT2VOL_LO2ZC | vol_l);
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wmcodec_write(ROUT2VOL, ROUT2VOL_RO2VU | ROUT2VOL_RO2ZC | vol_r);
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}
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void audiohw_set_bass(int value)
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{
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const int regvalues[] = {
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11, 10, 10, 9, 8, 8, 0xf, 6, 6, 5, 4, 4, 3, 2, 1, 0
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11, 10, 10, 9, 8, 8, 0xf, 6, 6, 5, 4, 4, 3, 2, 2, 1
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};
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if ((value >= -6) && (value <= 9)) {
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/* We use linear bass control with 200 Hz cutoff */
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wmcodec_write(BASSCTRL, regvalues[value + 6] | 0x40);
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wmcodec_write(BASSCTRL, regvalues[value + 6] | BASSCTRL_BC);
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}
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}
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void audiohw_set_treble(int value)
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{
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const int regvalues[] = {
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11, 10, 10, 9, 8, 8, 0xf, 6, 6, 5, 4, 4, 3, 2, 1, 0
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11, 10, 10, 9, 8, 8, 0xf, 6, 6, 5, 4, 4, 3, 2, 2, 1
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};
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if ((value >= -6) && (value <= 9)) {
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/* We use linear treble control with 4 kHz cutoff */
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wmcodec_write(TREBCTRL, regvalues[value + 6] | 0x40);
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}
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}
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void audiohw_mute(bool mute)
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{
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if (mute)
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{
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/* Set DACMU = 1 to soft-mute the audio DACs. */
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wmcodec_write(DACCTRL, 0x8);
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} else {
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/* Set DACMU = 0 to soft-un-mute the audio DACs. */
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wmcodec_write(DACCTRL, 0x0);
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wmcodec_write(TREBCTRL, regvalues[value + 6] | TREBCTRL_TC);
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}
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}
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/* Nice shutdown of WM8975 codec */
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void audiohw_close(void)
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{
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/* 1. Set DACMU = 1 to soft-mute the audio DACs. */
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wmcodec_write(DACCTRL, 0x8);
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audiohw_mute(true);
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/* 2. Disable all output buffers. */
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wmcodec_write(PWRMGMT2, 0x0); /*Pwr Mgmt(2)*/
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wmcodec_write(PWRMGMT2, 0x0);
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/* 3. Switch off the power supplies. */
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wmcodec_write(PWRMGMT1, 0x0); /*Pwr Mgmt(1)*/
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wmcodec_write(PWRMGMT1, 0x0);
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}
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/* Change the order of the noise shaper, 5th order is recommended above 32kHz */
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void audiohw_set_nsorder(int order)
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{
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(void)order;
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}
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/* Note: Disable output before calling this function */
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void audiohw_set_sample_rate(int sampling_control) {
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wmcodec_write(0x08, sampling_control);
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void audiohw_set_sample_rate(int sampling_control)
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{
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wmcodec_write(SAMPCTRL, sampling_control);
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}
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#ifdef HAVE_RECORDING
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void audiohw_enable_recording(bool source_mic)
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{
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(void)source_mic;
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wm8975_regs[PWRMGMT1] |= PWRMGMT1_AINL | PWRMGMT1_AINR
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| PWRMGMT1_ADCL | PWRMGMT1_ADCR;
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wm8975_write(PWRMGMT1, wm8975_regs[PWRMGMT1]);
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/* reset the I2S controller into known state */
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i2s_reset();
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/* NOTE: When switching to digital monitoring we will not want
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* the DACs disabled. Also the outputs shouldn't be disabled
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* when recording from line in (dock connector) - needs testing. */
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wm8975_regs[PWRMGMT2] &= ~(PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1
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| PWRMGMT2_LOUT2 | PWRMGMT2_ROUT2);
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wm8975_write(PWRMGMT2, wm8975_regs[PWRMGMT2]);
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/*
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* 1. Switch on power supplies.
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* By default the WM8750L is in Standby Mode, the DAC is
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* digitally muted and the Audio Interface, Line outputs
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* and Headphone outputs are all OFF (DACMU = 1 Power
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* Management registers 1 and 2 are all zeros).
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*/
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wmcodec_write(0x0f, 0x1ff);
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wmcodec_write(0x0f, 0x000);
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wm8975_write_or(LINVOL, LINVOL_LINMUTE);
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wm8975_write_or(RINVOL, RINVOL_RINMUTE);
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/* 2. Enable Vmid and VREF. */
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wmcodec_write(0x19, 0xc0); /*Pwr Mgmt(1)*/
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/* 3. Enable ADCs as required. */
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wmcodec_write(0x19, 0xcc); /*Pwr Mgmt(1)*/
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wmcodec_write(0x1a, 0x180); /*Pwr Mgmt(2)*/
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/* 4. Enable line and / or headphone output buffers as required. */
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wmcodec_write(0x19, 0xfc); /*Pwr Mgmt(1)*/
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/* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */
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/* IWL=00(16 bit) FORMAT=10(I2S format) */
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wmcodec_write(0x07, 0x42);
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/* The iPod can handle multiple frequencies, but fix at 44.1KHz for now */
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audiohw_set_sample_rate(WM8975_44100HZ);
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/* unmute inputs */
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wmcodec_write(0x00, 0x17); /* LINVOL (def 0dB) */
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wmcodec_write(0x01, 0x117); /* RINVOL (def 0dB) */
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wmcodec_write(0x15, 0x1d7); /* LADCVOL max vol x was ff */
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wmcodec_write(0x16, 0x1d7); /* RADCVOL max vol x was ff */
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wmcodec_write(ADDCTRL3, ADDCTRL3_VROI);
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if (source_mic) {
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/* VSEL=10(def) DATSEL=10 (use right ADC only) */
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wmcodec_write(0x17, 0xc9); /* Additional control(1) */
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/* VROI=1 (sets output resistance to 40kohms) */
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wmcodec_write(0x1b, 0x40); /* Additional control(3) */
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/* LINSEL=1 (LINPUT2) LMICBOOST=10 (20dB boost) */
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wmcodec_write(0x20, 0x60); /* ADCL signal path */
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wmcodec_write(0x21, 0x60); /* ADCR signal path */
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wmcodec_write(ADDCTRL1, ADDCTRL1_VSEL_LOWBIAS | ADDCTRL1_DATSEL_RADC
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| ADDCTRL1_TOEN);
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wmcodec_write(ADCLPATH, 0);
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wmcodec_write(ADCRPATH, ADCRPATH_RINSEL_RIN2 | ADCRPATH_RMICBOOST_20dB);
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} else {
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/* VSEL=10(def) DATSEL=00 (left->left, right->right) */
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wmcodec_write(0x17, 0xc1); /* Additional control(1) */
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wmcodec_write(ADDCTRL1, ADDCTRL1_VSEL_LOWBIAS | ADDCTRL1_DATSEL_NORMAL
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| ADDCTRL1_TOEN);
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wmcodec_write(ADCLPATH, ADCLPATH_LINSEL_LIN1 | ADCLPATH_LMICBOOST_OFF);
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wmcodec_write(ADCRPATH, ADCRPATH_RINSEL_RIN1 | ADCRPATH_RMICBOOST_OFF);
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}
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wm8975_write_and(LINVOL, ~LINVOL_LINMUTE);
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wm8975_write_and(RINVOL, ~RINVOL_RINMUTE);
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}
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/* VROI=1 (sets output resistance to 40kohms) */
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wmcodec_write(0x1b, 0x40); /* Additional control(3) */
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void audiohw_disable_recording(void)
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{
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/* mute inputs */
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wm8975_write_or(LINVOL, LINVOL_LINMUTE);
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wm8975_write_or(RINVOL, RINVOL_RINMUTE);
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/* LINSEL=0 (LINPUT1) LMICBOOST=00 (bypass boost) */
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wmcodec_write(0x20, 0x00); /* ADCL signal path */
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/* RINSEL=0 (RINPUT1) RMICBOOST=00 (bypass boost) */
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wmcodec_write(0x21, 0x00); /* ADCR signal path */
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wmcodec_write(ADDCTRL3, 0);
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wm8975_regs[PWRMGMT2] |= PWRMGMT2_DACL | PWRMGMT2_DACR
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| PWRMGMT2_LOUT1 | PWRMGMT2_ROUT1
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| PWRMGMT2_LOUT2 | PWRMGMT2_ROUT2;
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wm8975_write(PWRMGMT2, wm8975_regs[PWRMGMT2]);
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wm8975_regs[PWRMGMT1] &= ~(PWRMGMT1_AINL | PWRMGMT1_AINR
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| PWRMGMT1_ADCL | PWRMGMT1_ADCR);
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wm8975_write(PWRMGMT1, wm8975_regs[PWRMGMT1]);
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}
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void audiohw_set_recvol(int left, int right, int type)
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{
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switch (type)
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{
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case AUDIO_GAIN_MIC: /* Mic uses right ADC */
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wm8975_regs[RINVOL] &= ~RINVOL_MASK;
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wm8975_write_or(RINVOL, left & RINVOL_MASK);
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break;
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case AUDIO_GAIN_LINEIN:
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wm8975_regs[LINVOL] &= ~LINVOL_MASK;
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wm8975_write_or(LINVOL, left & LINVOL_MASK);
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wm8975_regs[RINVOL] &= ~RINVOL_MASK;
|
||||
wm8975_write_or(RINVOL, right & RINVOL_MASK);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void audiohw_disable_recording(void) {
|
||||
/* 1. Set DACMU = 1 to soft-mute the audio DACs. */
|
||||
wmcodec_write(0x05, 0x8);
|
||||
|
||||
/* 2. Disable all output buffers. */
|
||||
wmcodec_write(0x1a, 0x0); /*Pwr Mgmt(2)*/
|
||||
|
||||
/* 3. Switch off the power supplies. */
|
||||
wmcodec_write(0x19, 0x0); /*Pwr Mgmt(1)*/
|
||||
}
|
||||
|
||||
void audiohw_set_recvol(int left, int right, int type) {
|
||||
|
||||
(void)left;
|
||||
(void)right;
|
||||
(void)type;
|
||||
}
|
||||
|
||||
void audiohw_set_monitor(bool enable) {
|
||||
|
||||
void audiohw_set_monitor(bool enable)
|
||||
{
|
||||
(void)enable;
|
||||
}
|
||||
#endif /* HAVE_RECORDING */
|
||||
|
|
|
|||
|
|
@ -35,26 +35,264 @@ extern void audiohw_set_lineout_vol(int vol_l, int vol_r);
|
|||
extern void audiohw_set_nsorder(int order);
|
||||
extern void audiohw_set_sample_rate(int sampling_control);
|
||||
|
||||
/* Register addresses */
|
||||
#define LOUT1VOL 0x02
|
||||
#define ROUT1VOL 0x03
|
||||
#define DACCTRL 0x05
|
||||
#define AINTFCE 0x07
|
||||
#define BASSCTRL 0x0c
|
||||
#define TREBCTRL 0x0d
|
||||
#define RESET 0x0f
|
||||
#define PWRMGMT1 0x19
|
||||
#define PWRMGMT2 0x1a
|
||||
#define LOUTMIX1 0x22
|
||||
#define LOUTMIX2 0x23
|
||||
#define ROUTMIX1 0x24
|
||||
#define ROUTMIX2 0x25
|
||||
#define MOUTMIX1 0x26
|
||||
#define MOUTMIX2 0x27
|
||||
#define LOUT2VOL 0x28
|
||||
#define ROUT2VOL 0x29
|
||||
/* Register addresses and bits */
|
||||
|
||||
/* Register settings for the supported samplerates: */
|
||||
#define LINVOL 0x00
|
||||
#define LINVOL_MASK 0x3f
|
||||
#define LINVOL_LZCEN (1 << 6)
|
||||
#define LINVOL_LINMUTE (1 << 7)
|
||||
#define LINVOL_LIVU (1 << 8)
|
||||
|
||||
#define RINVOL 0x01
|
||||
#define RINVOL_MASK 0x3f
|
||||
#define RINVOL_RZCEN (1 << 6)
|
||||
#define RINVOL_RINMUTE (1 << 7)
|
||||
#define RINVOL_RIVU (1 << 8)
|
||||
|
||||
#define LOUT1VOL 0x02
|
||||
#define LOUT1VOL_MASK 0x7f
|
||||
#define LOUT1VOL_LO1ZC (1 << 7)
|
||||
#define LOUT1VOL_LO1VU (1 << 8)
|
||||
|
||||
#define ROUT1VOL 0x03
|
||||
#define ROUT1VOL_MASK 0x7f
|
||||
#define ROUT1VOL_RO1ZC (1 << 7)
|
||||
#define ROUT1VOL_RO1VU (1 << 8)
|
||||
|
||||
#define DAPCTRL 0x05 /* Digital audio path control */
|
||||
#define DAPCTRL_ADCHPD (1 << 0)
|
||||
#define DAPCTRL_DEEMP_DISABLE (0 << 1)
|
||||
#define DAPCTRL_DEEMP_32KHz (1 << 1)
|
||||
#define DAPCTRL_DEEMP_44KHz (2 << 1)
|
||||
#define DAPCTRL_DEEMP_48KHz (3 << 1)
|
||||
#define DAPCTRL_DEEMP_MASK (3 << 1)
|
||||
#define DAPCTRL_DACMU (1 << 3)
|
||||
#define DAPCTRL_HPOR (1 << 4)
|
||||
#define DAPCTRL_ADCPOL_NORMAL (0 << 5)
|
||||
#define DAPCTRL_ADCPOL_LINVERT (1 << 5)
|
||||
#define DAPCTRL_ADCPOL_RINVERT (2 << 5)
|
||||
#define DAPCTRL_ADCPOL_LRINVERT (3 << 5)
|
||||
#define DAPCTRL_ADCPOL_MASK (3 << 5)
|
||||
#define DAPCTRL_DACDIV2 (1 << 7)
|
||||
#define DAPCTRL_ADCDIV2 (1 << 8)
|
||||
|
||||
#define AINTFCE 0x07
|
||||
#define AINTFCE_FORMAT_MSB_RJUST (0 << 0)
|
||||
#define AINTFCE_FORMAT_MSB_LJUST (1 << 0)
|
||||
#define AINTFCE_FORMAT_I2S (2 << 0)
|
||||
#define AINTFCE_FORMAT_DSP (3 << 0)
|
||||
#define AINTFCE_FORMAT_MASK (3 << 0)
|
||||
#define AINTFCE_IWL_16BIT (0 << 2)
|
||||
#define AINTFCE_IWL_20BIT (1 << 2)
|
||||
#define AINTFCE_IWL_24BIT (2 << 2)
|
||||
#define AINTFCE_IWL_32BIT (3 << 2)
|
||||
#define AINTFCE_IWL_MASK (3 << 2)
|
||||
#define AINTFCE_LRP_I2S_RLO (0 << 4)
|
||||
#define AINTFCE_LRP_I2S_RHI (1 << 4)
|
||||
#define AINTFCE_DSP_MODE_B (0 << 4)
|
||||
#define AINTFCE_DSP_MODE_A (1 << 4)
|
||||
#define AINTFCE_LRSWAP (1 << 5)
|
||||
#define AINTFCE_MS (1 << 6)
|
||||
#define AINTFCE_BCLKINV (1 << 7)
|
||||
|
||||
#define SAMPCTRL 0x08
|
||||
#define SAMPCTRL_USB (1 << 0)
|
||||
/* Bits 1-5:
|
||||
* Sample rate setting are device-specific. See datasheet
|
||||
* for proper settings for the device's clocking */
|
||||
#define SAMPCTRL_SR_MASK (0x1f << 1)
|
||||
#define SAMPCTRL_CLKDIV2 (1 << 6)
|
||||
#define SAMPCTRL_BCM_OFF (0 << 7)
|
||||
#define SAMPCTRL_BCM_MCLK_4 (1 << 7)
|
||||
#define SAMPCTRL_BCM_MCLK_8 (2 << 7)
|
||||
#define SAMPCTRL_BCM_MCLK_16 (3 << 7)
|
||||
|
||||
#define LDACVOL 0x0a
|
||||
#define LDACVOL_MASK 0xff
|
||||
#define LDACVOL_LDVU (1 << 8)
|
||||
|
||||
#define RDACVOL 0x0b
|
||||
#define RDACVOL_MASK 0xff
|
||||
#define RDACVOL_RDVU (1 << 8)
|
||||
|
||||
#define BASSCTRL 0x0c
|
||||
#define BASSCTRL_MASK 0x0f
|
||||
#define BASSCTRL_BC (1 << 6)
|
||||
#define BASSCTRL_BB (1 << 7)
|
||||
|
||||
#define TREBCTRL 0x0d
|
||||
#define TREBCTRL_MASK 0x0f
|
||||
#define TREBCTRL_TC (1 << 6)
|
||||
|
||||
#define RESET 0x0f
|
||||
#define RESET_RESET 0x0
|
||||
|
||||
/* not used atm */
|
||||
#define ALC1 0x11
|
||||
#define ALC2 0x12
|
||||
#define ALC3 0x13
|
||||
#define NOISEGATE 0x14
|
||||
|
||||
#define LADCVOL 0x15
|
||||
#define LADCVOL_MASK 0xff
|
||||
#define LADCVOL_LAVU (1 << 8)
|
||||
|
||||
#define RADCVOL 0x16
|
||||
#define RADCVOL_MASK 0xff
|
||||
#define RADCVOL_RAVU (1 << 8)
|
||||
|
||||
#define ADDCTRL1 0x17
|
||||
#define ADDCTRL1_TOEN (1 << 0)
|
||||
#define ADDCTRL1DACINV (1 << 1)
|
||||
#define ADDCTRL1_DATSEL_NORMAL (0 << 2)
|
||||
#define ADDCTRL1_DATSEL_LADC (1 << 2)
|
||||
#define ADDCTRL1_DATSEL_RADC (2 << 2)
|
||||
#define ADDCTRL1_DATSEL_SWAPPED (3 << 2)
|
||||
#define ADDCTRL1_DMONOMIX_STEREO (0 << 4)
|
||||
#define ADDCTRL1_DMONOMIX_MONOLEFT (1 << 4)
|
||||
#define ADDCTRL1_DMONOMIX_MONORIGHT (2 << 4)
|
||||
#define ADDCTRL1_DMONOMIX_MONO (3 << 4)
|
||||
#define ADDCTRL1_VSEL_HIGHBIAS (0 << 6)
|
||||
#define ADDCTRL1_VSEL_MEDBIAS (1 << 6)
|
||||
#define ADDCTRL1_VSEL_LOWBIAS (3 << 6)
|
||||
#define ADDCTRL1_TSDEN (1 << 8)
|
||||
|
||||
#define ADDCTRL2 0x18
|
||||
#define ADDCTRL2_DACOSR (1 << 0)
|
||||
#define ADDCTRL2_ADCOSR (1 << 1)
|
||||
#define ADDCTRL2_LRCM (1 << 2)
|
||||
#define ADDCTRL2_TRI (1 << 3)
|
||||
#define ADDCTRL2_ROUT2INV (1 << 4)
|
||||
#define ADDCTRL2_HPSWPOL (1 << 5)
|
||||
#define ADDCTRL2_HPSWEN (1 << 6)
|
||||
#define ADDCTRL2_OUT3SW_VREF (0 << 7)
|
||||
#define ADDCTRL2_OUT3SW_ROUT1 (1 << 7)
|
||||
#define ADDCTRL2_OUT3SW_MONOOUT (2 << 7)
|
||||
#define ADDCTRL2_OUT3SW_ROUTMIX (3 << 7)
|
||||
|
||||
#define PWRMGMT1 0x19
|
||||
#define PWRMGMT1_DIGENB (1 << 0)
|
||||
#define PWRMGMT1_MICB (1 << 1)
|
||||
#define PWRMGMT1_ADCR (1 << 2)
|
||||
#define PWRMGMT1_ADCL (1 << 3)
|
||||
#define PWRMGMT1_AINR (1 << 4)
|
||||
#define PWRMGMT1_AINL (1 << 5)
|
||||
#define PWRMGMT1_VREF (1 << 6)
|
||||
#define PWRMGMT1_VMIDSEL_OFF (0 << 7)
|
||||
#define PWRMGMT1_VMIDSEL_50K (1 << 7)
|
||||
#define PWRMGMT1_VMIDSEL_500K (2 << 7)
|
||||
#define PWRMGMT1_VMIDSEL_5K (3 << 7)
|
||||
#define PWRMGMT1_VMIDSEL_MASK (3 << 7)
|
||||
|
||||
#define PWRMGMT2 0x1a
|
||||
#define PWRMGMT2_OUT3 (1 << 1)
|
||||
#define PWRMGMT2_MONO (1 << 2)
|
||||
#define PWRMGMT2_ROUT2 (1 << 3)
|
||||
#define PWRMGMT2_LOUT2 (1 << 4)
|
||||
#define PWRMGMT2_ROUT1 (1 << 5)
|
||||
#define PWRMGMT2_LOUT1 (1 << 6)
|
||||
#define PWRMGMT2_DACR (1 << 7)
|
||||
#define PWRMGMT2_DACL (1 << 8)
|
||||
|
||||
#define ADDCTRL3 0x1b
|
||||
#define ADDCTRL3_HPFLREN (1 << 5)
|
||||
#define ADDCTRL3_VROI (1 << 6)
|
||||
#define ADDCTRL3_ADCLRM_IN (0 << 7)
|
||||
#define ADDCTRL3_ADCLRM_MCLK (1 << 7)
|
||||
#define ADDCTRL3_ADCLRM_MCLK_55 (2 << 7)
|
||||
#define ADDCTRL3_ADCLRM_MCLK_6 (3 << 7)
|
||||
|
||||
#define ADCINMODE 0x1f
|
||||
#define ADCINMODE_LDCM (1 << 4)
|
||||
#define ADCINMODE_RDCM (1 << 5)
|
||||
#define ADCINMODE_MONOMIX_STEREO (0 << 6)
|
||||
#define ADCINMODE_MONOMIX_LADC (1 << 6)
|
||||
#define ADCINMODE_MONOMIX_RADC (2 << 6)
|
||||
#define ADCINMODE_MONOMIX_DIGITAL (3 << 6)
|
||||
#define ADCINMODE_DS (1 << 8)
|
||||
|
||||
#define ADCLPATH 0x20
|
||||
#define ADCLPATH_LMICBOOST_OFF (0 << 4)
|
||||
#define ADCLPATH_LMICBOOST_13dB (1 << 4)
|
||||
#define ADCLPATH_LMICBOOST_20dB (2 << 4)
|
||||
#define ADCLPATH_LMICBOOST_29dB (3 << 4)
|
||||
#define ADCLPATH_LINSEL_LIN1 (0 << 6)
|
||||
#define ADCLPATH_LINSEL_LIN2 (1 << 6)
|
||||
#define ADCLPATH_LINSEL_LIN3 (2 << 6)
|
||||
#define ADCLPATH_LINSEL_DIFF (3 << 6)
|
||||
|
||||
#define ADCRPATH 0x21
|
||||
#define ADCRPATH_RMICBOOST_OFF (0 << 4)
|
||||
#define ADCRPATH_RMICBOOST_13dB (1 << 4)
|
||||
#define ADCRPATH_RMICBOOST_20dB (2 << 4)
|
||||
#define ADCRPATH_RMICBOOST_29dB (3 << 4)
|
||||
#define ADCRPATH_RINSEL_RIN1 (0 << 6)
|
||||
#define ADCRPATH_RINSEL_RIN2 (1 << 6)
|
||||
#define ADCRPATH_RINSEL_RIN3 (2 << 6)
|
||||
#define ADCRPATH_RINSEL_DIFF (3 << 6)
|
||||
|
||||
#define LOUTMIX1 0x22
|
||||
#define LOUTMIX1_LMIXSEL_LIN1 (0 << 0)
|
||||
#define LOUTMIX1_LMIXSEL_LIN2 (1 << 0)
|
||||
#define LOUTMIX1_LMIXSEL_LIN3 (2 << 0)
|
||||
#define LOUTMIX1_LMIXSEL_LADCIN (3 << 0)
|
||||
#define LOUTMIX1_LMIXSEL_DIFF (4 << 0)
|
||||
#define LOUTMIX1_LI2LOVOL(x) ((x & 7) << 4)
|
||||
#define LOUTMIX1_LI2LOVOL_MASK (7 << 4)
|
||||
#define LOUTMIX1_LI2LO (1 << 7)
|
||||
#define LOUTMIX1_LD2LO (1 << 8)
|
||||
|
||||
#define LOUTMIX2 0x23
|
||||
#define LOUTMIX2_RI2LOVOL(x) ((x & 7) << 4)
|
||||
#define LOUTMIX2_RI2LOVOL_MASK (7 << 4)
|
||||
#define LOUTMIX2_RI2LO (1 << 7)
|
||||
#define LOUTMIX2_RD2LO (1 << 8)
|
||||
|
||||
#define ROUTMIX1 0x24
|
||||
#define ROUTMIX1_RMIXSEL_RIN1 (0 << 0)
|
||||
#define ROUTMIX1_RMIXSEL_RIN2 (1 << 0)
|
||||
#define ROUTMIX1_RMIXSEL_RIN3 (2 << 0)
|
||||
#define ROUTMIX1_RMIXSEL_RADCIN (3 << 0)
|
||||
#define ROUTMIX1_RMIXSEL_DIFF (4 << 0)
|
||||
#define ROUTMIX1_LI2ROVOL(x) ((x & 7) << 4)
|
||||
#define ROUTMIX1_LI2ROVOL_MASK (7 << 4)
|
||||
#define ROUTMIX1_LI2RO (1 << 7)
|
||||
#define ROUTMIX1_LD2RO (1 << 8)
|
||||
|
||||
#define ROUTMIX2 0x25
|
||||
#define ROUTMIX2_RI2ROVOL(x) ((x & 7) << 4)
|
||||
#define ROUTMIX2_RI2ROVOL_MASK (7 << 4)
|
||||
#define ROUTMIX2_RI2RO (1 << 7)
|
||||
#define ROUTMIX2_RD2RO (1 << 8)
|
||||
|
||||
#define MOUTMIX1 0x26
|
||||
#define MOUTMIX1_LI2MOVOL(x) ((x & 7) << 4)
|
||||
#define MOUTMIX1_LI2MOVOL_MASK (7 << 4)
|
||||
#define MOUTMIX1_LI2MO (1 << 7)
|
||||
#define MOUTMIX1_LD2MO (1 << 8)
|
||||
|
||||
#define MOUTMIX2 0x27
|
||||
#define MOUTMIX2_RI2MOVOL(x) ((x & 7) << 4)
|
||||
#define MOUTMIX2_RI2MOVOL_MASK (7 << 4)
|
||||
#define MOUTMIX2_RI2MO (1 << 7)
|
||||
#define MOUTMIX2_RD2MO (1 << 8)
|
||||
|
||||
#define LOUT2VOL 0x28
|
||||
#define LOUT2VOL_MASK 0x7f
|
||||
#define LOUT2VOL_LO2ZC (1 << 7)
|
||||
#define LOUT2VOL_LO2VU (1 << 8)
|
||||
|
||||
#define ROUT2VOL 0x29
|
||||
#define ROUT2VOL_MASK 0x7f
|
||||
#define ROUT2VOL_RO2ZC (1 << 7)
|
||||
#define ROUT2VOL_RO2VU (1 << 8)
|
||||
|
||||
#define MOUTVOL 0x2a
|
||||
#define MOUTVOL_MASK 0x7f
|
||||
#define MOUTVOL_MOZC (1 << 7)
|
||||
|
||||
|
||||
/* SAMPCTRL values for the supported samplerates: */
|
||||
#define WM8975_8000HZ 0x4d
|
||||
#define WM8975_12000HZ 0x61
|
||||
#define WM8975_16000HZ 0x55
|
||||
|
|
|
|||
|
|
@ -625,8 +625,8 @@ void sound_set(int setting, int value)
|
|||
sound_set_val(value);
|
||||
}
|
||||
|
||||
#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731) && !defined(HAVE_TSC2100)) \
|
||||
|| defined(SIMULATOR)
|
||||
#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731) && !defined (HAVE_WM8975) \
|
||||
&& !defined(HAVE_TSC2100)) || defined(SIMULATOR)
|
||||
int sound_val2phys(int setting, int value)
|
||||
{
|
||||
#if CONFIG_CODEC == MAS3587F
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@ void pcm_play_dma_init(void)
|
|||
/* Initialize default register values. */
|
||||
audiohw_init();
|
||||
|
||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751)
|
||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
|
||||
/* Power on */
|
||||
audiohw_enable_output(true);
|
||||
/* Unmute the master channel (DAC should be at zero point now). */
|
||||
|
|
@ -590,6 +590,13 @@ void pcm_rec_dma_start(void *addr, size_t size)
|
|||
void pcm_rec_dma_close(void)
|
||||
{
|
||||
pcm_rec_dma_stop();
|
||||
|
||||
#if defined(IPOD_COLOR) || defined (IPOD_4G)
|
||||
/* The usual magic from IPL - I'm guessing this configures the headphone
|
||||
socket to be input or output - in this case, output. */
|
||||
GPIO_SET_BITWISE(GPIOI_OUTPUT_VAL, 0x40);
|
||||
GPIO_SET_BITWISE(GPIOA_OUTPUT_VAL, 0x04);
|
||||
#endif
|
||||
} /* pcm_close_recording */
|
||||
|
||||
void pcm_rec_dma_init(void)
|
||||
|
|
@ -597,8 +604,8 @@ void pcm_rec_dma_init(void)
|
|||
#if defined(IPOD_COLOR) || defined (IPOD_4G)
|
||||
/* The usual magic from IPL - I'm guessing this configures the headphone
|
||||
socket to be input or output - in this case, input. */
|
||||
GPIOI_OUTPUT_VAL &= ~0x40;
|
||||
GPIOA_OUTPUT_VAL &= ~0x4;
|
||||
GPIO_CLEAR_BITWISE(GPIOI_OUTPUT_VAL, 0x40);
|
||||
GPIO_CLEAR_BITWISE(GPIOA_OUTPUT_VAL, 0x04);
|
||||
#endif
|
||||
|
||||
pcm_rec_dma_stop();
|
||||
|
|
|
|||
|
|
@ -96,13 +96,13 @@ void audiohw_init(void) {
|
|||
#endif /* IPOD_1G2G/3G */
|
||||
#endif
|
||||
|
||||
#if defined(HAVE_WM8731) || defined(HAVE_WM8751)
|
||||
#if defined(HAVE_WM8731) || defined(HAVE_WM8751) || defined(HAVE_WM8975)
|
||||
audiohw_preinit();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751)
|
||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
|
||||
void audiohw_postinit(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue