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Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).

Browse source 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-04-06 04:34:57 +00:00
parent be698f086d
commit 05099149f1
40 changed files with 323 additions and 126 deletions
Download patch file Download diff file Expand all files Collapse all files

2
firmware/drivers/ata.c
View file

@ -134,7 +134,7 @@ static void ata_lock_unlock(struct ata_lock *l)
#define mutex_unlock ata_lock_unlock
#endif /* MAX_PHYS_SECTOR_SIZE */
static struct mutex ata_mtx NOCACHEBSS_ATTR;
static struct mutex ata_mtx SHAREDBSS_ATTR;
int ata_device; /* device 0 (master) or 1 (slave) */
int ata_spinup_time = 0;

2
firmware/drivers/fat.c
View file

@ -201,7 +201,7 @@ struct fat_cache_entry
static char fat_cache_sectors[FAT_CACHE_SIZE][SECTOR_SIZE];
static struct fat_cache_entry fat_cache[FAT_CACHE_SIZE];
static struct mutex cache_mutex NOCACHEBSS_ATTR;
static struct mutex cache_mutex SHAREDBSS_ATTR;
#if defined(HAVE_HOTSWAP) && !defined(HAVE_MMC) /* A better condition ?? */
void fat_lock(void)

24
firmware/export/config.h
View file

@ -457,25 +457,30 @@
and not a special semaphore instruction */
#define CORELOCK_SWAP 2 /* A swap (exchange) instruction */
/* Dual core support - not yet working on the 1G/2G and 3G iPod */
#if defined(CPU_PP)
#define IDLE_STACK_SIZE 0x80
#define IDLE_STACK_WORDS 0x20
/* Attributes to place data in uncached DRAM */
/* These are useful beyond dual-core and ultimately beyond PP since they may
* be used for DMA buffers and such without cache maintenence calls. */
#define NOCACHEBSS_ATTR __attribute__((section(".ncbss"),nocommon))
#define NOCACHEDATA_ATTR __attribute__((section(".ncdata"),nocommon))
#if !defined(FORCE_SINGLE_CORE)
#define NUM_CORES 2
#define CURRENT_CORE current_core()
/* Use IRAM for variables shared across cores - large memory buffers should
* use UNCACHED_ADDR(a) and be appropriately aligned and padded */
#define NOCACHEBSS_ATTR IBSS_ATTR
#define NOCACHEDATA_ATTR IDATA_ATTR
/* Attributes for core-shared data in DRAM where IRAM is better used for other
* purposes. */
#define SHAREDBSS_ATTR NOCACHEBSS_ATTR
#define SHAREDDATA_ATTR NOCACHEDATA_ATTR
#define IF_COP(...) __VA_ARGS__
#define IF_COP_VOID(...) __VA_ARGS__
#define IF_COP_CORE(core) core
#if CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
#ifdef CPU_PP
#define CONFIG_CORELOCK SW_CORELOCK /* SWP(B) is broken */
#else
#define CONFIG_CORELOCK CORELOCK_SWAP
@ -500,9 +505,10 @@
#ifndef NUM_CORES
/* Default to single core */
#define NUM_CORES 1
#define CURRENT_CORE CPU
#define NOCACHEBSS_ATTR
#define NOCACHEDATA_ATTR
#define CURRENT_CORE CPU
/* Attributes for core-shared data in DRAM - no caching considerations */
#define SHAREDBSS_ATTR
#define SHAREDDATA_ATTR
#define CONFIG_CORELOCK CORELOCK_NONE
#define IF_COP(...)

4
firmware/kernel.c
View file

@ -49,7 +49,7 @@
#endif
#if !defined(CPU_PP) || !defined(BOOTLOADER)
volatile long current_tick NOCACHEDATA_ATTR = 0;
volatile long current_tick SHAREDDATA_ATTR = 0;
#endif
void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
@ -62,7 +62,7 @@ static struct
int count;
struct event_queue *queues[MAX_NUM_QUEUES];
IF_COP( struct corelock cl; )
} all_queues NOCACHEBSS_ATTR;
} all_queues SHAREDBSS_ATTR;
/****************************************************************************
* Standard kernel stuff

14
firmware/pcm.c
View file

@ -67,13 +67,13 @@
/* the registered callback function to ask for more mp3 data */
volatile pcm_more_callback_type pcm_callback_for_more
NOCACHEBSS_ATTR = NULL;
SHAREDBSS_ATTR = NULL;
/* PCM playback state */
volatile bool pcm_playing NOCACHEBSS_ATTR = false;
volatile bool pcm_playing SHAREDBSS_ATTR = false;
/* PCM paused state. paused implies playing */
volatile bool pcm_paused NOCACHEBSS_ATTR = false;
volatile bool pcm_paused SHAREDBSS_ATTR = false;
/* samplerate of currently playing audio - undefined if stopped */
unsigned long pcm_curr_sampr NOCACHEBSS_ATTR = 0;
unsigned long pcm_curr_sampr SHAREDBSS_ATTR = 0;
/**
* Do peak calculation using distance squared from axis and save a lot
@ -312,12 +312,12 @@ void pcm_mute(bool mute)
/** Low level pcm recording apis **/
/* Next start for recording peaks */
const volatile void *pcm_rec_peak_addr NOCACHEBSS_ATTR = NULL;
const volatile void *pcm_rec_peak_addr SHAREDBSS_ATTR = NULL;
/* the registered callback function for when more data is available */
volatile pcm_more_callback_type2
pcm_callback_more_ready NOCACHEBSS_ATTR = NULL;
pcm_callback_more_ready SHAREDBSS_ATTR = NULL;
/* DMA transfer in is currently active */
volatile bool pcm_recording NOCACHEBSS_ATTR = false;
volatile bool pcm_recording SHAREDBSS_ATTR = false;
/**
* Return recording peaks - From the end of the last peak up to

4
firmware/pcm_record.c
View file

@ -212,8 +212,8 @@ enum
/***************************************************************************/
static struct event_queue pcmrec_queue NOCACHEBSS_ATTR;
static struct queue_sender_list pcmrec_queue_send NOCACHEBSS_ATTR;
static struct event_queue pcmrec_queue SHAREDBSS_ATTR;
static struct queue_sender_list pcmrec_queue_send SHAREDBSS_ATTR;
static long pcmrec_stack[3*DEFAULT_STACK_SIZE/sizeof(long)];
static const char pcmrec_thread_name[] = "pcmrec";
static struct thread_entry *pcmrec_thread_p;

8
firmware/system.c
View file

@ -29,14 +29,14 @@
#include "string.h"
#ifndef SIMULATOR
long cpu_frequency NOCACHEBSS_ATTR = CPU_FREQ;
long cpu_frequency SHAREDBSS_ATTR = CPU_FREQ;
#endif
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
static int boost_counter NOCACHEBSS_ATTR = 0;
static bool cpu_idle NOCACHEBSS_ATTR = false;
static int boost_counter SHAREDBSS_ATTR = 0;
static bool cpu_idle SHAREDBSS_ATTR = false;
#if NUM_CORES > 1
struct spinlock boostctrl_spin NOCACHEBSS_ATTR;
struct spinlock boostctrl_spin SHAREDBSS_ATTR;
void cpu_boost_init(void)
{
spinlock_init(&boostctrl_spin);

2
firmware/target/arm/i2c-pp.c
View file

@ -33,7 +33,7 @@
#include "as3514.h"
/* Local functions definitions */
static struct mutex i2c_mtx NOCACHEBSS_ATTR;
static struct mutex i2c_mtx SHAREDBSS_ATTR;
#define POLL_TIMEOUT (HZ)

2
firmware/target/arm/ipod/1g2g/adc-ipod-1g2g.c
View file

@ -22,7 +22,7 @@
#include "hwcompat.h"
#include "kernel.h"
static struct mutex adc_mtx NOCACHEBSS_ATTR;
static struct mutex adc_mtx SHAREDBSS_ATTR;
/* used in the 2nd gen ADC interrupt */
static unsigned int_data;

56
firmware/target/arm/ipod/app.lds
View file

@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o)
#define IRAMORIG 0x40000000
#define IRAMSIZE 0xc000
#ifdef CPU_PP502x
#define NOCACHE_BASE 0x10000000
#else
#define NOCACHE_BASE 0x28000000
#endif
#define CACHEALIGN_SIZE 16
/* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@ -70,6 +78,18 @@ SECTIONS
_dataend = .;
} > DRAM
#if NOCACHE_BASE != 0
/* .ncdata section is placed at uncached physical alias address and is
* loaded at the proper cached virtual address - no copying is
* performed in the init code */
.ncdata . + NOCACHE_BASE :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncdata*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/DISCARD/ :
{
*(.eh_frame)
@ -103,7 +123,7 @@ SECTIONS
_iend = .;
} > IRAM
.idle_stacks :
.idle_stacks (NOLOAD) :
{
*(.idle_stacks)
#if NUM_CORES > 1
@ -116,7 +136,7 @@ SECTIONS
cop_idlestackend = .;
} > IRAM
.stack :
.stack (NOLOAD) :
{
*(.stack)
stackbegin = .;
@ -124,37 +144,53 @@ SECTIONS
stackend = .;
} > IRAM
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
/* .bss and .ncbss are treated as a single section to use one init loop to
* zero it - note "_edata" and "_end" */
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
{
_edata = .;
*(.bss*)
*(COMMON)
. = ALIGN(0x4);
_end = .;
} > DRAM
.audiobuf ALIGN(4) :
#if NOCACHE_BASE != 0
.ncbss . + NOCACHE_BASE (NOLOAD):
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/* This will be aligned by preceding alignments */
.endaddr . - NOCACHE_BASE (NOLOAD) :
{
_end = .;
} > DRAM
.audiobuf (NOLOAD) :
{
_audiobuffer = .;
audiobuffer = .;
} > DRAM
.audiobufend ENDAUDIOADDR:
.audiobufend ENDAUDIOADDR (NOLOAD) :
{
audiobufend = .;
_audiobufend = .;
} > DRAM
.codec ENDAUDIOADDR:
.codec ENDAUDIOADDR (NOLOAD) :
{
codecbuf = .;
_codecbuf = .;
}
.plugin ENDADDR:
.plugin ENDADDR (NOLOAD) :
{
_pluginbuf = .;
pluginbuf = .;
}
}

2
firmware/target/arm/ipod/boot.lds
View file

@ -43,6 +43,7 @@ SECTIONS
*(.irodata)
*(.idata)
*(.data*)
*(.ncdata*);
_dataend = . ;
}
@ -64,6 +65,7 @@ SECTIONS
_edata = .;
*(.bss*);
*(.ibss);
*(.ncbss*);
_end = .;
}
}

56
firmware/target/arm/iriver/app.lds
View file

@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o)
#define IRAMORIG 0x40000000
#define IRAMSIZE 0xc000
#ifdef CPU_PP502x
#define NOCACHE_BASE 0x10000000
#else
#define NOCACHE_BASE 0x28000000
#endif
#define CACHEALIGN_SIZE 16
/* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@ -70,6 +78,18 @@ SECTIONS
_dataend = .;
} > DRAM
#if NOCACHE_BASE != 0
/* .ncdata section is placed at uncached physical alias address and is
* loaded at the proper cached virtual address - no copying is
* performed in the init code */
.ncdata . + NOCACHE_BASE :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncdata*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/DISCARD/ :
{
*(.eh_frame)
@ -103,7 +123,7 @@ SECTIONS
_iend = .;
} > IRAM
.idle_stacks :
.idle_stacks (NOLOAD) :
{
*(.idle_stacks)
#if NUM_CORES > 1
@ -116,7 +136,7 @@ SECTIONS
cop_idlestackend = .;
} > IRAM
.stack :
.stack (NOLOAD) :
{
*(.stack)
stackbegin = .;
@ -124,37 +144,53 @@ SECTIONS
stackend = .;
} > IRAM
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
/* .bss and .ncbss are treated as a single section to use one init loop to
* zero it - note "_edata" and "_end" */
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
{
_edata = .;
*(.bss*)
*(COMMON)
. = ALIGN(0x4);
_end = .;
} > DRAM
.audiobuf ALIGN(4) :
#if NOCACHE_BASE != 0
.ncbss . + NOCACHE_BASE (NOLOAD):
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/* This will be aligned by preceding alignments */
.endaddr . - NOCACHE_BASE (NOLOAD) :
{
_end = .;
} > DRAM
.audiobuf (NOLOAD) :
{
_audiobuffer = .;
audiobuffer = .;
} > DRAM
.audiobufend ENDAUDIOADDR:
.audiobufend ENDAUDIOADDR (NOLOAD) :
{
audiobufend = .;
_audiobufend = .;
} > DRAM
.codec ENDAUDIOADDR:
.codec ENDAUDIOADDR (NOLOAD) :
{
codecbuf = .;
_codecbuf = .;
}
.plugin ENDADDR:
.plugin ENDADDR (NOLOAD) :
{
_pluginbuf = .;
pluginbuf = .;
}
}

2
firmware/target/arm/iriver/boot.lds
View file

@ -27,6 +27,7 @@ SECTIONS
*(.irodata)
*(.idata)
*(.data*)
*(.ncdata*);
_dataend = . ;
}
@ -48,6 +49,7 @@ SECTIONS
_edata = .;
*(.bss*);
*(.ibss);
*(.ncbss*);
_end = .;
}
}

2
firmware/target/arm/iriver/h10/lcd-h10_20gb.c
View file

@ -34,7 +34,7 @@ static unsigned short disp_control_rev;
/* Contrast setting << 8 */
static int lcd_contrast;
static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0;
static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0;
/* Forward declarations */
static void lcd_display_off(void);

56
firmware/target/arm/olympus/app.lds
View file

@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o)
#define IRAMORIG 0x40000000
#define IRAMSIZE 0xc000
#ifdef CPU_PP502x
#define NOCACHE_BASE 0x10000000
#else
#define NOCACHE_BASE 0x28000000
#endif
#define CACHEALIGN_SIZE 16
/* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@ -70,6 +78,18 @@ SECTIONS
_dataend = .;
} > DRAM
#if NOCACHE_BASE != 0
/* .ncdata section is placed at uncached physical alias address and is
* loaded at the proper cached virtual address - no copying is
* performed in the init code */
.ncdata . + NOCACHE_BASE :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncdata*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/DISCARD/ :
{
*(.eh_frame)
@ -103,7 +123,7 @@ SECTIONS
_iend = .;
} > IRAM
.idle_stacks :
.idle_stacks (NOLOAD) :
{
*(.idle_stacks)
#if NUM_CORES > 1
@ -116,7 +136,7 @@ SECTIONS
cop_idlestackend = .;
} > IRAM
.stack :
.stack (NOLOAD) :
{
*(.stack)
stackbegin = .;
@ -124,37 +144,53 @@ SECTIONS
stackend = .;
} > IRAM
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
/* .bss and .ncbss are treated as a single section to use one init loop to
* zero it - note "_edata" and "_end" */
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
{
_edata = .;
*(.bss*)
*(COMMON)
. = ALIGN(0x4);
_end = .;
} > DRAM
.audiobuf ALIGN(4) :
#if NOCACHE_BASE != 0
.ncbss . + NOCACHE_BASE (NOLOAD):
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/* This will be aligned by preceding alignments */
.endaddr . - NOCACHE_BASE (NOLOAD) :
{
_end = .;
} > DRAM
.audiobuf (NOLOAD) :
{
_audiobuffer = .;
audiobuffer = .;
} > DRAM
.audiobufend ENDAUDIOADDR:
.audiobufend ENDAUDIOADDR (NOLOAD) :
{
audiobufend = .;
_audiobufend = .;
} > DRAM
.codec ENDAUDIOADDR:
.codec ENDAUDIOADDR (NOLOAD) :
{
codecbuf = .;
_codecbuf = .;
}
.plugin ENDADDR:
.plugin ENDADDR (NOLOAD) :
{
_pluginbuf = .;
pluginbuf = .;
}
}

2
firmware/target/arm/olympus/boot.lds
View file

@ -27,6 +27,7 @@ SECTIONS
*(.irodata)
*(.idata)
*(.data*)
*(.ncdata*)
_dataend = . ;
}
@ -48,6 +49,7 @@ SECTIONS
_edata = .;
*(.bss*);
*(.ibss);
*(.ncbss*);
_end = .;
}
}

6
firmware/target/arm/pcm-pp.c
View file

@ -72,7 +72,7 @@ void fiq_handler(void)
/****************************************************************************
** Playback DMA transfer
**/
struct dma_data dma_play_data NOCACHEBSS_ATTR =
struct dma_data dma_play_data SHAREDBSS_ATTR =
{
/* Initialize to a locked, stopped state */
.p = NULL,
@ -84,7 +84,7 @@ struct dma_data dma_play_data NOCACHEBSS_ATTR =
.state = 0
};
static unsigned long pcm_freq NOCACHEDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
static unsigned long pcm_freq SHAREDDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
#ifdef HAVE_WM8751
/* Samplerate control for audio codec */
static int sr_ctrl = MROBE100_44100HZ;
@ -356,7 +356,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
**/
#ifdef HAVE_RECORDING
/* PCM recording interrupt routine lockout */
static struct dma_data dma_rec_data NOCACHEBSS_ATTR =
static struct dma_data dma_rec_data SHAREDBSS_ATTR =
{
/* Initialize to a locked, stopped state */
.p = NULL,

56
firmware/target/arm/sandisk/app.lds
View file

@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o)
#define IRAMORIG 0x40000000
#define IRAMSIZE 0xc000
#ifdef CPU_PP502x
#define NOCACHE_BASE 0x10000000
#else
#define NOCACHE_BASE 0x28000000
#endif
#define CACHEALIGN_SIZE 16
/* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@ -70,6 +78,18 @@ SECTIONS
_dataend = .;
} > DRAM
#if NOCACHE_BASE != 0
/* .ncdata section is placed at uncached physical alias address and is
* loaded at the proper cached virtual address - no copying is
* performed in the init code */
.ncdata . + NOCACHE_BASE :
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncdata*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/DISCARD/ :
{
*(.eh_frame)
@ -103,7 +123,7 @@ SECTIONS
_iend = .;
} > IRAM
.idle_stacks :
.idle_stacks (NOLOAD) :
{
*(.idle_stacks)
#if NUM_CORES > 1
@ -116,7 +136,7 @@ SECTIONS
cop_idlestackend = .;
} > IRAM
.stack :
.stack (NOLOAD) :
{
*(.stack)
stackbegin = .;
@ -124,37 +144,53 @@ SECTIONS
stackend = .;
} > IRAM
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
/* .bss and .ncbss are treated as a single section to use one init loop to
* zero it - note "_edata" and "_end" */
.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
{
_edata = .;
*(.bss*)
*(COMMON)
. = ALIGN(0x4);
_end = .;
} > DRAM
.audiobuf ALIGN(4) :
#if NOCACHE_BASE != 0
.ncbss . + NOCACHE_BASE (NOLOAD):
{
. = ALIGN(CACHEALIGN_SIZE);
*(.ncbss*)
. = ALIGN(CACHEALIGN_SIZE);
} AT> DRAM
#endif
/* This will be aligned by preceding alignments */
.endaddr . - NOCACHE_BASE (NOLOAD) :
{
_end = .;
} > DRAM
.audiobuf (NOLOAD) :
{
_audiobuffer = .;
audiobuffer = .;
} > DRAM
.audiobufend ENDAUDIOADDR:
.audiobufend ENDAUDIOADDR (NOLOAD) :
{
audiobufend = .;
_audiobufend = .;
} > DRAM
.codec ENDAUDIOADDR:
.codec ENDAUDIOADDR (NOLOAD) :
{
codecbuf = .;
_codecbuf = .;
}
.plugin ENDADDR:
.plugin ENDADDR (NOLOAD) :
{
_pluginbuf = .;
pluginbuf = .;
}
}

2
firmware/target/arm/sandisk/ata-c200_e200.c
View file

@ -165,7 +165,7 @@ static struct sd_card_status sd_status[NUM_VOLUMES] =
/* Shoot for around 75% usage */
static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x1c0)/sizeof(long)];
static const char sd_thread_name[] = "ata/sd";
static struct mutex sd_mtx NOCACHEBSS_ATTR;
static struct mutex sd_mtx SHAREDBSS_ATTR;
static struct event_queue sd_queue;
/* Posted when card plugged status has changed */

2
firmware/target/arm/sandisk/boot.lds
View file

@ -30,6 +30,7 @@ SECTIONS
*(.irodata)
*(.idata)
*(.data*)
*(.ncdata*)
_dataend = . ;
}
@ -51,6 +52,7 @@ SECTIONS
_edata = .;
*(.bss*);
*(.ibss);
*(.ncbss*);
_end = .;
}
}

2
firmware/target/arm/sandisk/sansa-c200/lcd-c200.c
View file

@ -23,7 +23,7 @@
#include "system.h"
/* Display status */
static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0;
static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0;
/* LCD command set for Samsung S6B33B2 */

4
firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
View file

@ -28,8 +28,8 @@
/* Power and display status */
static bool power_on = false; /* Is the power turned on? */
static bool display_on NOCACHEBSS_ATTR = false; /* Is the display turned on? */
static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0;
static bool display_on SHAREDBSS_ATTR = false; /* Is the display turned on? */
static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0;
/* Reverse Flag */
#define R_DISP_CONTROL_NORMAL 0x0004

2
firmware/target/arm/system-target.h
View file

@ -108,7 +108,7 @@ static inline unsigned int processor_id(void)
/* Certain data needs to be out of the way of cache line interference
* such as data for COP use or for use with UNCACHED_ADDR */
#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
/** cache functions **/
#ifndef BOOTLOADER

2
firmware/target/arm/tcc780x/ata-nand-tcc780x.c
View file

@ -42,7 +42,7 @@ static bool initialized = false;
static long next_yield = 0;
#define MIN_YIELD_PERIOD 2000
static struct mutex ata_mtx NOCACHEBSS_ATTR;
static struct mutex ata_mtx SHAREDBSS_ATTR;
#define SECTOR_SIZE 512

4
firmware/thread.c
View file

@ -235,7 +235,7 @@ extern uintptr_t cpu_idlestackbegin[];
extern uintptr_t cpu_idlestackend[];
extern uintptr_t cop_idlestackbegin[];
extern uintptr_t cop_idlestackend[];
static uintptr_t * const idle_stacks[NUM_CORES] NOCACHEDATA_ATTR =
static uintptr_t * const idle_stacks[NUM_CORES] =
{
[CPU] = cpu_idlestackbegin,
[COP] = cop_idlestackbegin
@ -251,7 +251,7 @@ struct core_semaphores
volatile uint8_t unused; /* 03h */
};
static struct core_semaphores core_semaphores[NUM_CORES] NOCACHEBSS_ATTR;
static struct core_semaphores core_semaphores[NUM_CORES] IBSS_ATTR;
#endif /* CONFIG_CPU == PP5002 */
#endif /* NUM_CORES */

6
firmware/timer.c
View file

@ -25,12 +25,12 @@
#include "logf.h"
static int timer_prio = -1;
void NOCACHEBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
void NOCACHEBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
#ifdef CPU_COLDFIRE
static int base_prescale;
#elif defined CPU_PP || CONFIG_CPU == PNX0101
static long NOCACHEBSS_ATTR cycles_new = 0;
static long SHAREDBSS_ATTR cycles_new = 0;
#endif
/* interrupt handler */