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s5l87xx: (Re)name the SHA-1 registers

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Synced with the s5l8702-sha1 Linux driver in the freemyipod fork

Change-Id: I5243346205f7883f4271d4b272936dd125adb496
This commit is contained in:
Vencislav Atanasov 2026-05-04 02:51:44 +03:00 • committed by Solomon Peachy
parent bbdada7690
commit 02638c1cb8
3 changed files with 43 additions and 31 deletions
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12
apps/plugins/crypt_firmware.c
View file

@ -103,18 +103,18 @@ static void aes_decrypt(void* data, uint32_t size)
static void calc_hash(uint32_t* data, uint32_t size, uint32_t* result)
{
uint32_t ptr, i;
uint32_t config = 2;
uint32_t config = SHA1_CONFIG_GO;
PWRCONEXT &= ~0x4;
for (ptr = 0; ptr < (size >> 2); ptr += 0x10)
{
for (i = 0; i < 0x10; i++) SHA1DATAIN[i] = data[ptr + i];
SHA1CONFIG = config;
config = 0xA;
while ((SHA1CONFIG & 1) != 0);
for (i = 0; i < 0x10; i++) SHA1_DATA[i] = data[ptr + i];
SHA1_CONFIG = config;
config = SHA1_CONFIG_CONT | SHA1_CONFIG_GO;
while ((SHA1_CONFIG & SHA1_CONFIG_BUSY) != 0);
}
for (i = 0; i < 5; i ++) result[i] = SHA1RESULT[i];
for (i = 0; i < 5; i ++) result[i] = SHA1_RESULT[i];
PWRCONEXT |= 0x4;
}

38
firmware/export/s5l87xx.h
View file

@ -26,9 +26,10 @@
#include <stdint.h>
#endif
#define REG16_PTR_T volatile uint16_t *
#define REG32_PTR_T volatile uint32_t *
#define VOID_PTR_PTR_T void* volatile*
#define REG_BIT(x) (1 << (x))
#define REG16_PTR_T volatile uint16_t *
#define REG32_PTR_T volatile uint32_t *
#define VOID_PTR_PTR_T void* volatile*
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
@ -1612,19 +1613,30 @@ Information for them was gathered solely by reverse-engineering Apple's firmware
#define SHA1_BASE 0x38000000
#endif
#define SHA1CONFIG (*((REG32_PTR_T)(SHA1_BASE)))
#define SHA1RESET (*((REG32_PTR_T)(SHA1_BASE + 0x04)))
#define SHA1_CONFIG (*((REG32_PTR_T)(SHA1_BASE)))
#define SHA1_SWRESET (*((REG32_PTR_T)(SHA1_BASE + 0x04)))
#define SHA1_INT_SRC (*((REG32_PTR_T)(SHA1_BASE + 0x08)))
#define SHA1_INT_MASK (*((REG32_PTR_T)(SHA1_BASE + 0x0C)))
#define SHA1_ENDIAN (*((REG32_PTR_T)(SHA1_BASE + 0x10)))
#if CONFIG_CPU == S5L8720
#define SHA1UNK10 (*((REG32_PTR_T)(SHA1_BASE + 0x10)))
#endif
// Result is 20 bytes (160 bits) 0x20-0x33
#define SHA1_RESULT ((REG32_PTR_T)(SHA1_BASE + 0x20))
#define SHA1RESULT ((REG32_PTR_T)(SHA1_BASE + 0x20))
#define SHA1DATAIN ((REG32_PTR_T)(SHA1_BASE + 0x40))
// Input is 64 bytes (512 bits) 0x40-0x7F
#define SHA1_DATA ((REG32_PTR_T)(SHA1_BASE + 0x40))
#if CONFIG_CPU == S5L8720
#define SHA1UNK80 (*((REG32_PTR_T)(SHA1_BASE + 0x80)))
#endif
#define SHA1_MASTER_MODE (*((REG32_PTR_T)(SHA1_BASE + 0x80)))
#define SHA1_MS_START_ADDR (*((REG32_PTR_T)(SHA1_BASE + 0x84)))
#define SHA1_VERSION (*((REG32_PTR_T)(SHA1_BASE + 0x88)))
#define SHA1_MS_SIZE (*((REG32_PTR_T)(SHA1_BASE + 0x8C)))
#define SHA1_FIFO_PARAM (*((REG32_PTR_T)(SHA1_BASE + 0x90)))
#define SHA1_FIFO_CMD (*((REG32_PTR_T)(SHA1_BASE + 0x94)))
#define SHA1_TX_FIFO_STAT (*((REG32_PTR_T)(SHA1_BASE + 0x98)))
#define SHA1_TX_FIFO (*((REG32_PTR_T)(SHA1_BASE + 0xA0)))
#define SHA1_CONFIG_BUSY REG_BIT(0)
#define SHA1_CONFIG_GO REG_BIT(1)
#define SHA1_CONFIG_CONT REG_BIT(3)
/* Clickwheel controller - S5L8701+ */
#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720

24
firmware/target/arm/s5l8702/crypto-s5l8702.c
View file

@ -64,13 +64,13 @@ void sha1(void* data, uint32_t size, void* hash)
uint32_t* databuf = (uint32_t*)data;
uint32_t* hashbuf = (uint32_t*)hash;
clockgate_enable(CLOCKGATE_SHA, true);
SHA1RESET = 1;
while (SHA1CONFIG & 1);
SHA1RESET = 0;
SHA1CONFIG = 0;
SHA1_SWRESET = 1;
while (SHA1_CONFIG & SHA1_CONFIG_BUSY);
SHA1_SWRESET = 0;
SHA1_CONFIG = 0;
#if CONFIG_CPU == S5L8720
SHA1UNK10 = 0;
SHA1UNK80 = 0;
SHA1_ENDIAN = 0; // little endian
SHA1_MASTER_MODE = 0; // slave mode
#endif
while (!done)
{
@ -93,15 +93,15 @@ void sha1(void* data, uint32_t size, void* hash)
tmp8[0x3f] = (size << 3) & 0xff;
done = true;
}
for (i = 0; i < 16; i++) SHA1DATAIN[i] = tmp32[i];
for (i = 0; i < 16; i++) SHA1_DATA[i] = tmp32[i];
}
else
for (i = 0; i < 16; i++) SHA1DATAIN[i] = *databuf++;
SHA1CONFIG |= 2;
while (SHA1CONFIG & 1);
SHA1CONFIG |= 8;
for (i = 0; i < 16; i++) SHA1_DATA[i] = *databuf++;
SHA1_CONFIG |= SHA1_CONFIG_GO;
while (SHA1_CONFIG & SHA1_CONFIG_BUSY);
SHA1_CONFIG |= SHA1_CONFIG_CONT;
}
for (i = 0; i < 5; i++) *hashbuf++ = SHA1RESULT[i];
for (i = 0; i < 5; i++) *hashbuf++ = SHA1_RESULT[i];
clockgate_enable(CLOCKGATE_SHA, false);
}