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ipodnano3g: enable the 2-CE Micron A5D5D52C NAND

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A contributor's check archive for a 2-chip-enable A5D5D52C unit matches
the row exactly and replays clean against the host FTL suite. The row
moves in with the validated chips on this evidence alone - no on-device
write test has been run.

Testing evidence: utils/ipodnano3g/RESULTS.md.

Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Change-Id: Ia9e00c0e880b10785da3ab52bc98dc93e94acfaf
This commit is contained in:
Andrew Rice 2026-09-19 07:52:53 +10:00
parent 9ee5873770
commit 01925dd5d0
2 changed files with 7 additions and 1 deletions
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5
utils/ipodnano3g/RESULTS.md
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@ -48,3 +48,8 @@ fault testing.
- **NAND check tool update, 2026-09-17.** The rebuilt check image reads a
4GB unit with no ECC failures or timeouts; two independent collections
from it agree byte for byte.
- **2-CE Micron A5D5D52C, enabled 2026-09-18.** A contributor's check
archive matches the table row exactly, including a derived `vflspares`
of 89. Replayed against the host suite: `test_ftl` agrees with the
oracle on all 1,982,464 sectors; `test_crash` survives 100 power cuts
(172 writes, 6 syncs, 0 sectors wrong). No on-device write test.