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imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
This commit is contained in:
Amaury Pouly
parent
97b9ade639
commit
017667c2dc
138 changed files with 41995 additions and 0 deletions
213
firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
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213
firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3700:3.2.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3700__PINCTRL__H__
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#define __HEADERGEN__STMP3700__PINCTRL__H__
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#define REGS_PINCTRL_BASE (0x80018000)
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#define REGS_PINCTRL_VERSION "3.2.0"
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/**
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* Register: HW_PINCTRL_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
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#define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
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#define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
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#define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
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#define BP_PINCTRL_CTRL_SFTRST 31
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#define BM_PINCTRL_CTRL_SFTRST 0x80000000
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#define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BP_PINCTRL_CTRL_CLKGATE 30
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#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
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#define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BP_PINCTRL_CTRL_PRESENT3 29
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#define BM_PINCTRL_CTRL_PRESENT3 0x20000000
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#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
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#define BP_PINCTRL_CTRL_PRESENT2 28
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#define BM_PINCTRL_CTRL_PRESENT2 0x10000000
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#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
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#define BP_PINCTRL_CTRL_PRESENT1 27
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#define BM_PINCTRL_CTRL_PRESENT1 0x8000000
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#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
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#define BP_PINCTRL_CTRL_PRESENT0 26
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#define BM_PINCTRL_CTRL_PRESENT0 0x4000000
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#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
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#define BP_PINCTRL_CTRL_IRQOUT3 3
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#define BM_PINCTRL_CTRL_IRQOUT3 0x8
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#define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8)
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#define BP_PINCTRL_CTRL_IRQOUT2 2
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#define BM_PINCTRL_CTRL_IRQOUT2 0x4
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#define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4)
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#define BP_PINCTRL_CTRL_IRQOUT1 1
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#define BM_PINCTRL_CTRL_IRQOUT1 0x2
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#define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2)
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#define BP_PINCTRL_CTRL_IRQOUT0 0
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#define BM_PINCTRL_CTRL_IRQOUT0 0x1
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#define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_PINCTRL_MUXSELn
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* Address: 0x100+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
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#define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
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#define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
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#define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
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#define BP_PINCTRL_MUXSELn_BITS 0
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#define BM_PINCTRL_MUXSELn_BITS 0xffffffff
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#define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_DRIVEn
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* Address: 0x200+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
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#define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
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#define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
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#define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
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#define BP_PINCTRL_DRIVEn_BITS 0
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#define BM_PINCTRL_DRIVEn_BITS 0xffffffff
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#define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_PULLn
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* Address: 0x300+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0))
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#define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4))
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#define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8))
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#define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc))
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#define BP_PINCTRL_PULLn_BITS 0
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#define BM_PINCTRL_PULLn_BITS 0xffffffff
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#define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_DOUTn
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* Address: 0x400+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
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#define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
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#define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
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#define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
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#define BP_PINCTRL_DOUTn_BITS 0
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#define BM_PINCTRL_DOUTn_BITS 0xffffffff
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#define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_DINn
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* Address: 0x500+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
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#define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
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#define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
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#define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
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#define BP_PINCTRL_DINn_BITS 0
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#define BM_PINCTRL_DINn_BITS 0xffffffff
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#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_DOEn
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* Address: 0x600+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
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#define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
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#define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
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#define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
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#define BP_PINCTRL_DOEn_BITS 0
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#define BM_PINCTRL_DOEn_BITS 0xffffffff
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#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_PIN2IRQn
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* Address: 0x700+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
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#define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
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#define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
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#define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
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#define BP_PINCTRL_PIN2IRQn_BITS 0
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#define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff
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#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_IRQENn
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* Address: 0x800+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
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#define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
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#define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
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#define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
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#define BP_PINCTRL_IRQENn_BITS 0
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#define BM_PINCTRL_IRQENn_BITS 0xffffffff
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#define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_IRQLEVELn
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* Address: 0x900+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
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#define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
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#define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
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#define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
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#define BP_PINCTRL_IRQLEVELn_BITS 0
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#define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff
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#define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_IRQPOLn
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* Address: 0xa00+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
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#define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
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#define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
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#define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
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#define BP_PINCTRL_IRQPOLn_BITS 0
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#define BM_PINCTRL_IRQPOLn_BITS 0xffffffff
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#define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_PINCTRL_IRQSTATn
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* Address: 0xb00+n*0x10
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* SCT: yes
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*/
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#define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
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#define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
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#define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
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#define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
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#define BP_PINCTRL_IRQSTATn_BITS 0
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#define BM_PINCTRL_IRQSTATn_BITS 0xffffffff
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#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
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#endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */
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