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iPod Classic: add non-cached memory region

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Configures uncached memory region and adds some defines for misc HW,
for compability with the bootloader and other future use, current
functionality should not be affected.

Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
This commit is contained in:
Cástor Muñoz 2015-12-17 02:37:18 +01:00
parent 348bfc5c8f
commit 00bda90a21
4 changed files with 95 additions and 66 deletions
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45
firmware/export/s5l8702.h
View file

@ -31,13 +31,13 @@
#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ #define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
#define DRAM_ORIG 0x08000000 #define DRAM_ORIG 0x08000000
#define IRAM_ORIG 0 #define IRAM_ORIG 0x22000000
#define DRAM_SIZE (MEMORYSIZE * 0x100000) #define DRAM_SIZE (MEMORYSIZE * 0x100000)
#define IRAM_SIZE 0x40000 #define IRAM_SIZE 0x40000
#define TTB_SIZE 0x4000 #define TTB_SIZE 0x4000
#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE) #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
#define IRAM0_ORIG 0x22000000 #define IRAM0_ORIG 0x22000000
#define IRAM0_SIZE 0x20000 #define IRAM0_SIZE 0x20000
@ -66,6 +66,29 @@
((i) == 2 ? 0x58 : \ ((i) == 2 ? 0x58 : \
((i) == 1 ? 0x4C : \ ((i) == 1 ? 0x4C : \
0x48))))))) 0x48)))))))
/* SW Reset Control Register */
#define SWRCON (*((volatile uint32_t*)(0x3C500050)))
/* Reset Status Register */
#define RSTSR (*((volatile uint32_t*)(0x3C500054)))
#define RSTSR_WDR_BIT (1 << 2)
#define RSTSR_SWR_BIT (1 << 1)
#define RSTSR_HWR_BIT (1 << 0)
/////WATCHDOG/////
#define WDTCON (*((volatile uint32_t*)(0x3C800000)))
#define WDTCNT (*((volatile uint32_t*)(0x3C800004)))
/////MEMCONTROLLER/////
#define MIU_BASE (0x38100000)
#define MIU_REG(off) (*((uint32_t volatile*)(MIU_BASE + (off))))
/* following registers are similar to s5l8700x */
#define MIUCON (*((uint32_t volatile*)(0x38100000)))
#define MIUCOM (*((uint32_t volatile*)(0x38100004)))
#define MIUAREF (*((uint32_t volatile*)(0x38100008)))
#define MIUMRS (*((uint32_t volatile*)(0x3810000C)))
#define MIUSDPARA (*((uint32_t volatile*)(0x38100010)))
/////TIMER///// /////TIMER/////
@ -160,10 +183,13 @@
#define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ #define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \
CLOCKGATE_I2C0) CLOCKGATE_I2C0)
#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus)))) #define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus)))) #define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus)))) #define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus)))) #define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
#define IICUNK10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus))))
#define IICUNK14(bus) (*((uint32_t volatile*)(0x3C600014 + 0x300000 * (bus))))
#define IICUNK18(bus) (*((uint32_t volatile*)(0x3C600018 + 0x300000 * (bus))))
/////INTERRUPT CONTROLLERS///// /////INTERRUPT CONTROLLERS/////
@ -344,6 +370,7 @@
#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5)))) #define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5)))) #define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5)))) #define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
#define PUNC(i) (*((uint32_t volatile*)(0x3cf00010 + ((i) << 5))))
#define PCON0 (*((uint32_t volatile*)(0x3cf00000))) #define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
#define PDAT0 (*((uint32_t volatile*)(0x3cf00004))) #define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
#define PCON1 (*((uint32_t volatile*)(0x3cf00020))) #define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
@ -392,12 +419,12 @@
#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i)))) #define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4))) #define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8))) #define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc))) #define SPIPIN(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10))) #define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20))) #define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30))) #define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34))) #define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) #define SPIDD(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) /* TBC */
/////AES///// /////AES/////

92
firmware/target/arm/s5l8702/crt0.S
View file

@ -23,9 +23,6 @@
#include "config.h" #include "config.h"
#include "cpu.h" #include "cpu.h"
#define CACHE_NONE 0
#define CACHE_ALL 0x0C
.section .intvect,"ax",%progbits .section .intvect,"ax",%progbits
.global start .global start
.global _newstart .global _newstart
@ -50,65 +47,48 @@ newstart2:
#ifdef BOOTLOADER #ifdef BOOTLOADER
/* Relocate ourself to IRAM - we have been loaded to DRAM */ /* Relocate ourself to IRAM - we have been loaded to DRAM */
mov r0, #0x08000000 /* source (DRAM) */ mov r0, #0x08000000 /* source (DRAM) */
mov r1, #0x22000000 /* dest (IRAM) */ mov r1, #0x22000000 /* dest (IRAM) */
ldr r2, =_dataend ldr r2, =_dataend
1: 1:
cmp r2, r1 cmp r2, r1
ldrhi r3, [r0], #4 ldrhi r3, [r0], #4
strhi r3, [r1], #4 strhi r3, [r1], #4
bhi 1b bhi 1b
ldr pc, =start_loc /* jump to the relocated start_loc: */ ldr pc, =start_loc /* jump to the relocated start_loc: */
start_loc: start_loc:
#endif #endif
mrc 15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000 bic r0, r0, #0x1000
bic r0, r0, #0x5 bic r0, r0, #0x5
mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
.cleancache: .cleancache:
mrc p15, 0, r15,c7,c10,3 mrc p15, 0, r15,c7,c10,3
bne .cleancache bne .cleancache
mov r0, #0 mov r0, #0
mcr p15, 0, r0,c7,c10,4 mcr p15, 0, r0,c7,c10,4
mcr p15, 0, r0,c7,c5,0 mcr p15, 0, r0,c7,c5,0
bl ttb_init
mov r0, #0 @ physical address /* reset VIC controller */
mov r1, #0 @ virtual address ldr r1, =0x38e00000
mov r2, #0x380 @ size (all memory) add r2, r1, #0x00001000
mov r3, #CACHE_ALL add r3, r1, #0x00002000
bl map_section sub r4, r0, #1
str r4, [r1,#0x14]
str r4, [r2,#0x14]
str r4, [r1,#0xf00]
str r4, [r2,#0xf00]
str r4, [r3,#0x08]
str r4, [r3,#0x0c]
str r0, [r1,#0x14]
str r0, [r2,#0x14]
mov r0, #0x38000000 @ physical address
mov r1, #0x38000000 @ virtual address
mov r2, #0x80 @ size (AHB/APB)
mov r3, #CACHE_NONE
bl map_section
bl enable_mmu
mrc 15, 0, r0, c1, c0, 0
orr r0, r0, #0x5
orr r0, r0, #0x1000
mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
ldr r1, =0x38e00000
add r2, r1, #0x00001000
add r3, r1, #0x00002000
sub r4, r0, #1
str r4, [r1,#0x14]
str r4, [r2,#0x14]
str r4, [r1,#0xf00]
str r4, [r2,#0xf00]
str r4, [r3,#0x08]
str r4, [r3,#0x0c]
str r0, [r1,#0x14]
str r0, [r2,#0x14]
#if !defined(BOOTLOADER) #if !defined(BOOTLOADER)
bl memory_init
/* Copy interrupt vectors to iram */ /* Copy interrupt vectors to iram */
ldr r2, =_intvectstart ldr r2, =_intvectstart
ldr r3, =_intvectend ldr r3, =_intvectend
@ -139,7 +119,7 @@ start_loc:
ldrhi r1, [r4], #4 ldrhi r1, [r4], #4
strhi r1, [r2], #4 strhi r1, [r2], #4
bhi 1b bhi 1b
/* Initialise ibss section to zero */ /* Initialise ibss section to zero */
ldr r2, =_iedata ldr r2, =_iedata
ldr r3, =_iend ldr r3, =_iend
@ -150,11 +130,11 @@ start_loc:
bhi 1b bhi 1b
#endif #endif
/* Set up stack for IRQ mode */ /* Set up stack for IRQ mode */
msr cpsr_c, #0xd2 msr cpsr_c, #0xd2
ldr sp, =_irqstackend ldr sp, =_irqstackend
/* Set up stack for FIQ mode */ /* Set up stack for FIQ mode */
msr cpsr_c, #0xd1 msr cpsr_c, #0xd1
ldr sp, =_fiqstackend ldr sp, =_fiqstackend
@ -178,4 +158,4 @@ start_loc:
strhi r3, [r2], #4 strhi r3, [r2], #4
bhi 1b bhi 1b
bl main b main

21
firmware/target/arm/s5l8702/system-s5l8702.c
View file

@ -168,7 +168,7 @@ void irq_handler(void)
irqvector[current_irq](); irqvector[current_irq]();
VIC0ADDRESS = NULL; VIC0ADDRESS = NULL;
VIC1ADDRESS = NULL; VIC1ADDRESS = NULL;
asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
"subs pc, lr, #4 \n"); /* Return from IRQ */ "subs pc, lr, #4 \n"); /* Return from IRQ */
@ -258,3 +258,22 @@ void set_cpu_frequency(long frequency)
cpu_frequency = frequency; cpu_frequency = frequency;
} }
#endif #endif
static void set_page_tables(void)
{
/* map RAM to itself and enable caching for it */
map_section(0, 0, 0x380, CACHE_ALL);
/* disable caching for I/O area */
map_section(0x38000000, 0x38000000, 0x80, CACHE_NONE);
/* map RAM uncached addresses */
map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE);
}
void memory_init(void)
{
ttb_init();
set_page_tables();
enable_mmu();
}

3
firmware/target/arm/s5l8702/system-target.h
View file

@ -31,6 +31,9 @@
#define STORAGE_WANTS_ALIGN #define STORAGE_WANTS_ALIGN
#define S5L8702_UNCACHED_ADDR(a) ((typeof(a)) ((uintptr_t)(a) + 0x40000000))
#define S5L8702_PHYSICAL_ADDR(a) ((typeof(a)) ((uintptr_t)(a)))
#define inl(a) (*(volatile unsigned long *) (a)) #define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a)) #define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a)) #define inb(a) (*(volatile unsigned char *) (a))