len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2025-12-08 12:45:26 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions

iPod Classic: add non-cached memory region

Browse source 
Configures uncached memory region and adds some defines for misc HW,
for compability with the bootloader and other future use, current
functionality should not be affected.

Change-Id: I390e79bea1aef5b10dfbc72ad327d7fe438ec6f5
This commit is contained in:
Cástor Muñoz 2015-12-17 02:37:18 +01:00
parent 348bfc5c8f
commit 00bda90a21
4 changed files with 95 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

92
firmware/target/arm/s5l8702/crt0.S
View file

@ -23,9 +23,6 @@
#include "config.h"
#include "cpu.h"
#define CACHE_NONE 0
#define CACHE_ALL 0x0C
.section .intvect,"ax",%progbits
.global start
.global _newstart
@ -50,65 +47,48 @@ newstart2:
#ifdef BOOTLOADER
/* Relocate ourself to IRAM - we have been loaded to DRAM */
mov r0, #0x08000000 /* source (DRAM) */
mov r1, #0x22000000 /* dest (IRAM) */
ldr r2, =_dataend
mov r0, #0x08000000 /* source (DRAM) */
mov r1, #0x22000000 /* dest (IRAM) */
ldr r2, =_dataend
1:
cmp r2, r1
ldrhi r3, [r0], #4
strhi r3, [r1], #4
bhi 1b
cmp r2, r1
ldrhi r3, [r0], #4
strhi r3, [r1], #4
bhi 1b
ldr pc, =start_loc /* jump to the relocated start_loc: */
ldr pc, =start_loc /* jump to the relocated start_loc: */
start_loc:
#endif
mrc 15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000
bic r0, r0, #0x5
mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000
bic r0, r0, #0x5
mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
.cleancache:
mrc p15, 0, r15,c7,c10,3
bne .cleancache
mov r0, #0
mcr p15, 0, r0,c7,c10,4
mcr p15, 0, r0,c7,c5,0
bl ttb_init
mrc p15, 0, r15,c7,c10,3
bne .cleancache
mov r0, #0
mcr p15, 0, r0,c7,c10,4
mcr p15, 0, r0,c7,c5,0
mov r0, #0 @ physical address
mov r1, #0 @ virtual address
mov r2, #0x380 @ size (all memory)
mov r3, #CACHE_ALL
bl map_section
/* reset VIC controller */
ldr r1, =0x38e00000
add r2, r1, #0x00001000
add r3, r1, #0x00002000
sub r4, r0, #1
str r4, [r1,#0x14]
str r4, [r2,#0x14]
str r4, [r1,#0xf00]
str r4, [r2,#0xf00]
str r4, [r3,#0x08]
str r4, [r3,#0x0c]
str r0, [r1,#0x14]
str r0, [r2,#0x14]
mov r0, #0x38000000 @ physical address
mov r1, #0x38000000 @ virtual address
mov r2, #0x80 @ size (AHB/APB)
mov r3, #CACHE_NONE
bl map_section
bl enable_mmu
mrc 15, 0, r0, c1, c0, 0
orr r0, r0, #0x5
orr r0, r0, #0x1000
mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
ldr r1, =0x38e00000
add r2, r1, #0x00001000
add r3, r1, #0x00002000
sub r4, r0, #1
str r4, [r1,#0x14]
str r4, [r2,#0x14]
str r4, [r1,#0xf00]
str r4, [r2,#0xf00]
str r4, [r3,#0x08]
str r4, [r3,#0x0c]
str r0, [r1,#0x14]
str r0, [r2,#0x14]
#if !defined(BOOTLOADER)
bl memory_init
/* Copy interrupt vectors to iram */
ldr r2, =_intvectstart
ldr r3, =_intvectend
@ -139,7 +119,7 @@ start_loc:
ldrhi r1, [r4], #4
strhi r1, [r2], #4
bhi 1b
/* Initialise ibss section to zero */
ldr r2, =_iedata
ldr r3, =_iend
@ -150,11 +130,11 @@ start_loc:
bhi 1b
#endif
/* Set up stack for IRQ mode */
/* Set up stack for IRQ mode */
msr cpsr_c, #0xd2
ldr sp, =_irqstackend
/* Set up stack for FIQ mode */
/* Set up stack for FIQ mode */
msr cpsr_c, #0xd1
ldr sp, =_fiqstackend
@ -178,4 +158,4 @@ start_loc:
strhi r3, [r2], #4
bhi 1b
bl main
b main

21
firmware/target/arm/s5l8702/system-s5l8702.c
View file

@ -168,7 +168,7 @@ void irq_handler(void)
irqvector[current_irq]();
VIC0ADDRESS = NULL;
VIC1ADDRESS = NULL;
asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
"subs pc, lr, #4 \n"); /* Return from IRQ */
@ -258,3 +258,22 @@ void set_cpu_frequency(long frequency)
cpu_frequency = frequency;
}
#endif
static void set_page_tables(void)
{
/* map RAM to itself and enable caching for it */
map_section(0, 0, 0x380, CACHE_ALL);
/* disable caching for I/O area */
map_section(0x38000000, 0x38000000, 0x80, CACHE_NONE);
/* map RAM uncached addresses */
map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE);
}
void memory_init(void)
{
ttb_init();
set_page_tables();
enable_mmu();
}

3
firmware/target/arm/s5l8702/system-target.h
View file

@ -31,6 +31,9 @@
#define STORAGE_WANTS_ALIGN
#define S5L8702_UNCACHED_ADDR(a) ((typeof(a)) ((uintptr_t)(a) + 0x40000000))
#define S5L8702_PHYSICAL_ADDR(a) ((typeof(a)) ((uintptr_t)(a)))
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a))