/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * x1000 version: 1.0
 * x1000 authors: Aidan MacDonald
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_CPM_H__
#define __HEADERGEN_CPM_H__

#include "macro.h"

#define REG_CPM_CCR                     jz_reg(CPM_CCR)
#define JA_CPM_CCR                      (0xb0000000 + 0x0)
#define JT_CPM_CCR                      JIO_32_RW
#define JN_CPM_CCR                      CPM_CCR
#define JI_CPM_CCR                      
#define BP_CPM_CCR_SEL_SRC              30
#define BM_CPM_CCR_SEL_SRC              0xc0000000
#define BV_CPM_CCR_SEL_SRC__STOP        0x0
#define BV_CPM_CCR_SEL_SRC__EXCLK       0x1
#define BV_CPM_CCR_SEL_SRC__APLL        0x2
#define BF_CPM_CCR_SEL_SRC(v)           (((v) & 0x3) << 30)
#define BFM_CPM_CCR_SEL_SRC(v)          BM_CPM_CCR_SEL_SRC
#define BF_CPM_CCR_SEL_SRC_V(e)         BF_CPM_CCR_SEL_SRC(BV_CPM_CCR_SEL_SRC__##e)
#define BFM_CPM_CCR_SEL_SRC_V(v)        BM_CPM_CCR_SEL_SRC
#define BP_CPM_CCR_SEL_CPLL             28
#define BM_CPM_CCR_SEL_CPLL             0x30000000
#define BV_CPM_CCR_SEL_CPLL__STOP       0x0
#define BV_CPM_CCR_SEL_CPLL__SCLK_A     0x1
#define BV_CPM_CCR_SEL_CPLL__MPLL       0x2
#define BF_CPM_CCR_SEL_CPLL(v)          (((v) & 0x3) << 28)
#define BFM_CPM_CCR_SEL_CPLL(v)         BM_CPM_CCR_SEL_CPLL
#define BF_CPM_CCR_SEL_CPLL_V(e)        BF_CPM_CCR_SEL_CPLL(BV_CPM_CCR_SEL_CPLL__##e)
#define BFM_CPM_CCR_SEL_CPLL_V(v)       BM_CPM_CCR_SEL_CPLL
#define BP_CPM_CCR_SEL_H0PLL            26
#define BM_CPM_CCR_SEL_H0PLL            0xc000000
#define BV_CPM_CCR_SEL_H0PLL__STOP      0x0
#define BV_CPM_CCR_SEL_H0PLL__SCLK_A    0x1
#define BV_CPM_CCR_SEL_H0PLL__MPLL      0x2
#define BF_CPM_CCR_SEL_H0PLL(v)         (((v) & 0x3) << 26)
#define BFM_CPM_CCR_SEL_H0PLL(v)        BM_CPM_CCR_SEL_H0PLL
#define BF_CPM_CCR_SEL_H0PLL_V(e)       BF_CPM_CCR_SEL_H0PLL(BV_CPM_CCR_SEL_H0PLL__##e)
#define BFM_CPM_CCR_SEL_H0PLL_V(v)      BM_CPM_CCR_SEL_H0PLL
#define BP_CPM_CCR_SEL_H2PLL            24
#define BM_CPM_CCR_SEL_H2PLL            0x3000000
#define BV_CPM_CCR_SEL_H2PLL__STOP      0x0
#define BV_CPM_CCR_SEL_H2PLL__SCLK_A    0x1
#define BV_CPM_CCR_SEL_H2PLL__MPLL      0x2
#define BF_CPM_CCR_SEL_H2PLL(v)         (((v) & 0x3) << 24)
#define BFM_CPM_CCR_SEL_H2PLL(v)        BM_CPM_CCR_SEL_H2PLL
#define BF_CPM_CCR_SEL_H2PLL_V(e)       BF_CPM_CCR_SEL_H2PLL(BV_CPM_CCR_SEL_H2PLL__##e)
#define BFM_CPM_CCR_SEL_H2PLL_V(v)      BM_CPM_CCR_SEL_H2PLL
#define BP_CPM_CCR_PDIV                 16
#define BM_CPM_CCR_PDIV                 0xf0000
#define BF_CPM_CCR_PDIV(v)              (((v) & 0xf) << 16)
#define BFM_CPM_CCR_PDIV(v)             BM_CPM_CCR_PDIV
#define BF_CPM_CCR_PDIV_V(e)            BF_CPM_CCR_PDIV(BV_CPM_CCR_PDIV__##e)
#define BFM_CPM_CCR_PDIV_V(v)           BM_CPM_CCR_PDIV
#define BP_CPM_CCR_H2DIV                12
#define BM_CPM_CCR_H2DIV                0xf000
#define BF_CPM_CCR_H2DIV(v)             (((v) & 0xf) << 12)
#define BFM_CPM_CCR_H2DIV(v)            BM_CPM_CCR_H2DIV
#define BF_CPM_CCR_H2DIV_V(e)           BF_CPM_CCR_H2DIV(BV_CPM_CCR_H2DIV__##e)
#define BFM_CPM_CCR_H2DIV_V(v)          BM_CPM_CCR_H2DIV
#define BP_CPM_CCR_H0DIV                8
#define BM_CPM_CCR_H0DIV                0xf00
#define BF_CPM_CCR_H0DIV(v)             (((v) & 0xf) << 8)
#define BFM_CPM_CCR_H0DIV(v)            BM_CPM_CCR_H0DIV
#define BF_CPM_CCR_H0DIV_V(e)           BF_CPM_CCR_H0DIV(BV_CPM_CCR_H0DIV__##e)
#define BFM_CPM_CCR_H0DIV_V(v)          BM_CPM_CCR_H0DIV
#define BP_CPM_CCR_L2DIV                4
#define BM_CPM_CCR_L2DIV                0xf0
#define BF_CPM_CCR_L2DIV(v)             (((v) & 0xf) << 4)
#define BFM_CPM_CCR_L2DIV(v)            BM_CPM_CCR_L2DIV
#define BF_CPM_CCR_L2DIV_V(e)           BF_CPM_CCR_L2DIV(BV_CPM_CCR_L2DIV__##e)
#define BFM_CPM_CCR_L2DIV_V(v)          BM_CPM_CCR_L2DIV
#define BP_CPM_CCR_CDIV                 0
#define BM_CPM_CCR_CDIV                 0xf
#define BF_CPM_CCR_CDIV(v)              (((v) & 0xf) << 0)
#define BFM_CPM_CCR_CDIV(v)             BM_CPM_CCR_CDIV
#define BF_CPM_CCR_CDIV_V(e)            BF_CPM_CCR_CDIV(BV_CPM_CCR_CDIV__##e)
#define BFM_CPM_CCR_CDIV_V(v)           BM_CPM_CCR_CDIV
#define BP_CPM_CCR_GATE_SCLKA           23
#define BM_CPM_CCR_GATE_SCLKA           0x800000
#define BF_CPM_CCR_GATE_SCLKA(v)        (((v) & 0x1) << 23)
#define BFM_CPM_CCR_GATE_SCLKA(v)       BM_CPM_CCR_GATE_SCLKA
#define BF_CPM_CCR_GATE_SCLKA_V(e)      BF_CPM_CCR_GATE_SCLKA(BV_CPM_CCR_GATE_SCLKA__##e)
#define BFM_CPM_CCR_GATE_SCLKA_V(v)     BM_CPM_CCR_GATE_SCLKA
#define BP_CPM_CCR_CE_CPU               22
#define BM_CPM_CCR_CE_CPU               0x400000
#define BF_CPM_CCR_CE_CPU(v)            (((v) & 0x1) << 22)
#define BFM_CPM_CCR_CE_CPU(v)           BM_CPM_CCR_CE_CPU
#define BF_CPM_CCR_CE_CPU_V(e)          BF_CPM_CCR_CE_CPU(BV_CPM_CCR_CE_CPU__##e)
#define BFM_CPM_CCR_CE_CPU_V(v)         BM_CPM_CCR_CE_CPU
#define BP_CPM_CCR_CE_AHB0              21
#define BM_CPM_CCR_CE_AHB0              0x200000
#define BF_CPM_CCR_CE_AHB0(v)           (((v) & 0x1) << 21)
#define BFM_CPM_CCR_CE_AHB0(v)          BM_CPM_CCR_CE_AHB0
#define BF_CPM_CCR_CE_AHB0_V(e)         BF_CPM_CCR_CE_AHB0(BV_CPM_CCR_CE_AHB0__##e)
#define BFM_CPM_CCR_CE_AHB0_V(v)        BM_CPM_CCR_CE_AHB0
#define BP_CPM_CCR_CE_AHB2              20
#define BM_CPM_CCR_CE_AHB2              0x100000
#define BF_CPM_CCR_CE_AHB2(v)           (((v) & 0x1) << 20)
#define BFM_CPM_CCR_CE_AHB2(v)          BM_CPM_CCR_CE_AHB2
#define BF_CPM_CCR_CE_AHB2_V(e)         BF_CPM_CCR_CE_AHB2(BV_CPM_CCR_CE_AHB2__##e)
#define BFM_CPM_CCR_CE_AHB2_V(v)        BM_CPM_CCR_CE_AHB2

#define REG_CPM_CSR                 jz_reg(CPM_CSR)
#define JA_CPM_CSR                  (0xb0000000 + 0xd4)
#define JT_CPM_CSR                  JIO_32_RW
#define JN_CPM_CSR                  CPM_CSR
#define JI_CPM_CSR                  
#define BP_CPM_CSR_SRC_MUX          31
#define BM_CPM_CSR_SRC_MUX          0x80000000
#define BF_CPM_CSR_SRC_MUX(v)       (((v) & 0x1) << 31)
#define BFM_CPM_CSR_SRC_MUX(v)      BM_CPM_CSR_SRC_MUX
#define BF_CPM_CSR_SRC_MUX_V(e)     BF_CPM_CSR_SRC_MUX(BV_CPM_CSR_SRC_MUX__##e)
#define BFM_CPM_CSR_SRC_MUX_V(v)    BM_CPM_CSR_SRC_MUX
#define BP_CPM_CSR_CPU_MUX          30
#define BM_CPM_CSR_CPU_MUX          0x40000000
#define BF_CPM_CSR_CPU_MUX(v)       (((v) & 0x1) << 30)
#define BFM_CPM_CSR_CPU_MUX(v)      BM_CPM_CSR_CPU_MUX
#define BF_CPM_CSR_CPU_MUX_V(e)     BF_CPM_CSR_CPU_MUX(BV_CPM_CSR_CPU_MUX__##e)
#define BFM_CPM_CSR_CPU_MUX_V(v)    BM_CPM_CSR_CPU_MUX
#define BP_CPM_CSR_AHB0_MUX         29
#define BM_CPM_CSR_AHB0_MUX         0x20000000
#define BF_CPM_CSR_AHB0_MUX(v)      (((v) & 0x1) << 29)
#define BFM_CPM_CSR_AHB0_MUX(v)     BM_CPM_CSR_AHB0_MUX
#define BF_CPM_CSR_AHB0_MUX_V(e)    BF_CPM_CSR_AHB0_MUX(BV_CPM_CSR_AHB0_MUX__##e)
#define BFM_CPM_CSR_AHB0_MUX_V(v)   BM_CPM_CSR_AHB0_MUX
#define BP_CPM_CSR_AHB2_MUX         28
#define BM_CPM_CSR_AHB2_MUX         0x10000000
#define BF_CPM_CSR_AHB2_MUX(v)      (((v) & 0x1) << 28)
#define BFM_CPM_CSR_AHB2_MUX(v)     BM_CPM_CSR_AHB2_MUX
#define BF_CPM_CSR_AHB2_MUX_V(e)    BF_CPM_CSR_AHB2_MUX(BV_CPM_CSR_AHB2_MUX__##e)
#define BFM_CPM_CSR_AHB2_MUX_V(v)   BM_CPM_CSR_AHB2_MUX
#define BP_CPM_CSR_DDR_MUX          27
#define BM_CPM_CSR_DDR_MUX          0x8000000
#define BF_CPM_CSR_DDR_MUX(v)       (((v) & 0x1) << 27)
#define BFM_CPM_CSR_DDR_MUX(v)      BM_CPM_CSR_DDR_MUX
#define BF_CPM_CSR_DDR_MUX_V(e)     BF_CPM_CSR_DDR_MUX(BV_CPM_CSR_DDR_MUX__##e)
#define BFM_CPM_CSR_DDR_MUX_V(v)    BM_CPM_CSR_DDR_MUX
#define BP_CPM_CSR_H2DIV_BUSY       2
#define BM_CPM_CSR_H2DIV_BUSY       0x4
#define BF_CPM_CSR_H2DIV_BUSY(v)    (((v) & 0x1) << 2)
#define BFM_CPM_CSR_H2DIV_BUSY(v)   BM_CPM_CSR_H2DIV_BUSY
#define BF_CPM_CSR_H2DIV_BUSY_V(e)  BF_CPM_CSR_H2DIV_BUSY(BV_CPM_CSR_H2DIV_BUSY__##e)
#define BFM_CPM_CSR_H2DIV_BUSY_V(v) BM_CPM_CSR_H2DIV_BUSY
#define BP_CPM_CSR_H0DIV_BUSY       1
#define BM_CPM_CSR_H0DIV_BUSY       0x2
#define BF_CPM_CSR_H0DIV_BUSY(v)    (((v) & 0x1) << 1)
#define BFM_CPM_CSR_H0DIV_BUSY(v)   BM_CPM_CSR_H0DIV_BUSY
#define BF_CPM_CSR_H0DIV_BUSY_V(e)  BF_CPM_CSR_H0DIV_BUSY(BV_CPM_CSR_H0DIV_BUSY__##e)
#define BFM_CPM_CSR_H0DIV_BUSY_V(v) BM_CPM_CSR_H0DIV_BUSY
#define BP_CPM_CSR_CDIV_BUSY        0
#define BM_CPM_CSR_CDIV_BUSY        0x1
#define BF_CPM_CSR_CDIV_BUSY(v)     (((v) & 0x1) << 0)
#define BFM_CPM_CSR_CDIV_BUSY(v)    BM_CPM_CSR_CDIV_BUSY
#define BF_CPM_CSR_CDIV_BUSY_V(e)   BF_CPM_CSR_CDIV_BUSY(BV_CPM_CSR_CDIV_BUSY__##e)
#define BFM_CPM_CSR_CDIV_BUSY_V(v)  BM_CPM_CSR_CDIV_BUSY

#define REG_CPM_DDRCDR                  jz_reg(CPM_DDRCDR)
#define JA_CPM_DDRCDR                   (0xb0000000 + 0x2c)
#define JT_CPM_DDRCDR                   JIO_32_RW
#define JN_CPM_DDRCDR                   CPM_DDRCDR
#define JI_CPM_DDRCDR                   
#define BP_CPM_DDRCDR_CLKSRC            30
#define BM_CPM_DDRCDR_CLKSRC            0xc0000000
#define BV_CPM_DDRCDR_CLKSRC__STOP      0x0
#define BV_CPM_DDRCDR_CLKSRC__SCLK_A    0x1
#define BV_CPM_DDRCDR_CLKSRC__MPLL      0x2
#define BF_CPM_DDRCDR_CLKSRC(v)         (((v) & 0x3) << 30)
#define BFM_CPM_DDRCDR_CLKSRC(v)        BM_CPM_DDRCDR_CLKSRC
#define BF_CPM_DDRCDR_CLKSRC_V(e)       BF_CPM_DDRCDR_CLKSRC(BV_CPM_DDRCDR_CLKSRC__##e)
#define BFM_CPM_DDRCDR_CLKSRC_V(v)      BM_CPM_DDRCDR_CLKSRC
#define BP_CPM_DDRCDR_CLKDIV            0
#define BM_CPM_DDRCDR_CLKDIV            0xf
#define BF_CPM_DDRCDR_CLKDIV(v)         (((v) & 0xf) << 0)
#define BFM_CPM_DDRCDR_CLKDIV(v)        BM_CPM_DDRCDR_CLKDIV
#define BF_CPM_DDRCDR_CLKDIV_V(e)       BF_CPM_DDRCDR_CLKDIV(BV_CPM_DDRCDR_CLKDIV__##e)
#define BFM_CPM_DDRCDR_CLKDIV_V(v)      BM_CPM_DDRCDR_CLKDIV
#define BP_CPM_DDRCDR_CE                29
#define BM_CPM_DDRCDR_CE                0x20000000
#define BF_CPM_DDRCDR_CE(v)             (((v) & 0x1) << 29)
#define BFM_CPM_DDRCDR_CE(v)            BM_CPM_DDRCDR_CE
#define BF_CPM_DDRCDR_CE_V(e)           BF_CPM_DDRCDR_CE(BV_CPM_DDRCDR_CE__##e)
#define BFM_CPM_DDRCDR_CE_V(v)          BM_CPM_DDRCDR_CE
#define BP_CPM_DDRCDR_BUSY              28
#define BM_CPM_DDRCDR_BUSY              0x10000000
#define BF_CPM_DDRCDR_BUSY(v)           (((v) & 0x1) << 28)
#define BFM_CPM_DDRCDR_BUSY(v)          BM_CPM_DDRCDR_BUSY
#define BF_CPM_DDRCDR_BUSY_V(e)         BF_CPM_DDRCDR_BUSY(BV_CPM_DDRCDR_BUSY__##e)
#define BFM_CPM_DDRCDR_BUSY_V(v)        BM_CPM_DDRCDR_BUSY
#define BP_CPM_DDRCDR_STOP              27
#define BM_CPM_DDRCDR_STOP              0x8000000
#define BF_CPM_DDRCDR_STOP(v)           (((v) & 0x1) << 27)
#define BFM_CPM_DDRCDR_STOP(v)          BM_CPM_DDRCDR_STOP
#define BF_CPM_DDRCDR_STOP_V(e)         BF_CPM_DDRCDR_STOP(BV_CPM_DDRCDR_STOP__##e)
#define BFM_CPM_DDRCDR_STOP_V(v)        BM_CPM_DDRCDR_STOP
#define BP_CPM_DDRCDR_GATE_EN           26
#define BM_CPM_DDRCDR_GATE_EN           0x4000000
#define BF_CPM_DDRCDR_GATE_EN(v)        (((v) & 0x1) << 26)
#define BFM_CPM_DDRCDR_GATE_EN(v)       BM_CPM_DDRCDR_GATE_EN
#define BF_CPM_DDRCDR_GATE_EN_V(e)      BF_CPM_DDRCDR_GATE_EN(BV_CPM_DDRCDR_GATE_EN__##e)
#define BFM_CPM_DDRCDR_GATE_EN_V(v)     BM_CPM_DDRCDR_GATE_EN
#define BP_CPM_DDRCDR_CHANGE_EN         25
#define BM_CPM_DDRCDR_CHANGE_EN         0x2000000
#define BF_CPM_DDRCDR_CHANGE_EN(v)      (((v) & 0x1) << 25)
#define BFM_CPM_DDRCDR_CHANGE_EN(v)     BM_CPM_DDRCDR_CHANGE_EN
#define BF_CPM_DDRCDR_CHANGE_EN_V(e)    BF_CPM_DDRCDR_CHANGE_EN(BV_CPM_DDRCDR_CHANGE_EN__##e)
#define BFM_CPM_DDRCDR_CHANGE_EN_V(v)   BM_CPM_DDRCDR_CHANGE_EN
#define BP_CPM_DDRCDR_FLAG              24
#define BM_CPM_DDRCDR_FLAG              0x1000000
#define BF_CPM_DDRCDR_FLAG(v)           (((v) & 0x1) << 24)
#define BFM_CPM_DDRCDR_FLAG(v)          BM_CPM_DDRCDR_FLAG
#define BF_CPM_DDRCDR_FLAG_V(e)         BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e)
#define BFM_CPM_DDRCDR_FLAG_V(v)        BM_CPM_DDRCDR_FLAG

#define REG_CPM_MACCDR                  jz_reg(CPM_MACCDR)
#define JA_CPM_MACCDR                   (0xb0000000 + 0x54)
#define JT_CPM_MACCDR                   JIO_32_RW
#define JN_CPM_MACCDR                   CPM_MACCDR
#define JI_CPM_MACCDR                   
#define BP_CPM_MACCDR_CLKDIV            0
#define BM_CPM_MACCDR_CLKDIV            0xff
#define BF_CPM_MACCDR_CLKDIV(v)         (((v) & 0xff) << 0)
#define BFM_CPM_MACCDR_CLKDIV(v)        BM_CPM_MACCDR_CLKDIV
#define BF_CPM_MACCDR_CLKDIV_V(e)       BF_CPM_MACCDR_CLKDIV(BV_CPM_MACCDR_CLKDIV__##e)
#define BFM_CPM_MACCDR_CLKDIV_V(v)      BM_CPM_MACCDR_CLKDIV
#define BP_CPM_MACCDR_CLKSRC            31
#define BM_CPM_MACCDR_CLKSRC            0x80000000
#define BV_CPM_MACCDR_CLKSRC__SCLK_A    0x0
#define BV_CPM_MACCDR_CLKSRC__MPLL      0x1
#define BF_CPM_MACCDR_CLKSRC(v)         (((v) & 0x1) << 31)
#define BFM_CPM_MACCDR_CLKSRC(v)        BM_CPM_MACCDR_CLKSRC
#define BF_CPM_MACCDR_CLKSRC_V(e)       BF_CPM_MACCDR_CLKSRC(BV_CPM_MACCDR_CLKSRC__##e)
#define BFM_CPM_MACCDR_CLKSRC_V(v)      BM_CPM_MACCDR_CLKSRC
#define BP_CPM_MACCDR_CE                29
#define BM_CPM_MACCDR_CE                0x20000000
#define BF_CPM_MACCDR_CE(v)             (((v) & 0x1) << 29)
#define BFM_CPM_MACCDR_CE(v)            BM_CPM_MACCDR_CE
#define BF_CPM_MACCDR_CE_V(e)           BF_CPM_MACCDR_CE(BV_CPM_MACCDR_CE__##e)
#define BFM_CPM_MACCDR_CE_V(v)          BM_CPM_MACCDR_CE
#define BP_CPM_MACCDR_BUSY              28
#define BM_CPM_MACCDR_BUSY              0x10000000
#define BF_CPM_MACCDR_BUSY(v)           (((v) & 0x1) << 28)
#define BFM_CPM_MACCDR_BUSY(v)          BM_CPM_MACCDR_BUSY
#define BF_CPM_MACCDR_BUSY_V(e)         BF_CPM_MACCDR_BUSY(BV_CPM_MACCDR_BUSY__##e)
#define BFM_CPM_MACCDR_BUSY_V(v)        BM_CPM_MACCDR_BUSY
#define BP_CPM_MACCDR_STOP              27
#define BM_CPM_MACCDR_STOP              0x8000000
#define BF_CPM_MACCDR_STOP(v)           (((v) & 0x1) << 27)
#define BFM_CPM_MACCDR_STOP(v)          BM_CPM_MACCDR_STOP
#define BF_CPM_MACCDR_STOP_V(e)         BF_CPM_MACCDR_STOP(BV_CPM_MACCDR_STOP__##e)
#define BFM_CPM_MACCDR_STOP_V(v)        BM_CPM_MACCDR_STOP

#define REG_CPM_I2SCDR              jz_reg(CPM_I2SCDR)
#define JA_CPM_I2SCDR               (0xb0000000 + 0x60)
#define JT_CPM_I2SCDR               JIO_32_RW
#define JN_CPM_I2SCDR               CPM_I2SCDR
#define JI_CPM_I2SCDR               
#define BP_CPM_I2SCDR_DIV_M         13
#define BM_CPM_I2SCDR_DIV_M         0x3fe000
#define BF_CPM_I2SCDR_DIV_M(v)      (((v) & 0x1ff) << 13)
#define BFM_CPM_I2SCDR_DIV_M(v)     BM_CPM_I2SCDR_DIV_M
#define BF_CPM_I2SCDR_DIV_M_V(e)    BF_CPM_I2SCDR_DIV_M(BV_CPM_I2SCDR_DIV_M__##e)
#define BFM_CPM_I2SCDR_DIV_M_V(v)   BM_CPM_I2SCDR_DIV_M
#define BP_CPM_I2SCDR_DIV_N         0
#define BM_CPM_I2SCDR_DIV_N         0x1fff
#define BF_CPM_I2SCDR_DIV_N(v)      (((v) & 0x1fff) << 0)
#define BFM_CPM_I2SCDR_DIV_N(v)     BM_CPM_I2SCDR_DIV_N
#define BF_CPM_I2SCDR_DIV_N_V(e)    BF_CPM_I2SCDR_DIV_N(BV_CPM_I2SCDR_DIV_N__##e)
#define BFM_CPM_I2SCDR_DIV_N_V(v)   BM_CPM_I2SCDR_DIV_N
#define BP_CPM_I2SCDR_PCS           31
#define BM_CPM_I2SCDR_PCS           0x80000000
#define BV_CPM_I2SCDR_PCS__SCLK_A   0x0
#define BV_CPM_I2SCDR_PCS__MPLL     0x1
#define BF_CPM_I2SCDR_PCS(v)        (((v) & 0x1) << 31)
#define BFM_CPM_I2SCDR_PCS(v)       BM_CPM_I2SCDR_PCS
#define BF_CPM_I2SCDR_PCS_V(e)      BF_CPM_I2SCDR_PCS(BV_CPM_I2SCDR_PCS__##e)
#define BFM_CPM_I2SCDR_PCS_V(v)     BM_CPM_I2SCDR_PCS
#define BP_CPM_I2SCDR_CS            30
#define BM_CPM_I2SCDR_CS            0x40000000
#define BV_CPM_I2SCDR_CS__EXCLK     0x0
#define BV_CPM_I2SCDR_CS__PLL       0x1
#define BF_CPM_I2SCDR_CS(v)         (((v) & 0x1) << 30)
#define BFM_CPM_I2SCDR_CS(v)        BM_CPM_I2SCDR_CS
#define BF_CPM_I2SCDR_CS_V(e)       BF_CPM_I2SCDR_CS(BV_CPM_I2SCDR_CS__##e)
#define BFM_CPM_I2SCDR_CS_V(v)      BM_CPM_I2SCDR_CS
#define BP_CPM_I2SCDR_CE            29
#define BM_CPM_I2SCDR_CE            0x20000000
#define BF_CPM_I2SCDR_CE(v)         (((v) & 0x1) << 29)
#define BFM_CPM_I2SCDR_CE(v)        BM_CPM_I2SCDR_CE
#define BF_CPM_I2SCDR_CE_V(e)       BF_CPM_I2SCDR_CE(BV_CPM_I2SCDR_CE__##e)
#define BFM_CPM_I2SCDR_CE_V(v)      BM_CPM_I2SCDR_CE

#define REG_CPM_I2SCDR1 jz_reg(CPM_I2SCDR1)
#define JA_CPM_I2SCDR1  (0xb0000000 + 0x70)
#define JT_CPM_I2SCDR1  JIO_32_RW
#define JN_CPM_I2SCDR1  CPM_I2SCDR1
#define JI_CPM_I2SCDR1  

#define REG_CPM_LPCDR               jz_reg(CPM_LPCDR)
#define JA_CPM_LPCDR                (0xb0000000 + 0x64)
#define JT_CPM_LPCDR                JIO_32_RW
#define JN_CPM_LPCDR                CPM_LPCDR
#define JI_CPM_LPCDR                
#define BP_CPM_LPCDR_CLKDIV         0
#define BM_CPM_LPCDR_CLKDIV         0xff
#define BF_CPM_LPCDR_CLKDIV(v)      (((v) & 0xff) << 0)
#define BFM_CPM_LPCDR_CLKDIV(v)     BM_CPM_LPCDR_CLKDIV
#define BF_CPM_LPCDR_CLKDIV_V(e)    BF_CPM_LPCDR_CLKDIV(BV_CPM_LPCDR_CLKDIV__##e)
#define BFM_CPM_LPCDR_CLKDIV_V(v)   BM_CPM_LPCDR_CLKDIV
#define BP_CPM_LPCDR_CLKSRC         31
#define BM_CPM_LPCDR_CLKSRC         0x80000000
#define BV_CPM_LPCDR_CLKSRC__SCLK_A 0x0
#define BV_CPM_LPCDR_CLKSRC__MPLL   0x1
#define BF_CPM_LPCDR_CLKSRC(v)      (((v) & 0x1) << 31)
#define BFM_CPM_LPCDR_CLKSRC(v)     BM_CPM_LPCDR_CLKSRC
#define BF_CPM_LPCDR_CLKSRC_V(e)    BF_CPM_LPCDR_CLKSRC(BV_CPM_LPCDR_CLKSRC__##e)
#define BFM_CPM_LPCDR_CLKSRC_V(v)   BM_CPM_LPCDR_CLKSRC
#define BP_CPM_LPCDR_CE             28
#define BM_CPM_LPCDR_CE             0x10000000
#define BF_CPM_LPCDR_CE(v)          (((v) & 0x1) << 28)
#define BFM_CPM_LPCDR_CE(v)         BM_CPM_LPCDR_CE
#define BF_CPM_LPCDR_CE_V(e)        BF_CPM_LPCDR_CE(BV_CPM_LPCDR_CE__##e)
#define BFM_CPM_LPCDR_CE_V(v)       BM_CPM_LPCDR_CE
#define BP_CPM_LPCDR_BUSY           27
#define BM_CPM_LPCDR_BUSY           0x8000000
#define BF_CPM_LPCDR_BUSY(v)        (((v) & 0x1) << 27)
#define BFM_CPM_LPCDR_BUSY(v)       BM_CPM_LPCDR_BUSY
#define BF_CPM_LPCDR_BUSY_V(e)      BF_CPM_LPCDR_BUSY(BV_CPM_LPCDR_BUSY__##e)
#define BFM_CPM_LPCDR_BUSY_V(v)     BM_CPM_LPCDR_BUSY
#define BP_CPM_LPCDR_STOP           26
#define BM_CPM_LPCDR_STOP           0x4000000
#define BF_CPM_LPCDR_STOP(v)        (((v) & 0x1) << 26)
#define BFM_CPM_LPCDR_STOP(v)       BM_CPM_LPCDR_STOP
#define BF_CPM_LPCDR_STOP_V(e)      BF_CPM_LPCDR_STOP(BV_CPM_LPCDR_STOP__##e)
#define BFM_CPM_LPCDR_STOP_V(v)     BM_CPM_LPCDR_STOP

#define REG_CPM_MSC0CDR                     jz_reg(CPM_MSC0CDR)
#define JA_CPM_MSC0CDR                      (0xb0000000 + 0x68)
#define JT_CPM_MSC0CDR                      JIO_32_RW
#define JN_CPM_MSC0CDR                      CPM_MSC0CDR
#define JI_CPM_MSC0CDR                      
#define BP_CPM_MSC0CDR_CLKDIV               0
#define BM_CPM_MSC0CDR_CLKDIV               0xff
#define BF_CPM_MSC0CDR_CLKDIV(v)            (((v) & 0xff) << 0)
#define BFM_CPM_MSC0CDR_CLKDIV(v)           BM_CPM_MSC0CDR_CLKDIV
#define BF_CPM_MSC0CDR_CLKDIV_V(e)          BF_CPM_MSC0CDR_CLKDIV(BV_CPM_MSC0CDR_CLKDIV__##e)
#define BFM_CPM_MSC0CDR_CLKDIV_V(v)         BM_CPM_MSC0CDR_CLKDIV
#define BP_CPM_MSC0CDR_CLKSRC               31
#define BM_CPM_MSC0CDR_CLKSRC               0x80000000
#define BV_CPM_MSC0CDR_CLKSRC__SCLK_A       0x0
#define BV_CPM_MSC0CDR_CLKSRC__MPLL         0x1
#define BF_CPM_MSC0CDR_CLKSRC(v)            (((v) & 0x1) << 31)
#define BFM_CPM_MSC0CDR_CLKSRC(v)           BM_CPM_MSC0CDR_CLKSRC
#define BF_CPM_MSC0CDR_CLKSRC_V(e)          BF_CPM_MSC0CDR_CLKSRC(BV_CPM_MSC0CDR_CLKSRC__##e)
#define BFM_CPM_MSC0CDR_CLKSRC_V(v)         BM_CPM_MSC0CDR_CLKSRC
#define BP_CPM_MSC0CDR_CE                   29
#define BM_CPM_MSC0CDR_CE                   0x20000000
#define BF_CPM_MSC0CDR_CE(v)                (((v) & 0x1) << 29)
#define BFM_CPM_MSC0CDR_CE(v)               BM_CPM_MSC0CDR_CE
#define BF_CPM_MSC0CDR_CE_V(e)              BF_CPM_MSC0CDR_CE(BV_CPM_MSC0CDR_CE__##e)
#define BFM_CPM_MSC0CDR_CE_V(v)             BM_CPM_MSC0CDR_CE
#define BP_CPM_MSC0CDR_BUSY                 28
#define BM_CPM_MSC0CDR_BUSY                 0x10000000
#define BF_CPM_MSC0CDR_BUSY(v)              (((v) & 0x1) << 28)
#define BFM_CPM_MSC0CDR_BUSY(v)             BM_CPM_MSC0CDR_BUSY
#define BF_CPM_MSC0CDR_BUSY_V(e)            BF_CPM_MSC0CDR_BUSY(BV_CPM_MSC0CDR_BUSY__##e)
#define BFM_CPM_MSC0CDR_BUSY_V(v)           BM_CPM_MSC0CDR_BUSY
#define BP_CPM_MSC0CDR_STOP                 27
#define BM_CPM_MSC0CDR_STOP                 0x8000000
#define BF_CPM_MSC0CDR_STOP(v)              (((v) & 0x1) << 27)
#define BFM_CPM_MSC0CDR_STOP(v)             BM_CPM_MSC0CDR_STOP
#define BF_CPM_MSC0CDR_STOP_V(e)            BF_CPM_MSC0CDR_STOP(BV_CPM_MSC0CDR_STOP__##e)
#define BFM_CPM_MSC0CDR_STOP_V(v)           BM_CPM_MSC0CDR_STOP
#define BP_CPM_MSC0CDR_S_CLK0_SEL           15
#define BM_CPM_MSC0CDR_S_CLK0_SEL           0x8000
#define BV_CPM_MSC0CDR_S_CLK0_SEL__90DEG    0x0
#define BV_CPM_MSC0CDR_S_CLK0_SEL__180DEG   0x1
#define BF_CPM_MSC0CDR_S_CLK0_SEL(v)        (((v) & 0x1) << 15)
#define BFM_CPM_MSC0CDR_S_CLK0_SEL(v)       BM_CPM_MSC0CDR_S_CLK0_SEL
#define BF_CPM_MSC0CDR_S_CLK0_SEL_V(e)      BF_CPM_MSC0CDR_S_CLK0_SEL(BV_CPM_MSC0CDR_S_CLK0_SEL__##e)
#define BFM_CPM_MSC0CDR_S_CLK0_SEL_V(v)     BM_CPM_MSC0CDR_S_CLK0_SEL

#define REG_CPM_MSC1CDR                     jz_reg(CPM_MSC1CDR)
#define JA_CPM_MSC1CDR                      (0xb0000000 + 0xa4)
#define JT_CPM_MSC1CDR                      JIO_32_RW
#define JN_CPM_MSC1CDR                      CPM_MSC1CDR
#define JI_CPM_MSC1CDR                      
#define BP_CPM_MSC1CDR_CLKDIV               0
#define BM_CPM_MSC1CDR_CLKDIV               0xff
#define BF_CPM_MSC1CDR_CLKDIV(v)            (((v) & 0xff) << 0)
#define BFM_CPM_MSC1CDR_CLKDIV(v)           BM_CPM_MSC1CDR_CLKDIV
#define BF_CPM_MSC1CDR_CLKDIV_V(e)          BF_CPM_MSC1CDR_CLKDIV(BV_CPM_MSC1CDR_CLKDIV__##e)
#define BFM_CPM_MSC1CDR_CLKDIV_V(v)         BM_CPM_MSC1CDR_CLKDIV
#define BP_CPM_MSC1CDR_CE                   29
#define BM_CPM_MSC1CDR_CE                   0x20000000
#define BF_CPM_MSC1CDR_CE(v)                (((v) & 0x1) << 29)
#define BFM_CPM_MSC1CDR_CE(v)               BM_CPM_MSC1CDR_CE
#define BF_CPM_MSC1CDR_CE_V(e)              BF_CPM_MSC1CDR_CE(BV_CPM_MSC1CDR_CE__##e)
#define BFM_CPM_MSC1CDR_CE_V(v)             BM_CPM_MSC1CDR_CE
#define BP_CPM_MSC1CDR_BUSY                 28
#define BM_CPM_MSC1CDR_BUSY                 0x10000000
#define BF_CPM_MSC1CDR_BUSY(v)              (((v) & 0x1) << 28)
#define BFM_CPM_MSC1CDR_BUSY(v)             BM_CPM_MSC1CDR_BUSY
#define BF_CPM_MSC1CDR_BUSY_V(e)            BF_CPM_MSC1CDR_BUSY(BV_CPM_MSC1CDR_BUSY__##e)
#define BFM_CPM_MSC1CDR_BUSY_V(v)           BM_CPM_MSC1CDR_BUSY
#define BP_CPM_MSC1CDR_STOP                 27
#define BM_CPM_MSC1CDR_STOP                 0x8000000
#define BF_CPM_MSC1CDR_STOP(v)              (((v) & 0x1) << 27)
#define BFM_CPM_MSC1CDR_STOP(v)             BM_CPM_MSC1CDR_STOP
#define BF_CPM_MSC1CDR_STOP_V(e)            BF_CPM_MSC1CDR_STOP(BV_CPM_MSC1CDR_STOP__##e)
#define BFM_CPM_MSC1CDR_STOP_V(v)           BM_CPM_MSC1CDR_STOP
#define BP_CPM_MSC1CDR_S_CLK1_SEL           15
#define BM_CPM_MSC1CDR_S_CLK1_SEL           0x8000
#define BV_CPM_MSC1CDR_S_CLK1_SEL__90DEG    0x0
#define BV_CPM_MSC1CDR_S_CLK1_SEL__180DEG   0x1
#define BF_CPM_MSC1CDR_S_CLK1_SEL(v)        (((v) & 0x1) << 15)
#define BFM_CPM_MSC1CDR_S_CLK1_SEL(v)       BM_CPM_MSC1CDR_S_CLK1_SEL
#define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e)      BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e)
#define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v)     BM_CPM_MSC1CDR_S_CLK1_SEL

#define REG_CPM_USBCDR                  jz_reg(CPM_USBCDR)
#define JA_CPM_USBCDR                   (0xb0000000 + 0x50)
#define JT_CPM_USBCDR                   JIO_32_RW
#define JN_CPM_USBCDR                   CPM_USBCDR
#define JI_CPM_USBCDR                   
#define BP_CPM_USBCDR_CLKSRC            30
#define BM_CPM_USBCDR_CLKSRC            0xc0000000
#define BV_CPM_USBCDR_CLKSRC__EXCLK     0x0
#define BV_CPM_USBCDR_CLKSRC__SCLK_A    0x2
#define BV_CPM_USBCDR_CLKSRC__MPLL      0x3
#define BF_CPM_USBCDR_CLKSRC(v)         (((v) & 0x3) << 30)
#define BFM_CPM_USBCDR_CLKSRC(v)        BM_CPM_USBCDR_CLKSRC
#define BF_CPM_USBCDR_CLKSRC_V(e)       BF_CPM_USBCDR_CLKSRC(BV_CPM_USBCDR_CLKSRC__##e)
#define BFM_CPM_USBCDR_CLKSRC_V(v)      BM_CPM_USBCDR_CLKSRC
#define BP_CPM_USBCDR_CLKDIV            0
#define BM_CPM_USBCDR_CLKDIV            0xff
#define BF_CPM_USBCDR_CLKDIV(v)         (((v) & 0xff) << 0)
#define BFM_CPM_USBCDR_CLKDIV(v)        BM_CPM_USBCDR_CLKDIV
#define BF_CPM_USBCDR_CLKDIV_V(e)       BF_CPM_USBCDR_CLKDIV(BV_CPM_USBCDR_CLKDIV__##e)
#define BFM_CPM_USBCDR_CLKDIV_V(v)      BM_CPM_USBCDR_CLKDIV
#define BP_CPM_USBCDR_CE                29
#define BM_CPM_USBCDR_CE                0x20000000
#define BF_CPM_USBCDR_CE(v)             (((v) & 0x1) << 29)
#define BFM_CPM_USBCDR_CE(v)            BM_CPM_USBCDR_CE
#define BF_CPM_USBCDR_CE_V(e)           BF_CPM_USBCDR_CE(BV_CPM_USBCDR_CE__##e)
#define BFM_CPM_USBCDR_CE_V(v)          BM_CPM_USBCDR_CE
#define BP_CPM_USBCDR_BUSY              28
#define BM_CPM_USBCDR_BUSY              0x10000000
#define BF_CPM_USBCDR_BUSY(v)           (((v) & 0x1) << 28)
#define BFM_CPM_USBCDR_BUSY(v)          BM_CPM_USBCDR_BUSY
#define BF_CPM_USBCDR_BUSY_V(e)         BF_CPM_USBCDR_BUSY(BV_CPM_USBCDR_BUSY__##e)
#define BFM_CPM_USBCDR_BUSY_V(v)        BM_CPM_USBCDR_BUSY
#define BP_CPM_USBCDR_STOP              27
#define BM_CPM_USBCDR_STOP              0x8000000
#define BF_CPM_USBCDR_STOP(v)           (((v) & 0x1) << 27)
#define BFM_CPM_USBCDR_STOP(v)          BM_CPM_USBCDR_STOP
#define BF_CPM_USBCDR_STOP_V(e)         BF_CPM_USBCDR_STOP(BV_CPM_USBCDR_STOP__##e)
#define BFM_CPM_USBCDR_STOP_V(v)        BM_CPM_USBCDR_STOP
#define BP_CPM_USBCDR_PHY_GATE          26
#define BM_CPM_USBCDR_PHY_GATE          0x4000000
#define BF_CPM_USBCDR_PHY_GATE(v)       (((v) & 0x1) << 26)
#define BFM_CPM_USBCDR_PHY_GATE(v)      BM_CPM_USBCDR_PHY_GATE
#define BF_CPM_USBCDR_PHY_GATE_V(e)     BF_CPM_USBCDR_PHY_GATE(BV_CPM_USBCDR_PHY_GATE__##e)
#define BFM_CPM_USBCDR_PHY_GATE_V(v)    BM_CPM_USBCDR_PHY_GATE

#define REG_CPM_SSICDR                  jz_reg(CPM_SSICDR)
#define JA_CPM_SSICDR                   (0xb0000000 + 0x74)
#define JT_CPM_SSICDR                   JIO_32_RW
#define JN_CPM_SSICDR                   CPM_SSICDR
#define JI_CPM_SSICDR                   
#define BP_CPM_SSICDR_CLKDIV            0
#define BM_CPM_SSICDR_CLKDIV            0xff
#define BF_CPM_SSICDR_CLKDIV(v)         (((v) & 0xff) << 0)
#define BFM_CPM_SSICDR_CLKDIV(v)        BM_CPM_SSICDR_CLKDIV
#define BF_CPM_SSICDR_CLKDIV_V(e)       BF_CPM_SSICDR_CLKDIV(BV_CPM_SSICDR_CLKDIV__##e)
#define BFM_CPM_SSICDR_CLKDIV_V(v)      BM_CPM_SSICDR_CLKDIV
#define BP_CPM_SSICDR_SFC_CS            31
#define BM_CPM_SSICDR_SFC_CS            0x80000000
#define BV_CPM_SSICDR_SFC_CS__SCLK_A    0x0
#define BV_CPM_SSICDR_SFC_CS__MPLL      0x1
#define BF_CPM_SSICDR_SFC_CS(v)         (((v) & 0x1) << 31)
#define BFM_CPM_SSICDR_SFC_CS(v)        BM_CPM_SSICDR_SFC_CS
#define BF_CPM_SSICDR_SFC_CS_V(e)       BF_CPM_SSICDR_SFC_CS(BV_CPM_SSICDR_SFC_CS__##e)
#define BFM_CPM_SSICDR_SFC_CS_V(v)      BM_CPM_SSICDR_SFC_CS
#define BP_CPM_SSICDR_SSI_CS            30
#define BM_CPM_SSICDR_SSI_CS            0x40000000
#define BV_CPM_SSICDR_SSI_CS__EXCLK     0x0
#define BV_CPM_SSICDR_SSI_CS__HALF_SFC  0x1
#define BF_CPM_SSICDR_SSI_CS(v)         (((v) & 0x1) << 30)
#define BFM_CPM_SSICDR_SSI_CS(v)        BM_CPM_SSICDR_SSI_CS
#define BF_CPM_SSICDR_SSI_CS_V(e)       BF_CPM_SSICDR_SSI_CS(BV_CPM_SSICDR_SSI_CS__##e)
#define BFM_CPM_SSICDR_SSI_CS_V(v)      BM_CPM_SSICDR_SSI_CS
#define BP_CPM_SSICDR_CE                29
#define BM_CPM_SSICDR_CE                0x20000000
#define BF_CPM_SSICDR_CE(v)             (((v) & 0x1) << 29)
#define BFM_CPM_SSICDR_CE(v)            BM_CPM_SSICDR_CE
#define BF_CPM_SSICDR_CE_V(e)           BF_CPM_SSICDR_CE(BV_CPM_SSICDR_CE__##e)
#define BFM_CPM_SSICDR_CE_V(v)          BM_CPM_SSICDR_CE
#define BP_CPM_SSICDR_BUSY              28
#define BM_CPM_SSICDR_BUSY              0x10000000
#define BF_CPM_SSICDR_BUSY(v)           (((v) & 0x1) << 28)
#define BFM_CPM_SSICDR_BUSY(v)          BM_CPM_SSICDR_BUSY
#define BF_CPM_SSICDR_BUSY_V(e)         BF_CPM_SSICDR_BUSY(BV_CPM_SSICDR_BUSY__##e)
#define BFM_CPM_SSICDR_BUSY_V(v)        BM_CPM_SSICDR_BUSY
#define BP_CPM_SSICDR_STOP              27
#define BM_CPM_SSICDR_STOP              0x8000000
#define BF_CPM_SSICDR_STOP(v)           (((v) & 0x1) << 27)
#define BFM_CPM_SSICDR_STOP(v)          BM_CPM_SSICDR_STOP
#define BF_CPM_SSICDR_STOP_V(e)         BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e)
#define BFM_CPM_SSICDR_STOP_V(v)        BM_CPM_SSICDR_STOP

#define REG_CPM_CIMCDR                  jz_reg(CPM_CIMCDR)
#define JA_CPM_CIMCDR                   (0xb0000000 + 0x7c)
#define JT_CPM_CIMCDR                   JIO_32_RW
#define JN_CPM_CIMCDR                   CPM_CIMCDR
#define JI_CPM_CIMCDR                   
#define BP_CPM_CIMCDR_CLKDIV            0
#define BM_CPM_CIMCDR_CLKDIV            0xff
#define BF_CPM_CIMCDR_CLKDIV(v)         (((v) & 0xff) << 0)
#define BFM_CPM_CIMCDR_CLKDIV(v)        BM_CPM_CIMCDR_CLKDIV
#define BF_CPM_CIMCDR_CLKDIV_V(e)       BF_CPM_CIMCDR_CLKDIV(BV_CPM_CIMCDR_CLKDIV__##e)
#define BFM_CPM_CIMCDR_CLKDIV_V(v)      BM_CPM_CIMCDR_CLKDIV
#define BP_CPM_CIMCDR_CLKSRC            31
#define BM_CPM_CIMCDR_CLKSRC            0x80000000
#define BV_CPM_CIMCDR_CLKSRC__SCLK_A    0x1
#define BV_CPM_CIMCDR_CLKSRC__MPLL      0x1
#define BF_CPM_CIMCDR_CLKSRC(v)         (((v) & 0x1) << 31)
#define BFM_CPM_CIMCDR_CLKSRC(v)        BM_CPM_CIMCDR_CLKSRC
#define BF_CPM_CIMCDR_CLKSRC_V(e)       BF_CPM_CIMCDR_CLKSRC(BV_CPM_CIMCDR_CLKSRC__##e)
#define BFM_CPM_CIMCDR_CLKSRC_V(v)      BM_CPM_CIMCDR_CLKSRC
#define BP_CPM_CIMCDR_CE                29
#define BM_CPM_CIMCDR_CE                0x20000000
#define BF_CPM_CIMCDR_CE(v)             (((v) & 0x1) << 29)
#define BFM_CPM_CIMCDR_CE(v)            BM_CPM_CIMCDR_CE
#define BF_CPM_CIMCDR_CE_V(e)           BF_CPM_CIMCDR_CE(BV_CPM_CIMCDR_CE__##e)
#define BFM_CPM_CIMCDR_CE_V(v)          BM_CPM_CIMCDR_CE
#define BP_CPM_CIMCDR_BUSY              28
#define BM_CPM_CIMCDR_BUSY              0x10000000
#define BF_CPM_CIMCDR_BUSY(v)           (((v) & 0x1) << 28)
#define BFM_CPM_CIMCDR_BUSY(v)          BM_CPM_CIMCDR_BUSY
#define BF_CPM_CIMCDR_BUSY_V(e)         BF_CPM_CIMCDR_BUSY(BV_CPM_CIMCDR_BUSY__##e)
#define BFM_CPM_CIMCDR_BUSY_V(v)        BM_CPM_CIMCDR_BUSY
#define BP_CPM_CIMCDR_STOP              27
#define BM_CPM_CIMCDR_STOP              0x8000000
#define BF_CPM_CIMCDR_STOP(v)           (((v) & 0x1) << 27)
#define BFM_CPM_CIMCDR_STOP(v)          BM_CPM_CIMCDR_STOP
#define BF_CPM_CIMCDR_STOP_V(e)         BF_CPM_CIMCDR_STOP(BV_CPM_CIMCDR_STOP__##e)
#define BFM_CPM_CIMCDR_STOP_V(v)        BM_CPM_CIMCDR_STOP

#define REG_CPM_PCMCDR              jz_reg(CPM_PCMCDR)
#define JA_CPM_PCMCDR               (0xb0000000 + 0x84)
#define JT_CPM_PCMCDR               JIO_32_RW
#define JN_CPM_PCMCDR               CPM_PCMCDR
#define JI_CPM_PCMCDR               
#define BP_CPM_PCMCDR_DIV_M         13
#define BM_CPM_PCMCDR_DIV_M         0x3fe000
#define BF_CPM_PCMCDR_DIV_M(v)      (((v) & 0x1ff) << 13)
#define BFM_CPM_PCMCDR_DIV_M(v)     BM_CPM_PCMCDR_DIV_M
#define BF_CPM_PCMCDR_DIV_M_V(e)    BF_CPM_PCMCDR_DIV_M(BV_CPM_PCMCDR_DIV_M__##e)
#define BFM_CPM_PCMCDR_DIV_M_V(v)   BM_CPM_PCMCDR_DIV_M
#define BP_CPM_PCMCDR_DIV_N         0
#define BM_CPM_PCMCDR_DIV_N         0x1fff
#define BF_CPM_PCMCDR_DIV_N(v)      (((v) & 0x1fff) << 0)
#define BFM_CPM_PCMCDR_DIV_N(v)     BM_CPM_PCMCDR_DIV_N
#define BF_CPM_PCMCDR_DIV_N_V(e)    BF_CPM_PCMCDR_DIV_N(BV_CPM_PCMCDR_DIV_N__##e)
#define BFM_CPM_PCMCDR_DIV_N_V(v)   BM_CPM_PCMCDR_DIV_N
#define BP_CPM_PCMCDR_PCS           31
#define BM_CPM_PCMCDR_PCS           0x80000000
#define BV_CPM_PCMCDR_PCS__SCLK_A   0x0
#define BV_CPM_PCMCDR_PCS__MPLL     0x1
#define BF_CPM_PCMCDR_PCS(v)        (((v) & 0x1) << 31)
#define BFM_CPM_PCMCDR_PCS(v)       BM_CPM_PCMCDR_PCS
#define BF_CPM_PCMCDR_PCS_V(e)      BF_CPM_PCMCDR_PCS(BV_CPM_PCMCDR_PCS__##e)
#define BFM_CPM_PCMCDR_PCS_V(v)     BM_CPM_PCMCDR_PCS
#define BP_CPM_PCMCDR_CS            30
#define BM_CPM_PCMCDR_CS            0x40000000
#define BV_CPM_PCMCDR_CS__EXCLK     0x0
#define BV_CPM_PCMCDR_CS__PLL       0x1
#define BF_CPM_PCMCDR_CS(v)         (((v) & 0x1) << 30)
#define BFM_CPM_PCMCDR_CS(v)        BM_CPM_PCMCDR_CS
#define BF_CPM_PCMCDR_CS_V(e)       BF_CPM_PCMCDR_CS(BV_CPM_PCMCDR_CS__##e)
#define BFM_CPM_PCMCDR_CS_V(v)      BM_CPM_PCMCDR_CS
#define BP_CPM_PCMCDR_CE            29
#define BM_CPM_PCMCDR_CE            0x20000000
#define BF_CPM_PCMCDR_CE(v)         (((v) & 0x1) << 29)
#define BFM_CPM_PCMCDR_CE(v)        BM_CPM_PCMCDR_CE
#define BF_CPM_PCMCDR_CE_V(e)       BF_CPM_PCMCDR_CE(BV_CPM_PCMCDR_CE__##e)
#define BFM_CPM_PCMCDR_CE_V(v)      BM_CPM_PCMCDR_CE

#define REG_CPM_PCMCDR1             jz_reg(CPM_PCMCDR1)
#define JA_CPM_PCMCDR1              (0xb0000000 + 0xe0)
#define JT_CPM_PCMCDR1              JIO_32_RW
#define JN_CPM_PCMCDR1              CPM_PCMCDR1
#define JI_CPM_PCMCDR1              
#define BP_CPM_PCMCDR1_DIV_D        0
#define BM_CPM_PCMCDR1_DIV_D        0x1fff
#define BF_CPM_PCMCDR1_DIV_D(v)     (((v) & 0x1fff) << 0)
#define BFM_CPM_PCMCDR1_DIV_D(v)    BM_CPM_PCMCDR1_DIV_D
#define BF_CPM_PCMCDR1_DIV_D_V(e)   BF_CPM_PCMCDR1_DIV_D(BV_CPM_PCMCDR1_DIV_D__##e)
#define BFM_CPM_PCMCDR1_DIV_D_V(v)  BM_CPM_PCMCDR1_DIV_D
#define BP_CPM_PCMCDR1_N_EN         31
#define BM_CPM_PCMCDR1_N_EN         0x80000000
#define BF_CPM_PCMCDR1_N_EN(v)      (((v) & 0x1) << 31)
#define BFM_CPM_PCMCDR1_N_EN(v)     BM_CPM_PCMCDR1_N_EN
#define BF_CPM_PCMCDR1_N_EN_V(e)    BF_CPM_PCMCDR1_N_EN(BV_CPM_PCMCDR1_N_EN__##e)
#define BFM_CPM_PCMCDR1_N_EN_V(v)   BM_CPM_PCMCDR1_N_EN
#define BP_CPM_PCMCDR1_D_EN         30
#define BM_CPM_PCMCDR1_D_EN         0x40000000
#define BF_CPM_PCMCDR1_D_EN(v)      (((v) & 0x1) << 30)
#define BFM_CPM_PCMCDR1_D_EN(v)     BM_CPM_PCMCDR1_D_EN
#define BF_CPM_PCMCDR1_D_EN_V(e)    BF_CPM_PCMCDR1_D_EN(BV_CPM_PCMCDR1_D_EN__##e)
#define BFM_CPM_PCMCDR1_D_EN_V(v)   BM_CPM_PCMCDR1_D_EN

#define REG_CPM_INTR            jz_reg(CPM_INTR)
#define JA_CPM_INTR             (0xb0000000 + 0xb0)
#define JT_CPM_INTR             JIO_32_RW
#define JN_CPM_INTR             CPM_INTR
#define JI_CPM_INTR             
#define BP_CPM_INTR_VBUS        1
#define BM_CPM_INTR_VBUS        0x2
#define BF_CPM_INTR_VBUS(v)     (((v) & 0x1) << 1)
#define BFM_CPM_INTR_VBUS(v)    BM_CPM_INTR_VBUS
#define BF_CPM_INTR_VBUS_V(e)   BF_CPM_INTR_VBUS(BV_CPM_INTR_VBUS__##e)
#define BFM_CPM_INTR_VBUS_V(v)  BM_CPM_INTR_VBUS
#define BP_CPM_INTR_ADEV        0
#define BM_CPM_INTR_ADEV        0x1
#define BF_CPM_INTR_ADEV(v)     (((v) & 0x1) << 0)
#define BFM_CPM_INTR_ADEV(v)    BM_CPM_INTR_ADEV
#define BF_CPM_INTR_ADEV_V(e)   BF_CPM_INTR_ADEV(BV_CPM_INTR_ADEV__##e)
#define BFM_CPM_INTR_ADEV_V(v)  BM_CPM_INTR_ADEV

#define REG_CPM_INTR_EN             jz_reg(CPM_INTR_EN)
#define JA_CPM_INTR_EN              (0xb0000000 + 0xb4)
#define JT_CPM_INTR_EN              JIO_32_RW
#define JN_CPM_INTR_EN              CPM_INTR_EN
#define JI_CPM_INTR_EN              
#define BP_CPM_INTR_EN_VBUS         1
#define BM_CPM_INTR_EN_VBUS         0x2
#define BF_CPM_INTR_EN_VBUS(v)      (((v) & 0x1) << 1)
#define BFM_CPM_INTR_EN_VBUS(v)     BM_CPM_INTR_EN_VBUS
#define BF_CPM_INTR_EN_VBUS_V(e)    BF_CPM_INTR_EN_VBUS(BV_CPM_INTR_EN_VBUS__##e)
#define BFM_CPM_INTR_EN_VBUS_V(v)   BM_CPM_INTR_EN_VBUS
#define BP_CPM_INTR_EN_ADEV         0
#define BM_CPM_INTR_EN_ADEV         0x1
#define BF_CPM_INTR_EN_ADEV(v)      (((v) & 0x1) << 0)
#define BFM_CPM_INTR_EN_ADEV(v)     BM_CPM_INTR_EN_ADEV
#define BF_CPM_INTR_EN_ADEV_V(e)    BF_CPM_INTR_EN_ADEV(BV_CPM_INTR_EN_ADEV__##e)
#define BFM_CPM_INTR_EN_ADEV_V(v)   BM_CPM_INTR_EN_ADEV

#define REG_CPM_DRCG    jz_reg(CPM_DRCG)
#define JA_CPM_DRCG     (0xb0000000 + 0xd0)
#define JT_CPM_DRCG     JIO_32_RW
#define JN_CPM_DRCG     CPM_DRCG
#define JI_CPM_DRCG     

#define REG_CPM_SCRATCH_PROT    jz_reg(CPM_SCRATCH_PROT)
#define JA_CPM_SCRATCH_PROT     (0xb0000000 + 0x38)
#define JT_CPM_SCRATCH_PROT     JIO_32_RW
#define JN_CPM_SCRATCH_PROT     CPM_SCRATCH_PROT
#define JI_CPM_SCRATCH_PROT     

#define REG_CPM_SCRATCH jz_reg(CPM_SCRATCH)
#define JA_CPM_SCRATCH  (0xb0000000 + 0x34)
#define JT_CPM_SCRATCH  JIO_32_RW
#define JN_CPM_SCRATCH  CPM_SCRATCH
#define JI_CPM_SCRATCH  

#define REG_CPM_USBPCR                              jz_reg(CPM_USBPCR)
#define JA_CPM_USBPCR                               (0xb0000000 + 0x3c)
#define JT_CPM_USBPCR                               JIO_32_RW
#define JN_CPM_USBPCR                               CPM_USBPCR
#define JI_CPM_USBPCR                               
#define BP_CPM_USBPCR_IDPULLUP_MASK                 28
#define BM_CPM_USBPCR_IDPULLUP_MASK                 0x30000000
#define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS         0x2
#define BV_CPM_USBPCR_IDPULLUP_MASK__ALWAYS_SUSPEND 0x1
#define BV_CPM_USBPCR_IDPULLUP_MASK__FROM_OTG       0x0
#define BF_CPM_USBPCR_IDPULLUP_MASK(v)              (((v) & 0x3) << 28)
#define BFM_CPM_USBPCR_IDPULLUP_MASK(v)             BM_CPM_USBPCR_IDPULLUP_MASK
#define BF_CPM_USBPCR_IDPULLUP_MASK_V(e)            BF_CPM_USBPCR_IDPULLUP_MASK(BV_CPM_USBPCR_IDPULLUP_MASK__##e)
#define BFM_CPM_USBPCR_IDPULLUP_MASK_V(v)           BM_CPM_USBPCR_IDPULLUP_MASK
#define BP_CPM_USBPCR_COMPDISTUNE                   17
#define BM_CPM_USBPCR_COMPDISTUNE                   0xe0000
#define BF_CPM_USBPCR_COMPDISTUNE(v)                (((v) & 0x7) << 17)
#define BFM_CPM_USBPCR_COMPDISTUNE(v)               BM_CPM_USBPCR_COMPDISTUNE
#define BF_CPM_USBPCR_COMPDISTUNE_V(e)              BF_CPM_USBPCR_COMPDISTUNE(BV_CPM_USBPCR_COMPDISTUNE__##e)
#define BFM_CPM_USBPCR_COMPDISTUNE_V(v)             BM_CPM_USBPCR_COMPDISTUNE
#define BP_CPM_USBPCR_OTGTUNE                       14
#define BM_CPM_USBPCR_OTGTUNE                       0x1c000
#define BF_CPM_USBPCR_OTGTUNE(v)                    (((v) & 0x7) << 14)
#define BFM_CPM_USBPCR_OTGTUNE(v)                   BM_CPM_USBPCR_OTGTUNE
#define BF_CPM_USBPCR_OTGTUNE_V(e)                  BF_CPM_USBPCR_OTGTUNE(BV_CPM_USBPCR_OTGTUNE__##e)
#define BFM_CPM_USBPCR_OTGTUNE_V(v)                 BM_CPM_USBPCR_OTGTUNE
#define BP_CPM_USBPCR_SQRXTUNE                      11
#define BM_CPM_USBPCR_SQRXTUNE                      0x3800
#define BF_CPM_USBPCR_SQRXTUNE(v)                   (((v) & 0x7) << 11)
#define BFM_CPM_USBPCR_SQRXTUNE(v)                  BM_CPM_USBPCR_SQRXTUNE
#define BF_CPM_USBPCR_SQRXTUNE_V(e)                 BF_CPM_USBPCR_SQRXTUNE(BV_CPM_USBPCR_SQRXTUNE__##e)
#define BFM_CPM_USBPCR_SQRXTUNE_V(v)                BM_CPM_USBPCR_SQRXTUNE
#define BP_CPM_USBPCR_TXFSLSTUNE                    7
#define BM_CPM_USBPCR_TXFSLSTUNE                    0x780
#define BF_CPM_USBPCR_TXFSLSTUNE(v)                 (((v) & 0xf) << 7)
#define BFM_CPM_USBPCR_TXFSLSTUNE(v)                BM_CPM_USBPCR_TXFSLSTUNE
#define BF_CPM_USBPCR_TXFSLSTUNE_V(e)               BF_CPM_USBPCR_TXFSLSTUNE(BV_CPM_USBPCR_TXFSLSTUNE__##e)
#define BFM_CPM_USBPCR_TXFSLSTUNE_V(v)              BM_CPM_USBPCR_TXFSLSTUNE
#define BP_CPM_USBPCR_TXHSXVTUNE                    4
#define BM_CPM_USBPCR_TXHSXVTUNE                    0x30
#define BF_CPM_USBPCR_TXHSXVTUNE(v)                 (((v) & 0x3) << 4)
#define BFM_CPM_USBPCR_TXHSXVTUNE(v)                BM_CPM_USBPCR_TXHSXVTUNE
#define BF_CPM_USBPCR_TXHSXVTUNE_V(e)               BF_CPM_USBPCR_TXHSXVTUNE(BV_CPM_USBPCR_TXHSXVTUNE__##e)
#define BFM_CPM_USBPCR_TXHSXVTUNE_V(v)              BM_CPM_USBPCR_TXHSXVTUNE
#define BP_CPM_USBPCR_TXVREFTUNE                    0
#define BM_CPM_USBPCR_TXVREFTUNE                    0xf
#define BF_CPM_USBPCR_TXVREFTUNE(v)                 (((v) & 0xf) << 0)
#define BFM_CPM_USBPCR_TXVREFTUNE(v)                BM_CPM_USBPCR_TXVREFTUNE
#define BF_CPM_USBPCR_TXVREFTUNE_V(e)               BF_CPM_USBPCR_TXVREFTUNE(BV_CPM_USBPCR_TXVREFTUNE__##e)
#define BFM_CPM_USBPCR_TXVREFTUNE_V(v)              BM_CPM_USBPCR_TXVREFTUNE
#define BP_CPM_USBPCR_USB_MODE                      31
#define BM_CPM_USBPCR_USB_MODE                      0x80000000
#define BV_CPM_USBPCR_USB_MODE__USB                 0x0
#define BV_CPM_USBPCR_USB_MODE__OTG                 0x1
#define BF_CPM_USBPCR_USB_MODE(v)                   (((v) & 0x1) << 31)
#define BFM_CPM_USBPCR_USB_MODE(v)                  BM_CPM_USBPCR_USB_MODE
#define BF_CPM_USBPCR_USB_MODE_V(e)                 BF_CPM_USBPCR_USB_MODE(BV_CPM_USBPCR_USB_MODE__##e)
#define BFM_CPM_USBPCR_USB_MODE_V(v)                BM_CPM_USBPCR_USB_MODE
#define BP_CPM_USBPCR_AVLD_REG                      30
#define BM_CPM_USBPCR_AVLD_REG                      0x40000000
#define BF_CPM_USBPCR_AVLD_REG(v)                   (((v) & 0x1) << 30)
#define BFM_CPM_USBPCR_AVLD_REG(v)                  BM_CPM_USBPCR_AVLD_REG
#define BF_CPM_USBPCR_AVLD_REG_V(e)                 BF_CPM_USBPCR_AVLD_REG(BV_CPM_USBPCR_AVLD_REG__##e)
#define BFM_CPM_USBPCR_AVLD_REG_V(v)                BM_CPM_USBPCR_AVLD_REG
#define BP_CPM_USBPCR_INCR_MASK                     27
#define BM_CPM_USBPCR_INCR_MASK                     0x8000000
#define BF_CPM_USBPCR_INCR_MASK(v)                  (((v) & 0x1) << 27)
#define BFM_CPM_USBPCR_INCR_MASK(v)                 BM_CPM_USBPCR_INCR_MASK
#define BF_CPM_USBPCR_INCR_MASK_V(e)                BF_CPM_USBPCR_INCR_MASK(BV_CPM_USBPCR_INCR_MASK__##e)
#define BFM_CPM_USBPCR_INCR_MASK_V(v)               BM_CPM_USBPCR_INCR_MASK
#define BP_CPM_USBPCR_TXRISETUNE                    26
#define BM_CPM_USBPCR_TXRISETUNE                    0x4000000
#define BF_CPM_USBPCR_TXRISETUNE(v)                 (((v) & 0x1) << 26)
#define BFM_CPM_USBPCR_TXRISETUNE(v)                BM_CPM_USBPCR_TXRISETUNE
#define BF_CPM_USBPCR_TXRISETUNE_V(e)               BF_CPM_USBPCR_TXRISETUNE(BV_CPM_USBPCR_TXRISETUNE__##e)
#define BFM_CPM_USBPCR_TXRISETUNE_V(v)              BM_CPM_USBPCR_TXRISETUNE
#define BP_CPM_USBPCR_COMMONONN                     25
#define BM_CPM_USBPCR_COMMONONN                     0x2000000
#define BF_CPM_USBPCR_COMMONONN(v)                  (((v) & 0x1) << 25)
#define BFM_CPM_USBPCR_COMMONONN(v)                 BM_CPM_USBPCR_COMMONONN
#define BF_CPM_USBPCR_COMMONONN_V(e)                BF_CPM_USBPCR_COMMONONN(BV_CPM_USBPCR_COMMONONN__##e)
#define BFM_CPM_USBPCR_COMMONONN_V(v)               BM_CPM_USBPCR_COMMONONN
#define BP_CPM_USBPCR_VBUSVLDEXT                    24
#define BM_CPM_USBPCR_VBUSVLDEXT                    0x1000000
#define BF_CPM_USBPCR_VBUSVLDEXT(v)                 (((v) & 0x1) << 24)
#define BFM_CPM_USBPCR_VBUSVLDEXT(v)                BM_CPM_USBPCR_VBUSVLDEXT
#define BF_CPM_USBPCR_VBUSVLDEXT_V(e)               BF_CPM_USBPCR_VBUSVLDEXT(BV_CPM_USBPCR_VBUSVLDEXT__##e)
#define BFM_CPM_USBPCR_VBUSVLDEXT_V(v)              BM_CPM_USBPCR_VBUSVLDEXT
#define BP_CPM_USBPCR_VBUSVLDEXTSEL                 23
#define BM_CPM_USBPCR_VBUSVLDEXTSEL                 0x800000
#define BF_CPM_USBPCR_VBUSVLDEXTSEL(v)              (((v) & 0x1) << 23)
#define BFM_CPM_USBPCR_VBUSVLDEXTSEL(v)             BM_CPM_USBPCR_VBUSVLDEXTSEL
#define BF_CPM_USBPCR_VBUSVLDEXTSEL_V(e)            BF_CPM_USBPCR_VBUSVLDEXTSEL(BV_CPM_USBPCR_VBUSVLDEXTSEL__##e)
#define BFM_CPM_USBPCR_VBUSVLDEXTSEL_V(v)           BM_CPM_USBPCR_VBUSVLDEXTSEL
#define BP_CPM_USBPCR_POR                           22
#define BM_CPM_USBPCR_POR                           0x400000
#define BF_CPM_USBPCR_POR(v)                        (((v) & 0x1) << 22)
#define BFM_CPM_USBPCR_POR(v)                       BM_CPM_USBPCR_POR
#define BF_CPM_USBPCR_POR_V(e)                      BF_CPM_USBPCR_POR(BV_CPM_USBPCR_POR__##e)
#define BFM_CPM_USBPCR_POR_V(v)                     BM_CPM_USBPCR_POR
#define BP_CPM_USBPCR_SIDDQ                         21
#define BM_CPM_USBPCR_SIDDQ                         0x200000
#define BF_CPM_USBPCR_SIDDQ(v)                      (((v) & 0x1) << 21)
#define BFM_CPM_USBPCR_SIDDQ(v)                     BM_CPM_USBPCR_SIDDQ
#define BF_CPM_USBPCR_SIDDQ_V(e)                    BF_CPM_USBPCR_SIDDQ(BV_CPM_USBPCR_SIDDQ__##e)
#define BFM_CPM_USBPCR_SIDDQ_V(v)                   BM_CPM_USBPCR_SIDDQ
#define BP_CPM_USBPCR_OTG_DISABLE                   20
#define BM_CPM_USBPCR_OTG_DISABLE                   0x100000
#define BF_CPM_USBPCR_OTG_DISABLE(v)                (((v) & 0x1) << 20)
#define BFM_CPM_USBPCR_OTG_DISABLE(v)               BM_CPM_USBPCR_OTG_DISABLE
#define BF_CPM_USBPCR_OTG_DISABLE_V(e)              BF_CPM_USBPCR_OTG_DISABLE(BV_CPM_USBPCR_OTG_DISABLE__##e)
#define BFM_CPM_USBPCR_OTG_DISABLE_V(v)             BM_CPM_USBPCR_OTG_DISABLE
#define BP_CPM_USBPCR_TXPREEMPHTUNE                 6
#define BM_CPM_USBPCR_TXPREEMPHTUNE                 0x40
#define BF_CPM_USBPCR_TXPREEMPHTUNE(v)              (((v) & 0x1) << 6)
#define BFM_CPM_USBPCR_TXPREEMPHTUNE(v)             BM_CPM_USBPCR_TXPREEMPHTUNE
#define BF_CPM_USBPCR_TXPREEMPHTUNE_V(e)            BF_CPM_USBPCR_TXPREEMPHTUNE(BV_CPM_USBPCR_TXPREEMPHTUNE__##e)
#define BFM_CPM_USBPCR_TXPREEMPHTUNE_V(v)           BM_CPM_USBPCR_TXPREEMPHTUNE

#define REG_CPM_USBRDT                  jz_reg(CPM_USBRDT)
#define JA_CPM_USBRDT                   (0xb0000000 + 0x40)
#define JT_CPM_USBRDT                   JIO_32_RW
#define JN_CPM_USBRDT                   CPM_USBRDT
#define JI_CPM_USBRDT                   
#define BP_CPM_USBRDT_RDT               0
#define BM_CPM_USBRDT_RDT               0x7fffff
#define BF_CPM_USBRDT_RDT(v)            (((v) & 0x7fffff) << 0)
#define BFM_CPM_USBRDT_RDT(v)           BM_CPM_USBRDT_RDT
#define BF_CPM_USBRDT_RDT_V(e)          BF_CPM_USBRDT_RDT(BV_CPM_USBRDT_RDT__##e)
#define BFM_CPM_USBRDT_RDT_V(v)         BM_CPM_USBRDT_RDT
#define BP_CPM_USBRDT_HB_MASK           26
#define BM_CPM_USBRDT_HB_MASK           0x4000000
#define BF_CPM_USBRDT_HB_MASK(v)        (((v) & 0x1) << 26)
#define BFM_CPM_USBRDT_HB_MASK(v)       BM_CPM_USBRDT_HB_MASK
#define BF_CPM_USBRDT_HB_MASK_V(e)      BF_CPM_USBRDT_HB_MASK(BV_CPM_USBRDT_HB_MASK__##e)
#define BFM_CPM_USBRDT_HB_MASK_V(v)     BM_CPM_USBRDT_HB_MASK
#define BP_CPM_USBRDT_VBFIL_LD_EN       25
#define BM_CPM_USBRDT_VBFIL_LD_EN       0x2000000
#define BF_CPM_USBRDT_VBFIL_LD_EN(v)    (((v) & 0x1) << 25)
#define BFM_CPM_USBRDT_VBFIL_LD_EN(v)   BM_CPM_USBRDT_VBFIL_LD_EN
#define BF_CPM_USBRDT_VBFIL_LD_EN_V(e)  BF_CPM_USBRDT_VBFIL_LD_EN(BV_CPM_USBRDT_VBFIL_LD_EN__##e)
#define BFM_CPM_USBRDT_VBFIL_LD_EN_V(v) BM_CPM_USBRDT_VBFIL_LD_EN
#define BP_CPM_USBRDT_IDDIG_EN          24
#define BM_CPM_USBRDT_IDDIG_EN          0x1000000
#define BF_CPM_USBRDT_IDDIG_EN(v)       (((v) & 0x1) << 24)
#define BFM_CPM_USBRDT_IDDIG_EN(v)      BM_CPM_USBRDT_IDDIG_EN
#define BF_CPM_USBRDT_IDDIG_EN_V(e)     BF_CPM_USBRDT_IDDIG_EN(BV_CPM_USBRDT_IDDIG_EN__##e)
#define BFM_CPM_USBRDT_IDDIG_EN_V(v)    BM_CPM_USBRDT_IDDIG_EN
#define BP_CPM_USBRDT_IDDIG_REG         23
#define BM_CPM_USBRDT_IDDIG_REG         0x800000
#define BF_CPM_USBRDT_IDDIG_REG(v)      (((v) & 0x1) << 23)
#define BFM_CPM_USBRDT_IDDIG_REG(v)     BM_CPM_USBRDT_IDDIG_REG
#define BF_CPM_USBRDT_IDDIG_REG_V(e)    BF_CPM_USBRDT_IDDIG_REG(BV_CPM_USBRDT_IDDIG_REG__##e)
#define BFM_CPM_USBRDT_IDDIG_REG_V(v)   BM_CPM_USBRDT_IDDIG_REG

#define REG_CPM_USBVBFIL                jz_reg(CPM_USBVBFIL)
#define JA_CPM_USBVBFIL                 (0xb0000000 + 0x44)
#define JT_CPM_USBVBFIL                 JIO_32_RW
#define JN_CPM_USBVBFIL                 CPM_USBVBFIL
#define JI_CPM_USBVBFIL                 
#define BP_CPM_USBVBFIL_IDDIGFIL        16
#define BM_CPM_USBVBFIL_IDDIGFIL        0xffff0000
#define BF_CPM_USBVBFIL_IDDIGFIL(v)     (((v) & 0xffff) << 16)
#define BFM_CPM_USBVBFIL_IDDIGFIL(v)    BM_CPM_USBVBFIL_IDDIGFIL
#define BF_CPM_USBVBFIL_IDDIGFIL_V(e)   BF_CPM_USBVBFIL_IDDIGFIL(BV_CPM_USBVBFIL_IDDIGFIL__##e)
#define BFM_CPM_USBVBFIL_IDDIGFIL_V(v)  BM_CPM_USBVBFIL_IDDIGFIL
#define BP_CPM_USBVBFIL_VBFIL           0
#define BM_CPM_USBVBFIL_VBFIL           0xffff
#define BF_CPM_USBVBFIL_VBFIL(v)        (((v) & 0xffff) << 0)
#define BFM_CPM_USBVBFIL_VBFIL(v)       BM_CPM_USBVBFIL_VBFIL
#define BF_CPM_USBVBFIL_VBFIL_V(e)      BF_CPM_USBVBFIL_VBFIL(BV_CPM_USBVBFIL_VBFIL__##e)
#define BFM_CPM_USBVBFIL_VBFIL_V(v)     BM_CPM_USBVBFIL_VBFIL

#define REG_CPM_USBPCR1                     jz_reg(CPM_USBPCR1)
#define JA_CPM_USBPCR1                      (0xb0000000 + 0x48)
#define JT_CPM_USBPCR1                      JIO_32_RW
#define JN_CPM_USBPCR1                      CPM_USBPCR1
#define JI_CPM_USBPCR1                      
#define BP_CPM_USBPCR1_REFCLK_SEL           26
#define BM_CPM_USBPCR1_REFCLK_SEL           0xc000000
#define BV_CPM_USBPCR1_REFCLK_SEL__CLKCORE  0x2
#define BV_CPM_USBPCR1_REFCLK_SEL__EXTERNAL 0x1
#define BV_CPM_USBPCR1_REFCLK_SEL__CRYSTAL  0x0
#define BF_CPM_USBPCR1_REFCLK_SEL(v)        (((v) & 0x3) << 26)
#define BFM_CPM_USBPCR1_REFCLK_SEL(v)       BM_CPM_USBPCR1_REFCLK_SEL
#define BF_CPM_USBPCR1_REFCLK_SEL_V(e)      BF_CPM_USBPCR1_REFCLK_SEL(BV_CPM_USBPCR1_REFCLK_SEL__##e)
#define BFM_CPM_USBPCR1_REFCLK_SEL_V(v)     BM_CPM_USBPCR1_REFCLK_SEL
#define BP_CPM_USBPCR1_REFCLK_DIV           24
#define BM_CPM_USBPCR1_REFCLK_DIV           0x3000000
#define BV_CPM_USBPCR1_REFCLK_DIV__48MHZ    0x2
#define BV_CPM_USBPCR1_REFCLK_DIV__24MHZ    0x1
#define BV_CPM_USBPCR1_REFCLK_DIV__12MHZ    0x0
#define BF_CPM_USBPCR1_REFCLK_DIV(v)        (((v) & 0x3) << 24)
#define BFM_CPM_USBPCR1_REFCLK_DIV(v)       BM_CPM_USBPCR1_REFCLK_DIV
#define BF_CPM_USBPCR1_REFCLK_DIV_V(e)      BF_CPM_USBPCR1_REFCLK_DIV(BV_CPM_USBPCR1_REFCLK_DIV__##e)
#define BFM_CPM_USBPCR1_REFCLK_DIV_V(v)     BM_CPM_USBPCR1_REFCLK_DIV
#define BP_CPM_USBPCR1_BVLD_REG             31
#define BM_CPM_USBPCR1_BVLD_REG             0x80000000
#define BF_CPM_USBPCR1_BVLD_REG(v)          (((v) & 0x1) << 31)
#define BFM_CPM_USBPCR1_BVLD_REG(v)         BM_CPM_USBPCR1_BVLD_REG
#define BF_CPM_USBPCR1_BVLD_REG_V(e)        BF_CPM_USBPCR1_BVLD_REG(BV_CPM_USBPCR1_BVLD_REG__##e)
#define BFM_CPM_USBPCR1_BVLD_REG_V(v)       BM_CPM_USBPCR1_BVLD_REG
#define BP_CPM_USBPCR1_PORT_RST             21
#define BM_CPM_USBPCR1_PORT_RST             0x200000
#define BF_CPM_USBPCR1_PORT_RST(v)          (((v) & 0x1) << 21)
#define BFM_CPM_USBPCR1_PORT_RST(v)         BM_CPM_USBPCR1_PORT_RST
#define BF_CPM_USBPCR1_PORT_RST_V(e)        BF_CPM_USBPCR1_PORT_RST(BV_CPM_USBPCR1_PORT_RST__##e)
#define BFM_CPM_USBPCR1_PORT_RST_V(v)       BM_CPM_USBPCR1_PORT_RST
#define BP_CPM_USBPCR1_WORD_IF              19
#define BM_CPM_USBPCR1_WORD_IF              0x80000
#define BV_CPM_USBPCR1_WORD_IF__16BIT       0x1
#define BV_CPM_USBPCR1_WORD_IF__8BIT        0x0
#define BF_CPM_USBPCR1_WORD_IF(v)           (((v) & 0x1) << 19)
#define BFM_CPM_USBPCR1_WORD_IF(v)          BM_CPM_USBPCR1_WORD_IF
#define BF_CPM_USBPCR1_WORD_IF_V(e)         BF_CPM_USBPCR1_WORD_IF(BV_CPM_USBPCR1_WORD_IF__##e)
#define BFM_CPM_USBPCR1_WORD_IF_V(v)        BM_CPM_USBPCR1_WORD_IF

#define REG_CPM_APCR                jz_reg(CPM_APCR)
#define JA_CPM_APCR                 (0xb0000000 + 0x10)
#define JT_CPM_APCR                 JIO_32_RW
#define JN_CPM_APCR                 CPM_APCR
#define JI_CPM_APCR                 
#define BP_CPM_APCR_PLLM            24
#define BM_CPM_APCR_PLLM            0x7f000000
#define BF_CPM_APCR_PLLM(v)         (((v) & 0x7f) << 24)
#define BFM_CPM_APCR_PLLM(v)        BM_CPM_APCR_PLLM
#define BF_CPM_APCR_PLLM_V(e)       BF_CPM_APCR_PLLM(BV_CPM_APCR_PLLM__##e)
#define BFM_CPM_APCR_PLLM_V(v)      BM_CPM_APCR_PLLM
#define BP_CPM_APCR_PLLN            18
#define BM_CPM_APCR_PLLN            0x7c0000
#define BF_CPM_APCR_PLLN(v)         (((v) & 0x1f) << 18)
#define BFM_CPM_APCR_PLLN(v)        BM_CPM_APCR_PLLN
#define BF_CPM_APCR_PLLN_V(e)       BF_CPM_APCR_PLLN(BV_CPM_APCR_PLLN__##e)
#define BFM_CPM_APCR_PLLN_V(v)      BM_CPM_APCR_PLLN
#define BP_CPM_APCR_PLLOD           16
#define BM_CPM_APCR_PLLOD           0x30000
#define BF_CPM_APCR_PLLOD(v)        (((v) & 0x3) << 16)
#define BFM_CPM_APCR_PLLOD(v)       BM_CPM_APCR_PLLOD
#define BF_CPM_APCR_PLLOD_V(e)      BF_CPM_APCR_PLLOD(BV_CPM_APCR_PLLOD__##e)
#define BFM_CPM_APCR_PLLOD_V(v)     BM_CPM_APCR_PLLOD
#define BP_CPM_APCR_PLLST           0
#define BM_CPM_APCR_PLLST           0xff
#define BF_CPM_APCR_PLLST(v)        (((v) & 0xff) << 0)
#define BFM_CPM_APCR_PLLST(v)       BM_CPM_APCR_PLLST
#define BF_CPM_APCR_PLLST_V(e)      BF_CPM_APCR_PLLST(BV_CPM_APCR_PLLST__##e)
#define BFM_CPM_APCR_PLLST_V(v)     BM_CPM_APCR_PLLST
#define BP_CPM_APCR_BS              31
#define BM_CPM_APCR_BS              0x80000000
#define BF_CPM_APCR_BS(v)           (((v) & 0x1) << 31)
#define BFM_CPM_APCR_BS(v)          BM_CPM_APCR_BS
#define BF_CPM_APCR_BS_V(e)         BF_CPM_APCR_BS(BV_CPM_APCR_BS__##e)
#define BFM_CPM_APCR_BS_V(v)        BM_CPM_APCR_BS
#define BP_CPM_APCR_LOCK            15
#define BM_CPM_APCR_LOCK            0x8000
#define BF_CPM_APCR_LOCK(v)         (((v) & 0x1) << 15)
#define BFM_CPM_APCR_LOCK(v)        BM_CPM_APCR_LOCK
#define BF_CPM_APCR_LOCK_V(e)       BF_CPM_APCR_LOCK(BV_CPM_APCR_LOCK__##e)
#define BFM_CPM_APCR_LOCK_V(v)      BM_CPM_APCR_LOCK
#define BP_CPM_APCR_ON              10
#define BM_CPM_APCR_ON              0x400
#define BF_CPM_APCR_ON(v)           (((v) & 0x1) << 10)
#define BFM_CPM_APCR_ON(v)          BM_CPM_APCR_ON
#define BF_CPM_APCR_ON_V(e)         BF_CPM_APCR_ON(BV_CPM_APCR_ON__##e)
#define BFM_CPM_APCR_ON_V(v)        BM_CPM_APCR_ON
#define BP_CPM_APCR_BYPASS          9
#define BM_CPM_APCR_BYPASS          0x200
#define BF_CPM_APCR_BYPASS(v)       (((v) & 0x1) << 9)
#define BFM_CPM_APCR_BYPASS(v)      BM_CPM_APCR_BYPASS
#define BF_CPM_APCR_BYPASS_V(e)     BF_CPM_APCR_BYPASS(BV_CPM_APCR_BYPASS__##e)
#define BFM_CPM_APCR_BYPASS_V(v)    BM_CPM_APCR_BYPASS
#define BP_CPM_APCR_ENABLE          8
#define BM_CPM_APCR_ENABLE          0x100
#define BF_CPM_APCR_ENABLE(v)       (((v) & 0x1) << 8)
#define BFM_CPM_APCR_ENABLE(v)      BM_CPM_APCR_ENABLE
#define BF_CPM_APCR_ENABLE_V(e)     BF_CPM_APCR_ENABLE(BV_CPM_APCR_ENABLE__##e)
#define BFM_CPM_APCR_ENABLE_V(v)    BM_CPM_APCR_ENABLE

#define REG_CPM_MPCR                jz_reg(CPM_MPCR)
#define JA_CPM_MPCR                 (0xb0000000 + 0x14)
#define JT_CPM_MPCR                 JIO_32_RW
#define JN_CPM_MPCR                 CPM_MPCR
#define JI_CPM_MPCR                 
#define BP_CPM_MPCR_PLLM            24
#define BM_CPM_MPCR_PLLM            0x7f000000
#define BF_CPM_MPCR_PLLM(v)         (((v) & 0x7f) << 24)
#define BFM_CPM_MPCR_PLLM(v)        BM_CPM_MPCR_PLLM
#define BF_CPM_MPCR_PLLM_V(e)       BF_CPM_MPCR_PLLM(BV_CPM_MPCR_PLLM__##e)
#define BFM_CPM_MPCR_PLLM_V(v)      BM_CPM_MPCR_PLLM
#define BP_CPM_MPCR_PLLN            18
#define BM_CPM_MPCR_PLLN            0x7c0000
#define BF_CPM_MPCR_PLLN(v)         (((v) & 0x1f) << 18)
#define BFM_CPM_MPCR_PLLN(v)        BM_CPM_MPCR_PLLN
#define BF_CPM_MPCR_PLLN_V(e)       BF_CPM_MPCR_PLLN(BV_CPM_MPCR_PLLN__##e)
#define BFM_CPM_MPCR_PLLN_V(v)      BM_CPM_MPCR_PLLN
#define BP_CPM_MPCR_PLLOD           16
#define BM_CPM_MPCR_PLLOD           0x30000
#define BF_CPM_MPCR_PLLOD(v)        (((v) & 0x3) << 16)
#define BFM_CPM_MPCR_PLLOD(v)       BM_CPM_MPCR_PLLOD
#define BF_CPM_MPCR_PLLOD_V(e)      BF_CPM_MPCR_PLLOD(BV_CPM_MPCR_PLLOD__##e)
#define BFM_CPM_MPCR_PLLOD_V(v)     BM_CPM_MPCR_PLLOD
#define BP_CPM_MPCR_BS              31
#define BM_CPM_MPCR_BS              0x80000000
#define BF_CPM_MPCR_BS(v)           (((v) & 0x1) << 31)
#define BFM_CPM_MPCR_BS(v)          BM_CPM_MPCR_BS
#define BF_CPM_MPCR_BS_V(e)         BF_CPM_MPCR_BS(BV_CPM_MPCR_BS__##e)
#define BFM_CPM_MPCR_BS_V(v)        BM_CPM_MPCR_BS
#define BP_CPM_MPCR_ENABLE          7
#define BM_CPM_MPCR_ENABLE          0x80
#define BF_CPM_MPCR_ENABLE(v)       (((v) & 0x1) << 7)
#define BFM_CPM_MPCR_ENABLE(v)      BM_CPM_MPCR_ENABLE
#define BF_CPM_MPCR_ENABLE_V(e)     BF_CPM_MPCR_ENABLE(BV_CPM_MPCR_ENABLE__##e)
#define BFM_CPM_MPCR_ENABLE_V(v)    BM_CPM_MPCR_ENABLE
#define BP_CPM_MPCR_BYPASS          6
#define BM_CPM_MPCR_BYPASS          0x40
#define BF_CPM_MPCR_BYPASS(v)       (((v) & 0x1) << 6)
#define BFM_CPM_MPCR_BYPASS(v)      BM_CPM_MPCR_BYPASS
#define BF_CPM_MPCR_BYPASS_V(e)     BF_CPM_MPCR_BYPASS(BV_CPM_MPCR_BYPASS__##e)
#define BFM_CPM_MPCR_BYPASS_V(v)    BM_CPM_MPCR_BYPASS
#define BP_CPM_MPCR_LOCK            1
#define BM_CPM_MPCR_LOCK            0x2
#define BF_CPM_MPCR_LOCK(v)         (((v) & 0x1) << 1)
#define BFM_CPM_MPCR_LOCK(v)        BM_CPM_MPCR_LOCK
#define BF_CPM_MPCR_LOCK_V(e)       BF_CPM_MPCR_LOCK(BV_CPM_MPCR_LOCK__##e)
#define BFM_CPM_MPCR_LOCK_V(v)      BM_CPM_MPCR_LOCK
#define BP_CPM_MPCR_ON              0
#define BM_CPM_MPCR_ON              0x1
#define BF_CPM_MPCR_ON(v)           (((v) & 0x1) << 0)
#define BFM_CPM_MPCR_ON(v)          BM_CPM_MPCR_ON
#define BF_CPM_MPCR_ON_V(e)         BF_CPM_MPCR_ON(BV_CPM_MPCR_ON__##e)
#define BFM_CPM_MPCR_ON_V(v)        BM_CPM_MPCR_ON

#define REG_CPM_LCR             jz_reg(CPM_LCR)
#define JA_CPM_LCR              (0xb0000000 + 0x4)
#define JT_CPM_LCR              JIO_32_RW
#define JN_CPM_LCR              CPM_LCR
#define JI_CPM_LCR              
#define BP_CPM_LCR_PST          8
#define BM_CPM_LCR_PST          0xfff00
#define BF_CPM_LCR_PST(v)       (((v) & 0xfff) << 8)
#define BFM_CPM_LCR_PST(v)      BM_CPM_LCR_PST
#define BF_CPM_LCR_PST_V(e)     BF_CPM_LCR_PST(BV_CPM_LCR_PST__##e)
#define BFM_CPM_LCR_PST_V(v)    BM_CPM_LCR_PST
#define BP_CPM_LCR_LPM          0
#define BM_CPM_LCR_LPM          0x3
#define BV_CPM_LCR_LPM__IDLE    0x0
#define BV_CPM_LCR_LPM__SLEEP   0x1
#define BF_CPM_LCR_LPM(v)       (((v) & 0x3) << 0)
#define BFM_CPM_LCR_LPM(v)      BM_CPM_LCR_LPM
#define BF_CPM_LCR_LPM_V(e)     BF_CPM_LCR_LPM(BV_CPM_LCR_LPM__##e)
#define BFM_CPM_LCR_LPM_V(v)    BM_CPM_LCR_LPM

#define REG_CPM_PSWC0ST jz_reg(CPM_PSWC0ST)
#define JA_CPM_PSWC0ST  (0xb0000000 + 0x90)
#define JT_CPM_PSWC0ST  JIO_32_RW
#define JN_CPM_PSWC0ST  CPM_PSWC0ST
#define JI_CPM_PSWC0ST  

#define REG_CPM_PSWC1ST jz_reg(CPM_PSWC1ST)
#define JA_CPM_PSWC1ST  (0xb0000000 + 0x94)
#define JT_CPM_PSWC1ST  JIO_32_RW
#define JN_CPM_PSWC1ST  CPM_PSWC1ST
#define JI_CPM_PSWC1ST  

#define REG_CPM_PSWC2ST jz_reg(CPM_PSWC2ST)
#define JA_CPM_PSWC2ST  (0xb0000000 + 0x98)
#define JT_CPM_PSWC2ST  JIO_32_RW
#define JN_CPM_PSWC2ST  CPM_PSWC2ST
#define JI_CPM_PSWC2ST  

#define REG_CPM_PSWC3ST jz_reg(CPM_PSWC3ST)
#define JA_CPM_PSWC3ST  (0xb0000000 + 0x9c)
#define JT_CPM_PSWC3ST  JIO_32_RW
#define JN_CPM_PSWC3ST  CPM_PSWC3ST
#define JI_CPM_PSWC3ST  

#define REG_CPM_CLKGR               jz_reg(CPM_CLKGR)
#define JA_CPM_CLKGR                (0xb0000000 + 0x20)
#define JT_CPM_CLKGR                JIO_32_RW
#define JN_CPM_CLKGR                CPM_CLKGR
#define JI_CPM_CLKGR                
#define BP_CPM_CLKGR_DDR            31
#define BM_CPM_CLKGR_DDR            0x80000000
#define BF_CPM_CLKGR_DDR(v)         (((v) & 0x1) << 31)
#define BFM_CPM_CLKGR_DDR(v)        BM_CPM_CLKGR_DDR
#define BF_CPM_CLKGR_DDR_V(e)       BF_CPM_CLKGR_DDR(BV_CPM_CLKGR_DDR__##e)
#define BFM_CPM_CLKGR_DDR_V(v)      BM_CPM_CLKGR_DDR
#define BP_CPM_CLKGR_CPU_BIT        30
#define BM_CPM_CLKGR_CPU_BIT        0x40000000
#define BF_CPM_CLKGR_CPU_BIT(v)     (((v) & 0x1) << 30)
#define BFM_CPM_CLKGR_CPU_BIT(v)    BM_CPM_CLKGR_CPU_BIT
#define BF_CPM_CLKGR_CPU_BIT_V(e)   BF_CPM_CLKGR_CPU_BIT(BV_CPM_CLKGR_CPU_BIT__##e)
#define BFM_CPM_CLKGR_CPU_BIT_V(v)  BM_CPM_CLKGR_CPU_BIT
#define BP_CPM_CLKGR_AHB0           29
#define BM_CPM_CLKGR_AHB0           0x20000000
#define BF_CPM_CLKGR_AHB0(v)        (((v) & 0x1) << 29)
#define BFM_CPM_CLKGR_AHB0(v)       BM_CPM_CLKGR_AHB0
#define BF_CPM_CLKGR_AHB0_V(e)      BF_CPM_CLKGR_AHB0(BV_CPM_CLKGR_AHB0__##e)
#define BFM_CPM_CLKGR_AHB0_V(v)     BM_CPM_CLKGR_AHB0
#define BP_CPM_CLKGR_APB0           28
#define BM_CPM_CLKGR_APB0           0x10000000
#define BF_CPM_CLKGR_APB0(v)        (((v) & 0x1) << 28)
#define BFM_CPM_CLKGR_APB0(v)       BM_CPM_CLKGR_APB0
#define BF_CPM_CLKGR_APB0_V(e)      BF_CPM_CLKGR_APB0(BV_CPM_CLKGR_APB0__##e)
#define BFM_CPM_CLKGR_APB0_V(v)     BM_CPM_CLKGR_APB0
#define BP_CPM_CLKGR_RTC            27
#define BM_CPM_CLKGR_RTC            0x8000000
#define BF_CPM_CLKGR_RTC(v)         (((v) & 0x1) << 27)
#define BFM_CPM_CLKGR_RTC(v)        BM_CPM_CLKGR_RTC
#define BF_CPM_CLKGR_RTC_V(e)       BF_CPM_CLKGR_RTC(BV_CPM_CLKGR_RTC__##e)
#define BFM_CPM_CLKGR_RTC_V(v)      BM_CPM_CLKGR_RTC
#define BP_CPM_CLKGR_PCM            26
#define BM_CPM_CLKGR_PCM            0x4000000
#define BF_CPM_CLKGR_PCM(v)         (((v) & 0x1) << 26)
#define BFM_CPM_CLKGR_PCM(v)        BM_CPM_CLKGR_PCM
#define BF_CPM_CLKGR_PCM_V(e)       BF_CPM_CLKGR_PCM(BV_CPM_CLKGR_PCM__##e)
#define BFM_CPM_CLKGR_PCM_V(v)      BM_CPM_CLKGR_PCM
#define BP_CPM_CLKGR_MAC            25
#define BM_CPM_CLKGR_MAC            0x2000000
#define BF_CPM_CLKGR_MAC(v)         (((v) & 0x1) << 25)
#define BFM_CPM_CLKGR_MAC(v)        BM_CPM_CLKGR_MAC
#define BF_CPM_CLKGR_MAC_V(e)       BF_CPM_CLKGR_MAC(BV_CPM_CLKGR_MAC__##e)
#define BFM_CPM_CLKGR_MAC_V(v)      BM_CPM_CLKGR_MAC
#define BP_CPM_CLKGR_AES            24
#define BM_CPM_CLKGR_AES            0x1000000
#define BF_CPM_CLKGR_AES(v)         (((v) & 0x1) << 24)
#define BFM_CPM_CLKGR_AES(v)        BM_CPM_CLKGR_AES
#define BF_CPM_CLKGR_AES_V(e)       BF_CPM_CLKGR_AES(BV_CPM_CLKGR_AES__##e)
#define BFM_CPM_CLKGR_AES_V(v)      BM_CPM_CLKGR_AES
#define BP_CPM_CLKGR_LCD            23
#define BM_CPM_CLKGR_LCD            0x800000
#define BF_CPM_CLKGR_LCD(v)         (((v) & 0x1) << 23)
#define BFM_CPM_CLKGR_LCD(v)        BM_CPM_CLKGR_LCD
#define BF_CPM_CLKGR_LCD_V(e)       BF_CPM_CLKGR_LCD(BV_CPM_CLKGR_LCD__##e)
#define BFM_CPM_CLKGR_LCD_V(v)      BM_CPM_CLKGR_LCD
#define BP_CPM_CLKGR_CIM            22
#define BM_CPM_CLKGR_CIM            0x400000
#define BF_CPM_CLKGR_CIM(v)         (((v) & 0x1) << 22)
#define BFM_CPM_CLKGR_CIM(v)        BM_CPM_CLKGR_CIM
#define BF_CPM_CLKGR_CIM_V(e)       BF_CPM_CLKGR_CIM(BV_CPM_CLKGR_CIM__##e)
#define BFM_CPM_CLKGR_CIM_V(v)      BM_CPM_CLKGR_CIM
#define BP_CPM_CLKGR_PDMA           21
#define BM_CPM_CLKGR_PDMA           0x200000
#define BF_CPM_CLKGR_PDMA(v)        (((v) & 0x1) << 21)
#define BFM_CPM_CLKGR_PDMA(v)       BM_CPM_CLKGR_PDMA
#define BF_CPM_CLKGR_PDMA_V(e)      BF_CPM_CLKGR_PDMA(BV_CPM_CLKGR_PDMA__##e)
#define BFM_CPM_CLKGR_PDMA_V(v)     BM_CPM_CLKGR_PDMA
#define BP_CPM_CLKGR_OST            20
#define BM_CPM_CLKGR_OST            0x100000
#define BF_CPM_CLKGR_OST(v)         (((v) & 0x1) << 20)
#define BFM_CPM_CLKGR_OST(v)        BM_CPM_CLKGR_OST
#define BF_CPM_CLKGR_OST_V(e)       BF_CPM_CLKGR_OST(BV_CPM_CLKGR_OST__##e)
#define BFM_CPM_CLKGR_OST_V(v)      BM_CPM_CLKGR_OST
#define BP_CPM_CLKGR_SSI            19
#define BM_CPM_CLKGR_SSI            0x80000
#define BF_CPM_CLKGR_SSI(v)         (((v) & 0x1) << 19)
#define BFM_CPM_CLKGR_SSI(v)        BM_CPM_CLKGR_SSI
#define BF_CPM_CLKGR_SSI_V(e)       BF_CPM_CLKGR_SSI(BV_CPM_CLKGR_SSI__##e)
#define BFM_CPM_CLKGR_SSI_V(v)      BM_CPM_CLKGR_SSI
#define BP_CPM_CLKGR_TCU            18
#define BM_CPM_CLKGR_TCU            0x40000
#define BF_CPM_CLKGR_TCU(v)         (((v) & 0x1) << 18)
#define BFM_CPM_CLKGR_TCU(v)        BM_CPM_CLKGR_TCU
#define BF_CPM_CLKGR_TCU_V(e)       BF_CPM_CLKGR_TCU(BV_CPM_CLKGR_TCU__##e)
#define BFM_CPM_CLKGR_TCU_V(v)      BM_CPM_CLKGR_TCU
#define BP_CPM_CLKGR_DMIC           17
#define BM_CPM_CLKGR_DMIC           0x20000
#define BF_CPM_CLKGR_DMIC(v)        (((v) & 0x1) << 17)
#define BFM_CPM_CLKGR_DMIC(v)       BM_CPM_CLKGR_DMIC
#define BF_CPM_CLKGR_DMIC_V(e)      BF_CPM_CLKGR_DMIC(BV_CPM_CLKGR_DMIC__##e)
#define BFM_CPM_CLKGR_DMIC_V(v)     BM_CPM_CLKGR_DMIC
#define BP_CPM_CLKGR_UART2          16
#define BM_CPM_CLKGR_UART2          0x10000
#define BF_CPM_CLKGR_UART2(v)       (((v) & 0x1) << 16)
#define BFM_CPM_CLKGR_UART2(v)      BM_CPM_CLKGR_UART2
#define BF_CPM_CLKGR_UART2_V(e)     BF_CPM_CLKGR_UART2(BV_CPM_CLKGR_UART2__##e)
#define BFM_CPM_CLKGR_UART2_V(v)    BM_CPM_CLKGR_UART2
#define BP_CPM_CLKGR_UART1          15
#define BM_CPM_CLKGR_UART1          0x8000
#define BF_CPM_CLKGR_UART1(v)       (((v) & 0x1) << 15)
#define BFM_CPM_CLKGR_UART1(v)      BM_CPM_CLKGR_UART1
#define BF_CPM_CLKGR_UART1_V(e)     BF_CPM_CLKGR_UART1(BV_CPM_CLKGR_UART1__##e)
#define BFM_CPM_CLKGR_UART1_V(v)    BM_CPM_CLKGR_UART1
#define BP_CPM_CLKGR_UART0          14
#define BM_CPM_CLKGR_UART0          0x4000
#define BF_CPM_CLKGR_UART0(v)       (((v) & 0x1) << 14)
#define BFM_CPM_CLKGR_UART0(v)      BM_CPM_CLKGR_UART0
#define BF_CPM_CLKGR_UART0_V(e)     BF_CPM_CLKGR_UART0(BV_CPM_CLKGR_UART0__##e)
#define BFM_CPM_CLKGR_UART0_V(v)    BM_CPM_CLKGR_UART0
#define BP_CPM_CLKGR_JPEG           12
#define BM_CPM_CLKGR_JPEG           0x1000
#define BF_CPM_CLKGR_JPEG(v)        (((v) & 0x1) << 12)
#define BFM_CPM_CLKGR_JPEG(v)       BM_CPM_CLKGR_JPEG
#define BF_CPM_CLKGR_JPEG_V(e)      BF_CPM_CLKGR_JPEG(BV_CPM_CLKGR_JPEG__##e)
#define BFM_CPM_CLKGR_JPEG_V(v)     BM_CPM_CLKGR_JPEG
#define BP_CPM_CLKGR_AIC            11
#define BM_CPM_CLKGR_AIC            0x800
#define BF_CPM_CLKGR_AIC(v)         (((v) & 0x1) << 11)
#define BFM_CPM_CLKGR_AIC(v)        BM_CPM_CLKGR_AIC
#define BF_CPM_CLKGR_AIC_V(e)       BF_CPM_CLKGR_AIC(BV_CPM_CLKGR_AIC__##e)
#define BFM_CPM_CLKGR_AIC_V(v)      BM_CPM_CLKGR_AIC
#define BP_CPM_CLKGR_I2C2           9
#define BM_CPM_CLKGR_I2C2           0x200
#define BF_CPM_CLKGR_I2C2(v)        (((v) & 0x1) << 9)
#define BFM_CPM_CLKGR_I2C2(v)       BM_CPM_CLKGR_I2C2
#define BF_CPM_CLKGR_I2C2_V(e)      BF_CPM_CLKGR_I2C2(BV_CPM_CLKGR_I2C2__##e)
#define BFM_CPM_CLKGR_I2C2_V(v)     BM_CPM_CLKGR_I2C2
#define BP_CPM_CLKGR_I2C1           8
#define BM_CPM_CLKGR_I2C1           0x100
#define BF_CPM_CLKGR_I2C1(v)        (((v) & 0x1) << 8)
#define BFM_CPM_CLKGR_I2C1(v)       BM_CPM_CLKGR_I2C1
#define BF_CPM_CLKGR_I2C1_V(e)      BF_CPM_CLKGR_I2C1(BV_CPM_CLKGR_I2C1__##e)
#define BFM_CPM_CLKGR_I2C1_V(v)     BM_CPM_CLKGR_I2C1
#define BP_CPM_CLKGR_I2C0           7
#define BM_CPM_CLKGR_I2C0           0x80
#define BF_CPM_CLKGR_I2C0(v)        (((v) & 0x1) << 7)
#define BFM_CPM_CLKGR_I2C0(v)       BM_CPM_CLKGR_I2C0
#define BF_CPM_CLKGR_I2C0_V(e)      BF_CPM_CLKGR_I2C0(BV_CPM_CLKGR_I2C0__##e)
#define BFM_CPM_CLKGR_I2C0_V(v)     BM_CPM_CLKGR_I2C0
#define BP_CPM_CLKGR_SCC            6
#define BM_CPM_CLKGR_SCC            0x40
#define BF_CPM_CLKGR_SCC(v)         (((v) & 0x1) << 6)
#define BFM_CPM_CLKGR_SCC(v)        BM_CPM_CLKGR_SCC
#define BF_CPM_CLKGR_SCC_V(e)       BF_CPM_CLKGR_SCC(BV_CPM_CLKGR_SCC__##e)
#define BFM_CPM_CLKGR_SCC_V(v)      BM_CPM_CLKGR_SCC
#define BP_CPM_CLKGR_MSC1           5
#define BM_CPM_CLKGR_MSC1           0x20
#define BF_CPM_CLKGR_MSC1(v)        (((v) & 0x1) << 5)
#define BFM_CPM_CLKGR_MSC1(v)       BM_CPM_CLKGR_MSC1
#define BF_CPM_CLKGR_MSC1_V(e)      BF_CPM_CLKGR_MSC1(BV_CPM_CLKGR_MSC1__##e)
#define BFM_CPM_CLKGR_MSC1_V(v)     BM_CPM_CLKGR_MSC1
#define BP_CPM_CLKGR_MSC0           4
#define BM_CPM_CLKGR_MSC0           0x10
#define BF_CPM_CLKGR_MSC0(v)        (((v) & 0x1) << 4)
#define BFM_CPM_CLKGR_MSC0(v)       BM_CPM_CLKGR_MSC0
#define BF_CPM_CLKGR_MSC0_V(e)      BF_CPM_CLKGR_MSC0(BV_CPM_CLKGR_MSC0__##e)
#define BFM_CPM_CLKGR_MSC0_V(v)     BM_CPM_CLKGR_MSC0
#define BP_CPM_CLKGR_OTG            3
#define BM_CPM_CLKGR_OTG            0x8
#define BF_CPM_CLKGR_OTG(v)         (((v) & 0x1) << 3)
#define BFM_CPM_CLKGR_OTG(v)        BM_CPM_CLKGR_OTG
#define BF_CPM_CLKGR_OTG_V(e)       BF_CPM_CLKGR_OTG(BV_CPM_CLKGR_OTG__##e)
#define BFM_CPM_CLKGR_OTG_V(v)      BM_CPM_CLKGR_OTG
#define BP_CPM_CLKGR_SFC            2
#define BM_CPM_CLKGR_SFC            0x4
#define BF_CPM_CLKGR_SFC(v)         (((v) & 0x1) << 2)
#define BFM_CPM_CLKGR_SFC(v)        BM_CPM_CLKGR_SFC
#define BF_CPM_CLKGR_SFC_V(e)       BF_CPM_CLKGR_SFC(BV_CPM_CLKGR_SFC__##e)
#define BFM_CPM_CLKGR_SFC_V(v)      BM_CPM_CLKGR_SFC
#define BP_CPM_CLKGR_EFUSE          1
#define BM_CPM_CLKGR_EFUSE          0x2
#define BF_CPM_CLKGR_EFUSE(v)       (((v) & 0x1) << 1)
#define BFM_CPM_CLKGR_EFUSE(v)      BM_CPM_CLKGR_EFUSE
#define BF_CPM_CLKGR_EFUSE_V(e)     BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e)
#define BFM_CPM_CLKGR_EFUSE_V(v)    BM_CPM_CLKGR_EFUSE

#define REG_CPM_SRBC                jz_reg(CPM_SRBC)
#define JA_CPM_SRBC                 (0xb0000000 + 0xc4)
#define JT_CPM_SRBC                 JIO_32_RW
#define JN_CPM_SRBC                 CPM_SRBC
#define JI_CPM_SRBC                 
#define BP_CPM_SRBC_JPEG_SR         31
#define BM_CPM_SRBC_JPEG_SR         0x80000000
#define BF_CPM_SRBC_JPEG_SR(v)      (((v) & 0x1) << 31)
#define BFM_CPM_SRBC_JPEG_SR(v)     BM_CPM_SRBC_JPEG_SR
#define BF_CPM_SRBC_JPEG_SR_V(e)    BF_CPM_SRBC_JPEG_SR(BV_CPM_SRBC_JPEG_SR__##e)
#define BFM_CPM_SRBC_JPEG_SR_V(v)   BM_CPM_SRBC_JPEG_SR
#define BP_CPM_SRBC_JPEG_STOP       30
#define BM_CPM_SRBC_JPEG_STOP       0x40000000
#define BF_CPM_SRBC_JPEG_STOP(v)    (((v) & 0x1) << 30)
#define BFM_CPM_SRBC_JPEG_STOP(v)   BM_CPM_SRBC_JPEG_STOP
#define BF_CPM_SRBC_JPEG_STOP_V(e)  BF_CPM_SRBC_JPEG_STOP(BV_CPM_SRBC_JPEG_STOP__##e)
#define BFM_CPM_SRBC_JPEG_STOP_V(v) BM_CPM_SRBC_JPEG_STOP
#define BP_CPM_SRBC_JPEG_ACK        29
#define BM_CPM_SRBC_JPEG_ACK        0x20000000
#define BF_CPM_SRBC_JPEG_ACK(v)     (((v) & 0x1) << 29)
#define BFM_CPM_SRBC_JPEG_ACK(v)    BM_CPM_SRBC_JPEG_ACK
#define BF_CPM_SRBC_JPEG_ACK_V(e)   BF_CPM_SRBC_JPEG_ACK(BV_CPM_SRBC_JPEG_ACK__##e)
#define BFM_CPM_SRBC_JPEG_ACK_V(v)  BM_CPM_SRBC_JPEG_ACK
#define BP_CPM_SRBC_LCD_SR          25
#define BM_CPM_SRBC_LCD_SR          0x2000000
#define BF_CPM_SRBC_LCD_SR(v)       (((v) & 0x1) << 25)
#define BFM_CPM_SRBC_LCD_SR(v)      BM_CPM_SRBC_LCD_SR
#define BF_CPM_SRBC_LCD_SR_V(e)     BF_CPM_SRBC_LCD_SR(BV_CPM_SRBC_LCD_SR__##e)
#define BFM_CPM_SRBC_LCD_SR_V(v)    BM_CPM_SRBC_LCD_SR
#define BP_CPM_SRBC_LCD_STOP        24
#define BM_CPM_SRBC_LCD_STOP        0x1000000
#define BF_CPM_SRBC_LCD_STOP(v)     (((v) & 0x1) << 24)
#define BFM_CPM_SRBC_LCD_STOP(v)    BM_CPM_SRBC_LCD_STOP
#define BF_CPM_SRBC_LCD_STOP_V(e)   BF_CPM_SRBC_LCD_STOP(BV_CPM_SRBC_LCD_STOP__##e)
#define BFM_CPM_SRBC_LCD_STOP_V(v)  BM_CPM_SRBC_LCD_STOP
#define BP_CPM_SRBC_LCD_ACK         23
#define BM_CPM_SRBC_LCD_ACK         0x800000
#define BF_CPM_SRBC_LCD_ACK(v)      (((v) & 0x1) << 23)
#define BFM_CPM_SRBC_LCD_ACK(v)     BM_CPM_SRBC_LCD_ACK
#define BF_CPM_SRBC_LCD_ACK_V(e)    BF_CPM_SRBC_LCD_ACK(BV_CPM_SRBC_LCD_ACK__##e)
#define BFM_CPM_SRBC_LCD_ACK_V(v)   BM_CPM_SRBC_LCD_ACK
#define BP_CPM_SRBC_CIM_STOP        21
#define BM_CPM_SRBC_CIM_STOP        0x200000
#define BF_CPM_SRBC_CIM_STOP(v)     (((v) & 0x1) << 21)
#define BFM_CPM_SRBC_CIM_STOP(v)    BM_CPM_SRBC_CIM_STOP
#define BF_CPM_SRBC_CIM_STOP_V(e)   BF_CPM_SRBC_CIM_STOP(BV_CPM_SRBC_CIM_STOP__##e)
#define BFM_CPM_SRBC_CIM_STOP_V(v)  BM_CPM_SRBC_CIM_STOP
#define BP_CPM_SRBC_CIM_ACK         20
#define BM_CPM_SRBC_CIM_ACK         0x100000
#define BF_CPM_SRBC_CIM_ACK(v)      (((v) & 0x1) << 20)
#define BFM_CPM_SRBC_CIM_ACK(v)     BM_CPM_SRBC_CIM_ACK
#define BF_CPM_SRBC_CIM_ACK_V(e)    BF_CPM_SRBC_CIM_ACK(BV_CPM_SRBC_CIM_ACK__##e)
#define BFM_CPM_SRBC_CIM_ACK_V(v)   BM_CPM_SRBC_CIM_ACK
#define BP_CPM_SRBC_CPU_STOP        15
#define BM_CPM_SRBC_CPU_STOP        0x8000
#define BF_CPM_SRBC_CPU_STOP(v)     (((v) & 0x1) << 15)
#define BFM_CPM_SRBC_CPU_STOP(v)    BM_CPM_SRBC_CPU_STOP
#define BF_CPM_SRBC_CPU_STOP_V(e)   BF_CPM_SRBC_CPU_STOP(BV_CPM_SRBC_CPU_STOP__##e)
#define BFM_CPM_SRBC_CPU_STOP_V(v)  BM_CPM_SRBC_CPU_STOP
#define BP_CPM_SRBC_CPU_ACK         14
#define BM_CPM_SRBC_CPU_ACK         0x4000
#define BF_CPM_SRBC_CPU_ACK(v)      (((v) & 0x1) << 14)
#define BFM_CPM_SRBC_CPU_ACK(v)     BM_CPM_SRBC_CPU_ACK
#define BF_CPM_SRBC_CPU_ACK_V(e)    BF_CPM_SRBC_CPU_ACK(BV_CPM_SRBC_CPU_ACK__##e)
#define BFM_CPM_SRBC_CPU_ACK_V(v)   BM_CPM_SRBC_CPU_ACK
#define BP_CPM_SRBC_OTG_SR          12
#define BM_CPM_SRBC_OTG_SR          0x1000
#define BF_CPM_SRBC_OTG_SR(v)       (((v) & 0x1) << 12)
#define BFM_CPM_SRBC_OTG_SR(v)      BM_CPM_SRBC_OTG_SR
#define BF_CPM_SRBC_OTG_SR_V(e)     BF_CPM_SRBC_OTG_SR(BV_CPM_SRBC_OTG_SR__##e)
#define BFM_CPM_SRBC_OTG_SR_V(v)    BM_CPM_SRBC_OTG_SR
#define BP_CPM_SRBC_AHB2_STOP       8
#define BM_CPM_SRBC_AHB2_STOP       0x100
#define BF_CPM_SRBC_AHB2_STOP(v)    (((v) & 0x1) << 8)
#define BFM_CPM_SRBC_AHB2_STOP(v)   BM_CPM_SRBC_AHB2_STOP
#define BF_CPM_SRBC_AHB2_STOP_V(e)  BF_CPM_SRBC_AHB2_STOP(BV_CPM_SRBC_AHB2_STOP__##e)
#define BFM_CPM_SRBC_AHB2_STOP_V(v) BM_CPM_SRBC_AHB2_STOP
#define BP_CPM_SRBC_AHB2_ACK        7
#define BM_CPM_SRBC_AHB2_ACK        0x80
#define BF_CPM_SRBC_AHB2_ACK(v)     (((v) & 0x1) << 7)
#define BFM_CPM_SRBC_AHB2_ACK(v)    BM_CPM_SRBC_AHB2_ACK
#define BF_CPM_SRBC_AHB2_ACK_V(e)   BF_CPM_SRBC_AHB2_ACK(BV_CPM_SRBC_AHB2_ACK__##e)
#define BFM_CPM_SRBC_AHB2_ACK_V(v)  BM_CPM_SRBC_AHB2_ACK
#define BP_CPM_SRBC_DDR_STOP        6
#define BM_CPM_SRBC_DDR_STOP        0x40
#define BF_CPM_SRBC_DDR_STOP(v)     (((v) & 0x1) << 6)
#define BFM_CPM_SRBC_DDR_STOP(v)    BM_CPM_SRBC_DDR_STOP
#define BF_CPM_SRBC_DDR_STOP_V(e)   BF_CPM_SRBC_DDR_STOP(BV_CPM_SRBC_DDR_STOP__##e)
#define BFM_CPM_SRBC_DDR_STOP_V(v)  BM_CPM_SRBC_DDR_STOP
#define BP_CPM_SRBC_DDR_ACK         5
#define BM_CPM_SRBC_DDR_ACK         0x20
#define BF_CPM_SRBC_DDR_ACK(v)      (((v) & 0x1) << 5)
#define BFM_CPM_SRBC_DDR_ACK(v)     BM_CPM_SRBC_DDR_ACK
#define BF_CPM_SRBC_DDR_ACK_V(e)    BF_CPM_SRBC_DDR_ACK(BV_CPM_SRBC_DDR_ACK__##e)
#define BFM_CPM_SRBC_DDR_ACK_V(v)   BM_CPM_SRBC_DDR_ACK

#define REG_CPM_OPCR                        jz_reg(CPM_OPCR)
#define JA_CPM_OPCR                         (0xb0000000 + 0x24)
#define JT_CPM_OPCR                         JIO_32_RW
#define JN_CPM_OPCR                         CPM_OPCR
#define JI_CPM_OPCR                         
#define BP_CPM_OPCR_O1ST                    8
#define BM_CPM_OPCR_O1ST                    0xfff00
#define BF_CPM_OPCR_O1ST(v)                 (((v) & 0xfff) << 8)
#define BFM_CPM_OPCR_O1ST(v)                BM_CPM_OPCR_O1ST
#define BF_CPM_OPCR_O1ST_V(e)               BF_CPM_OPCR_O1ST(BV_CPM_OPCR_O1ST__##e)
#define BFM_CPM_OPCR_O1ST_V(v)              BM_CPM_OPCR_O1ST
#define BP_CPM_OPCR_IDLE_DIS                31
#define BM_CPM_OPCR_IDLE_DIS                0x80000000
#define BF_CPM_OPCR_IDLE_DIS(v)             (((v) & 0x1) << 31)
#define BFM_CPM_OPCR_IDLE_DIS(v)            BM_CPM_OPCR_IDLE_DIS
#define BF_CPM_OPCR_IDLE_DIS_V(e)           BF_CPM_OPCR_IDLE_DIS(BV_CPM_OPCR_IDLE_DIS__##e)
#define BFM_CPM_OPCR_IDLE_DIS_V(v)          BM_CPM_OPCR_IDLE_DIS
#define BP_CPM_OPCR_MASK_INT                30
#define BM_CPM_OPCR_MASK_INT                0x40000000
#define BF_CPM_OPCR_MASK_INT(v)             (((v) & 0x1) << 30)
#define BFM_CPM_OPCR_MASK_INT(v)            BM_CPM_OPCR_MASK_INT
#define BF_CPM_OPCR_MASK_INT_V(e)           BF_CPM_OPCR_MASK_INT(BV_CPM_OPCR_MASK_INT__##e)
#define BFM_CPM_OPCR_MASK_INT_V(v)          BM_CPM_OPCR_MASK_INT
#define BP_CPM_OPCR_MASK_VPU                29
#define BM_CPM_OPCR_MASK_VPU                0x20000000
#define BF_CPM_OPCR_MASK_VPU(v)             (((v) & 0x1) << 29)
#define BFM_CPM_OPCR_MASK_VPU(v)            BM_CPM_OPCR_MASK_VPU
#define BF_CPM_OPCR_MASK_VPU_V(e)           BF_CPM_OPCR_MASK_VPU(BV_CPM_OPCR_MASK_VPU__##e)
#define BFM_CPM_OPCR_MASK_VPU_V(v)          BM_CPM_OPCR_MASK_VPU
#define BP_CPM_OPCR_GATE_SCLK_A_BUS         28
#define BM_CPM_OPCR_GATE_SCLK_A_BUS         0x10000000
#define BF_CPM_OPCR_GATE_SCLK_A_BUS(v)      (((v) & 0x1) << 28)
#define BFM_CPM_OPCR_GATE_SCLK_A_BUS(v)     BM_CPM_OPCR_GATE_SCLK_A_BUS
#define BF_CPM_OPCR_GATE_SCLK_A_BUS_V(e)    BF_CPM_OPCR_GATE_SCLK_A_BUS(BV_CPM_OPCR_GATE_SCLK_A_BUS__##e)
#define BFM_CPM_OPCR_GATE_SCLK_A_BUS_V(v)   BM_CPM_OPCR_GATE_SCLK_A_BUS
#define BP_CPM_OPCR_L2C_PD                  25
#define BM_CPM_OPCR_L2C_PD                  0x2000000
#define BF_CPM_OPCR_L2C_PD(v)               (((v) & 0x1) << 25)
#define BFM_CPM_OPCR_L2C_PD(v)              BM_CPM_OPCR_L2C_PD
#define BF_CPM_OPCR_L2C_PD_V(e)             BF_CPM_OPCR_L2C_PD(BV_CPM_OPCR_L2C_PD__##e)
#define BFM_CPM_OPCR_L2C_PD_V(v)            BM_CPM_OPCR_L2C_PD
#define BP_CPM_OPCR_REQ_MODE                24
#define BM_CPM_OPCR_REQ_MODE                0x1000000
#define BF_CPM_OPCR_REQ_MODE(v)             (((v) & 0x1) << 24)
#define BFM_CPM_OPCR_REQ_MODE(v)            BM_CPM_OPCR_REQ_MODE
#define BF_CPM_OPCR_REQ_MODE_V(e)           BF_CPM_OPCR_REQ_MODE(BV_CPM_OPCR_REQ_MODE__##e)
#define BFM_CPM_OPCR_REQ_MODE_V(v)          BM_CPM_OPCR_REQ_MODE
#define BP_CPM_OPCR_GATE_USBPHY_CLK         23
#define BM_CPM_OPCR_GATE_USBPHY_CLK         0x800000
#define BF_CPM_OPCR_GATE_USBPHY_CLK(v)      (((v) & 0x1) << 23)
#define BFM_CPM_OPCR_GATE_USBPHY_CLK(v)     BM_CPM_OPCR_GATE_USBPHY_CLK
#define BF_CPM_OPCR_GATE_USBPHY_CLK_V(e)    BF_CPM_OPCR_GATE_USBPHY_CLK(BV_CPM_OPCR_GATE_USBPHY_CLK__##e)
#define BFM_CPM_OPCR_GATE_USBPHY_CLK_V(v)   BM_CPM_OPCR_GATE_USBPHY_CLK
#define BP_CPM_OPCR_DIS_STOP_MUX            22
#define BM_CPM_OPCR_DIS_STOP_MUX            0x400000
#define BF_CPM_OPCR_DIS_STOP_MUX(v)         (((v) & 0x1) << 22)
#define BFM_CPM_OPCR_DIS_STOP_MUX(v)        BM_CPM_OPCR_DIS_STOP_MUX
#define BF_CPM_OPCR_DIS_STOP_MUX_V(e)       BF_CPM_OPCR_DIS_STOP_MUX(BV_CPM_OPCR_DIS_STOP_MUX__##e)
#define BFM_CPM_OPCR_DIS_STOP_MUX_V(v)      BM_CPM_OPCR_DIS_STOP_MUX
#define BP_CPM_OPCR_SPENDN0                 7
#define BM_CPM_OPCR_SPENDN0                 0x80
#define BF_CPM_OPCR_SPENDN0(v)              (((v) & 0x1) << 7)
#define BFM_CPM_OPCR_SPENDN0(v)             BM_CPM_OPCR_SPENDN0
#define BF_CPM_OPCR_SPENDN0_V(e)            BF_CPM_OPCR_SPENDN0(BV_CPM_OPCR_SPENDN0__##e)
#define BFM_CPM_OPCR_SPENDN0_V(v)           BM_CPM_OPCR_SPENDN0
#define BP_CPM_OPCR_SPENDN1                 6
#define BM_CPM_OPCR_SPENDN1                 0x40
#define BF_CPM_OPCR_SPENDN1(v)              (((v) & 0x1) << 6)
#define BFM_CPM_OPCR_SPENDN1(v)             BM_CPM_OPCR_SPENDN1
#define BF_CPM_OPCR_SPENDN1_V(e)            BF_CPM_OPCR_SPENDN1(BV_CPM_OPCR_SPENDN1__##e)
#define BFM_CPM_OPCR_SPENDN1_V(v)           BM_CPM_OPCR_SPENDN1
#define BP_CPM_OPCR_CPU_MODE                5
#define BM_CPM_OPCR_CPU_MODE                0x20
#define BF_CPM_OPCR_CPU_MODE(v)             (((v) & 0x1) << 5)
#define BFM_CPM_OPCR_CPU_MODE(v)            BM_CPM_OPCR_CPU_MODE
#define BF_CPM_OPCR_CPU_MODE_V(e)           BF_CPM_OPCR_CPU_MODE(BV_CPM_OPCR_CPU_MODE__##e)
#define BFM_CPM_OPCR_CPU_MODE_V(v)          BM_CPM_OPCR_CPU_MODE
#define BP_CPM_OPCR_O1SE                    4
#define BM_CPM_OPCR_O1SE                    0x10
#define BF_CPM_OPCR_O1SE(v)                 (((v) & 0x1) << 4)
#define BFM_CPM_OPCR_O1SE(v)                BM_CPM_OPCR_O1SE
#define BF_CPM_OPCR_O1SE_V(e)               BF_CPM_OPCR_O1SE(BV_CPM_OPCR_O1SE__##e)
#define BFM_CPM_OPCR_O1SE_V(v)              BM_CPM_OPCR_O1SE
#define BP_CPM_OPCR_PD                      3
#define BM_CPM_OPCR_PD                      0x8
#define BF_CPM_OPCR_PD(v)                   (((v) & 0x1) << 3)
#define BFM_CPM_OPCR_PD(v)                  BM_CPM_OPCR_PD
#define BF_CPM_OPCR_PD_V(e)                 BF_CPM_OPCR_PD(BV_CPM_OPCR_PD__##e)
#define BFM_CPM_OPCR_PD_V(v)                BM_CPM_OPCR_PD
#define BP_CPM_OPCR_ERCS                    2
#define BM_CPM_OPCR_ERCS                    0x4
#define BF_CPM_OPCR_ERCS(v)                 (((v) & 0x1) << 2)
#define BFM_CPM_OPCR_ERCS(v)                BM_CPM_OPCR_ERCS
#define BF_CPM_OPCR_ERCS_V(e)               BF_CPM_OPCR_ERCS(BV_CPM_OPCR_ERCS__##e)
#define BFM_CPM_OPCR_ERCS_V(v)              BM_CPM_OPCR_ERCS
#define BP_CPM_OPCR_BUS_MODE                1
#define BM_CPM_OPCR_BUS_MODE                0x2
#define BF_CPM_OPCR_BUS_MODE(v)             (((v) & 0x1) << 1)
#define BFM_CPM_OPCR_BUS_MODE(v)            BM_CPM_OPCR_BUS_MODE
#define BF_CPM_OPCR_BUS_MODE_V(e)           BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e)
#define BFM_CPM_OPCR_BUS_MODE_V(v)          BM_CPM_OPCR_BUS_MODE

#define REG_CPM_RSR             jz_reg(CPM_RSR)
#define JA_CPM_RSR              (0xb0000000 + 0x8)
#define JT_CPM_RSR              JIO_32_RW
#define JN_CPM_RSR              CPM_RSR
#define JI_CPM_RSR              
#define BP_CPM_RSR_HR           3
#define BM_CPM_RSR_HR           0x8
#define BF_CPM_RSR_HR(v)        (((v) & 0x1) << 3)
#define BFM_CPM_RSR_HR(v)       BM_CPM_RSR_HR
#define BF_CPM_RSR_HR_V(e)      BF_CPM_RSR_HR(BV_CPM_RSR_HR__##e)
#define BFM_CPM_RSR_HR_V(v)     BM_CPM_RSR_HR
#define BP_CPM_RSR_P0R          2
#define BM_CPM_RSR_P0R          0x4
#define BF_CPM_RSR_P0R(v)       (((v) & 0x1) << 2)
#define BFM_CPM_RSR_P0R(v)      BM_CPM_RSR_P0R
#define BF_CPM_RSR_P0R_V(e)     BF_CPM_RSR_P0R(BV_CPM_RSR_P0R__##e)
#define BFM_CPM_RSR_P0R_V(v)    BM_CPM_RSR_P0R
#define BP_CPM_RSR_WR           1
#define BM_CPM_RSR_WR           0x2
#define BF_CPM_RSR_WR(v)        (((v) & 0x1) << 1)
#define BFM_CPM_RSR_WR(v)       BM_CPM_RSR_WR
#define BF_CPM_RSR_WR_V(e)      BF_CPM_RSR_WR(BV_CPM_RSR_WR__##e)
#define BFM_CPM_RSR_WR_V(v)     BM_CPM_RSR_WR
#define BP_CPM_RSR_PR           0
#define BM_CPM_RSR_PR           0x1
#define BF_CPM_RSR_PR(v)        (((v) & 0x1) << 0)
#define BFM_CPM_RSR_PR(v)       BM_CPM_RSR_PR
#define BF_CPM_RSR_PR_V(e)      BF_CPM_RSR_PR(BV_CPM_RSR_PR__##e)
#define BFM_CPM_RSR_PR_V(v)     BM_CPM_RSR_PR

#endif /* __HEADERGEN_CPM_H__*/
