/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * imx233 version: 2.4.0
 * imx233 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_IMX233_POWER_H__
#define __HEADERGEN_IMX233_POWER_H__

#define HW_POWER_CTRL                               HW(POWER_CTRL)
#define HWA_POWER_CTRL                              (0x80044000 + 0x0)
#define HWT_POWER_CTRL                              HWIO_32_RW
#define HWN_POWER_CTRL                              POWER_CTRL
#define HWI_POWER_CTRL                              
#define HW_POWER_CTRL_SET                           HW(POWER_CTRL_SET)
#define HWA_POWER_CTRL_SET                          (HWA_POWER_CTRL + 0x4)
#define HWT_POWER_CTRL_SET                          HWIO_32_WO
#define HWN_POWER_CTRL_SET                          POWER_CTRL
#define HWI_POWER_CTRL_SET                          
#define HW_POWER_CTRL_CLR                           HW(POWER_CTRL_CLR)
#define HWA_POWER_CTRL_CLR                          (HWA_POWER_CTRL + 0x8)
#define HWT_POWER_CTRL_CLR                          HWIO_32_WO
#define HWN_POWER_CTRL_CLR                          POWER_CTRL
#define HWI_POWER_CTRL_CLR                          
#define HW_POWER_CTRL_TOG                           HW(POWER_CTRL_TOG)
#define HWA_POWER_CTRL_TOG                          (HWA_POWER_CTRL + 0xc)
#define HWT_POWER_CTRL_TOG                          HWIO_32_WO
#define HWN_POWER_CTRL_TOG                          POWER_CTRL
#define HWI_POWER_CTRL_TOG                          
#define BP_POWER_CTRL_RSRVD3                        31
#define BM_POWER_CTRL_RSRVD3                        0x80000000
#define BF_POWER_CTRL_RSRVD3(v)                     (((v) & 0x1) << 31)
#define BFM_POWER_CTRL_RSRVD3(v)                    BM_POWER_CTRL_RSRVD3
#define BF_POWER_CTRL_RSRVD3_V(e)                   BF_POWER_CTRL_RSRVD3(BV_POWER_CTRL_RSRVD3__##e)
#define BFM_POWER_CTRL_RSRVD3_V(v)                  BM_POWER_CTRL_RSRVD3
#define BP_POWER_CTRL_CLKGATE                       30
#define BM_POWER_CTRL_CLKGATE                       0x40000000
#define BF_POWER_CTRL_CLKGATE(v)                    (((v) & 0x1) << 30)
#define BFM_POWER_CTRL_CLKGATE(v)                   BM_POWER_CTRL_CLKGATE
#define BF_POWER_CTRL_CLKGATE_V(e)                  BF_POWER_CTRL_CLKGATE(BV_POWER_CTRL_CLKGATE__##e)
#define BFM_POWER_CTRL_CLKGATE_V(v)                 BM_POWER_CTRL_CLKGATE
#define BP_POWER_CTRL_RSRVD2                        28
#define BM_POWER_CTRL_RSRVD2                        0x30000000
#define BF_POWER_CTRL_RSRVD2(v)                     (((v) & 0x3) << 28)
#define BFM_POWER_CTRL_RSRVD2(v)                    BM_POWER_CTRL_RSRVD2
#define BF_POWER_CTRL_RSRVD2_V(e)                   BF_POWER_CTRL_RSRVD2(BV_POWER_CTRL_RSRVD2__##e)
#define BFM_POWER_CTRL_RSRVD2_V(v)                  BM_POWER_CTRL_RSRVD2
#define BP_POWER_CTRL_PSWITCH_MID_TRAN              27
#define BM_POWER_CTRL_PSWITCH_MID_TRAN              0x8000000
#define BF_POWER_CTRL_PSWITCH_MID_TRAN(v)           (((v) & 0x1) << 27)
#define BFM_POWER_CTRL_PSWITCH_MID_TRAN(v)          BM_POWER_CTRL_PSWITCH_MID_TRAN
#define BF_POWER_CTRL_PSWITCH_MID_TRAN_V(e)         BF_POWER_CTRL_PSWITCH_MID_TRAN(BV_POWER_CTRL_PSWITCH_MID_TRAN__##e)
#define BFM_POWER_CTRL_PSWITCH_MID_TRAN_V(v)        BM_POWER_CTRL_PSWITCH_MID_TRAN
#define BP_POWER_CTRL_RSRVD1                        25
#define BM_POWER_CTRL_RSRVD1                        0x6000000
#define BF_POWER_CTRL_RSRVD1(v)                     (((v) & 0x3) << 25)
#define BFM_POWER_CTRL_RSRVD1(v)                    BM_POWER_CTRL_RSRVD1
#define BF_POWER_CTRL_RSRVD1_V(e)                   BF_POWER_CTRL_RSRVD1(BV_POWER_CTRL_RSRVD1__##e)
#define BFM_POWER_CTRL_RSRVD1_V(v)                  BM_POWER_CTRL_RSRVD1
#define BP_POWER_CTRL_DCDC4P2_BO_IRQ                24
#define BM_POWER_CTRL_DCDC4P2_BO_IRQ                0x1000000
#define BF_POWER_CTRL_DCDC4P2_BO_IRQ(v)             (((v) & 0x1) << 24)
#define BFM_POWER_CTRL_DCDC4P2_BO_IRQ(v)            BM_POWER_CTRL_DCDC4P2_BO_IRQ
#define BF_POWER_CTRL_DCDC4P2_BO_IRQ_V(e)           BF_POWER_CTRL_DCDC4P2_BO_IRQ(BV_POWER_CTRL_DCDC4P2_BO_IRQ__##e)
#define BFM_POWER_CTRL_DCDC4P2_BO_IRQ_V(v)          BM_POWER_CTRL_DCDC4P2_BO_IRQ
#define BP_POWER_CTRL_ENIRQ_DCDC4P2_BO              23
#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO              0x800000
#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)           (((v) & 0x1) << 23)
#define BFM_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)          BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO_V(e)         BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(BV_POWER_CTRL_ENIRQ_DCDC4P2_BO__##e)
#define BFM_POWER_CTRL_ENIRQ_DCDC4P2_BO_V(v)        BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
#define BP_POWER_CTRL_VDD5V_DROOP_IRQ               22
#define BM_POWER_CTRL_VDD5V_DROOP_IRQ               0x400000
#define BF_POWER_CTRL_VDD5V_DROOP_IRQ(v)            (((v) & 0x1) << 22)
#define BFM_POWER_CTRL_VDD5V_DROOP_IRQ(v)           BM_POWER_CTRL_VDD5V_DROOP_IRQ
#define BF_POWER_CTRL_VDD5V_DROOP_IRQ_V(e)          BF_POWER_CTRL_VDD5V_DROOP_IRQ(BV_POWER_CTRL_VDD5V_DROOP_IRQ__##e)
#define BFM_POWER_CTRL_VDD5V_DROOP_IRQ_V(v)         BM_POWER_CTRL_VDD5V_DROOP_IRQ
#define BP_POWER_CTRL_ENIRQ_VDD5V_DROOP             21
#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP             0x200000
#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)          (((v) & 0x1) << 21)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)         BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP_V(e)        BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(BV_POWER_CTRL_ENIRQ_VDD5V_DROOP__##e)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_DROOP_V(v)       BM_POWER_CTRL_ENIRQ_VDD5V_DROOP
#define BP_POWER_CTRL_PSWITCH_IRQ                   20
#define BM_POWER_CTRL_PSWITCH_IRQ                   0x100000
#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) & 0x1) << 20)
#define BFM_POWER_CTRL_PSWITCH_IRQ(v)               BM_POWER_CTRL_PSWITCH_IRQ
#define BF_POWER_CTRL_PSWITCH_IRQ_V(e)              BF_POWER_CTRL_PSWITCH_IRQ(BV_POWER_CTRL_PSWITCH_IRQ__##e)
#define BFM_POWER_CTRL_PSWITCH_IRQ_V(v)             BM_POWER_CTRL_PSWITCH_IRQ
#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               19
#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x80000
#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) & 0x1) << 19)
#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC(v)           BM_POWER_CTRL_PSWITCH_IRQ_SRC
#define BF_POWER_CTRL_PSWITCH_IRQ_SRC_V(e)          BF_POWER_CTRL_PSWITCH_IRQ_SRC(BV_POWER_CTRL_PSWITCH_IRQ_SRC__##e)
#define BFM_POWER_CTRL_PSWITCH_IRQ_SRC_V(v)         BM_POWER_CTRL_PSWITCH_IRQ_SRC
#define BP_POWER_CTRL_POLARITY_PSWITCH              18
#define BM_POWER_CTRL_POLARITY_PSWITCH              0x40000
#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) & 0x1) << 18)
#define BFM_POWER_CTRL_POLARITY_PSWITCH(v)          BM_POWER_CTRL_POLARITY_PSWITCH
#define BF_POWER_CTRL_POLARITY_PSWITCH_V(e)         BF_POWER_CTRL_POLARITY_PSWITCH(BV_POWER_CTRL_POLARITY_PSWITCH__##e)
#define BFM_POWER_CTRL_POLARITY_PSWITCH_V(v)        BM_POWER_CTRL_POLARITY_PSWITCH
#define BP_POWER_CTRL_ENIRQ_PSWITCH                 17
#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x20000
#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) & 0x1) << 17)
#define BFM_POWER_CTRL_ENIRQ_PSWITCH(v)             BM_POWER_CTRL_ENIRQ_PSWITCH
#define BF_POWER_CTRL_ENIRQ_PSWITCH_V(e)            BF_POWER_CTRL_ENIRQ_PSWITCH(BV_POWER_CTRL_ENIRQ_PSWITCH__##e)
#define BFM_POWER_CTRL_ENIRQ_PSWITCH_V(v)           BM_POWER_CTRL_ENIRQ_PSWITCH
#define BP_POWER_CTRL_POLARITY_DC_OK                16
#define BM_POWER_CTRL_POLARITY_DC_OK                0x10000
#define BF_POWER_CTRL_POLARITY_DC_OK(v)             (((v) & 0x1) << 16)
#define BFM_POWER_CTRL_POLARITY_DC_OK(v)            BM_POWER_CTRL_POLARITY_DC_OK
#define BF_POWER_CTRL_POLARITY_DC_OK_V(e)           BF_POWER_CTRL_POLARITY_DC_OK(BV_POWER_CTRL_POLARITY_DC_OK__##e)
#define BFM_POWER_CTRL_POLARITY_DC_OK_V(v)          BM_POWER_CTRL_POLARITY_DC_OK
#define BP_POWER_CTRL_DC_OK_IRQ                     15
#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) & 0x1) << 15)
#define BFM_POWER_CTRL_DC_OK_IRQ(v)                 BM_POWER_CTRL_DC_OK_IRQ
#define BF_POWER_CTRL_DC_OK_IRQ_V(e)                BF_POWER_CTRL_DC_OK_IRQ(BV_POWER_CTRL_DC_OK_IRQ__##e)
#define BFM_POWER_CTRL_DC_OK_IRQ_V(v)               BM_POWER_CTRL_DC_OK_IRQ
#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) & 0x1) << 14)
#define BFM_POWER_CTRL_ENIRQ_DC_OK(v)               BM_POWER_CTRL_ENIRQ_DC_OK
#define BF_POWER_CTRL_ENIRQ_DC_OK_V(e)              BF_POWER_CTRL_ENIRQ_DC_OK(BV_POWER_CTRL_ENIRQ_DC_OK__##e)
#define BFM_POWER_CTRL_ENIRQ_DC_OK_V(v)             BM_POWER_CTRL_ENIRQ_DC_OK
#define BP_POWER_CTRL_BATT_BO_IRQ                   13
#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) & 0x1) << 13)
#define BFM_POWER_CTRL_BATT_BO_IRQ(v)               BM_POWER_CTRL_BATT_BO_IRQ
#define BF_POWER_CTRL_BATT_BO_IRQ_V(e)              BF_POWER_CTRL_BATT_BO_IRQ(BV_POWER_CTRL_BATT_BO_IRQ__##e)
#define BFM_POWER_CTRL_BATT_BO_IRQ_V(v)             BM_POWER_CTRL_BATT_BO_IRQ
#define BP_POWER_CTRL_ENIRQBATT_BO                  12
#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) & 0x1) << 12)
#define BFM_POWER_CTRL_ENIRQBATT_BO(v)              BM_POWER_CTRL_ENIRQBATT_BO
#define BF_POWER_CTRL_ENIRQBATT_BO_V(e)             BF_POWER_CTRL_ENIRQBATT_BO(BV_POWER_CTRL_ENIRQBATT_BO__##e)
#define BFM_POWER_CTRL_ENIRQBATT_BO_V(v)            BM_POWER_CTRL_ENIRQBATT_BO
#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) & 0x1) << 11)
#define BFM_POWER_CTRL_VDDIO_BO_IRQ(v)              BM_POWER_CTRL_VDDIO_BO_IRQ
#define BF_POWER_CTRL_VDDIO_BO_IRQ_V(e)             BF_POWER_CTRL_VDDIO_BO_IRQ(BV_POWER_CTRL_VDDIO_BO_IRQ__##e)
#define BFM_POWER_CTRL_VDDIO_BO_IRQ_V(v)            BM_POWER_CTRL_VDDIO_BO_IRQ
#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) & 0x1) << 10)
#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO(v)            BM_POWER_CTRL_ENIRQ_VDDIO_BO
#define BF_POWER_CTRL_ENIRQ_VDDIO_BO_V(e)           BF_POWER_CTRL_ENIRQ_VDDIO_BO(BV_POWER_CTRL_ENIRQ_VDDIO_BO__##e)
#define BFM_POWER_CTRL_ENIRQ_VDDIO_BO_V(v)          BM_POWER_CTRL_ENIRQ_VDDIO_BO
#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) & 0x1) << 9)
#define BFM_POWER_CTRL_VDDA_BO_IRQ(v)               BM_POWER_CTRL_VDDA_BO_IRQ
#define BF_POWER_CTRL_VDDA_BO_IRQ_V(e)              BF_POWER_CTRL_VDDA_BO_IRQ(BV_POWER_CTRL_VDDA_BO_IRQ__##e)
#define BFM_POWER_CTRL_VDDA_BO_IRQ_V(v)             BM_POWER_CTRL_VDDA_BO_IRQ
#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) & 0x1) << 8)
#define BFM_POWER_CTRL_ENIRQ_VDDA_BO(v)             BM_POWER_CTRL_ENIRQ_VDDA_BO
#define BF_POWER_CTRL_ENIRQ_VDDA_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDA_BO(BV_POWER_CTRL_ENIRQ_VDDA_BO__##e)
#define BFM_POWER_CTRL_ENIRQ_VDDA_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDA_BO
#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) & 0x1) << 7)
#define BFM_POWER_CTRL_VDDD_BO_IRQ(v)               BM_POWER_CTRL_VDDD_BO_IRQ
#define BF_POWER_CTRL_VDDD_BO_IRQ_V(e)              BF_POWER_CTRL_VDDD_BO_IRQ(BV_POWER_CTRL_VDDD_BO_IRQ__##e)
#define BFM_POWER_CTRL_VDDD_BO_IRQ_V(v)             BM_POWER_CTRL_VDDD_BO_IRQ
#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) & 0x1) << 6)
#define BFM_POWER_CTRL_ENIRQ_VDDD_BO(v)             BM_POWER_CTRL_ENIRQ_VDDD_BO
#define BF_POWER_CTRL_ENIRQ_VDDD_BO_V(e)            BF_POWER_CTRL_ENIRQ_VDDD_BO(BV_POWER_CTRL_ENIRQ_VDDD_BO__##e)
#define BFM_POWER_CTRL_ENIRQ_VDDD_BO_V(v)           BM_POWER_CTRL_ENIRQ_VDDD_BO
#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) & 0x1) << 5)
#define BFM_POWER_CTRL_POLARITY_VBUSVALID(v)        BM_POWER_CTRL_POLARITY_VBUSVALID
#define BF_POWER_CTRL_POLARITY_VBUSVALID_V(e)       BF_POWER_CTRL_POLARITY_VBUSVALID(BV_POWER_CTRL_POLARITY_VBUSVALID__##e)
#define BFM_POWER_CTRL_POLARITY_VBUSVALID_V(v)      BM_POWER_CTRL_POLARITY_VBUSVALID
#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) & 0x1) << 4)
#define BFM_POWER_CTRL_VBUSVALID_IRQ(v)             BM_POWER_CTRL_VBUSVALID_IRQ
#define BF_POWER_CTRL_VBUSVALID_IRQ_V(e)            BF_POWER_CTRL_VBUSVALID_IRQ(BV_POWER_CTRL_VBUSVALID_IRQ__##e)
#define BFM_POWER_CTRL_VBUSVALID_IRQ_V(v)           BM_POWER_CTRL_VBUSVALID_IRQ
#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) & 0x1) << 3)
#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID(v)          BM_POWER_CTRL_ENIRQ_VBUS_VALID
#define BF_POWER_CTRL_ENIRQ_VBUS_VALID_V(e)         BF_POWER_CTRL_ENIRQ_VBUS_VALID(BV_POWER_CTRL_ENIRQ_VBUS_VALID__##e)
#define BFM_POWER_CTRL_ENIRQ_VBUS_VALID_V(v)        BM_POWER_CTRL_ENIRQ_VBUS_VALID
#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) & 0x1) << 2)
#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)   BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(e)  BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(BV_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO_V(v) BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO
#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) & 0x1) << 1)
#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)        BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(e)       BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(BV_POWER_CTRL_VDD5V_GT_VDDIO_IRQ__##e)
#define BFM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ_V(v)      BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ
#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) & 0x1) << 0)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)      BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO
#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(e)     BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(BV_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO_V(v)    BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO

#define HW_POWER_5VCTRL                             HW(POWER_5VCTRL)
#define HWA_POWER_5VCTRL                            (0x80044000 + 0x10)
#define HWT_POWER_5VCTRL                            HWIO_32_RW
#define HWN_POWER_5VCTRL                            POWER_5VCTRL
#define HWI_POWER_5VCTRL                            
#define HW_POWER_5VCTRL_SET                         HW(POWER_5VCTRL_SET)
#define HWA_POWER_5VCTRL_SET                        (HWA_POWER_5VCTRL + 0x4)
#define HWT_POWER_5VCTRL_SET                        HWIO_32_WO
#define HWN_POWER_5VCTRL_SET                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_SET                        
#define HW_POWER_5VCTRL_CLR                         HW(POWER_5VCTRL_CLR)
#define HWA_POWER_5VCTRL_CLR                        (HWA_POWER_5VCTRL + 0x8)
#define HWT_POWER_5VCTRL_CLR                        HWIO_32_WO
#define HWN_POWER_5VCTRL_CLR                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_CLR                        
#define HW_POWER_5VCTRL_TOG                         HW(POWER_5VCTRL_TOG)
#define HWA_POWER_5VCTRL_TOG                        (HWA_POWER_5VCTRL + 0xc)
#define HWT_POWER_5VCTRL_TOG                        HWIO_32_WO
#define HWN_POWER_5VCTRL_TOG                        POWER_5VCTRL
#define HWI_POWER_5VCTRL_TOG                        
#define BP_POWER_5VCTRL_RSRVD6                      30
#define BM_POWER_5VCTRL_RSRVD6                      0xc0000000
#define BF_POWER_5VCTRL_RSRVD6(v)                   (((v) & 0x3) << 30)
#define BFM_POWER_5VCTRL_RSRVD6(v)                  BM_POWER_5VCTRL_RSRVD6
#define BF_POWER_5VCTRL_RSRVD6_V(e)                 BF_POWER_5VCTRL_RSRVD6(BV_POWER_5VCTRL_RSRVD6__##e)
#define BFM_POWER_5VCTRL_RSRVD6_V(v)                BM_POWER_5VCTRL_RSRVD6
#define BP_POWER_5VCTRL_VBUSDROOP_TRSH              28
#define BM_POWER_5VCTRL_VBUSDROOP_TRSH              0x30000000
#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v)           (((v) & 0x3) << 28)
#define BFM_POWER_5VCTRL_VBUSDROOP_TRSH(v)          BM_POWER_5VCTRL_VBUSDROOP_TRSH
#define BF_POWER_5VCTRL_VBUSDROOP_TRSH_V(e)         BF_POWER_5VCTRL_VBUSDROOP_TRSH(BV_POWER_5VCTRL_VBUSDROOP_TRSH__##e)
#define BFM_POWER_5VCTRL_VBUSDROOP_TRSH_V(v)        BM_POWER_5VCTRL_VBUSDROOP_TRSH
#define BP_POWER_5VCTRL_RSRVD5                      27
#define BM_POWER_5VCTRL_RSRVD5                      0x8000000
#define BF_POWER_5VCTRL_RSRVD5(v)                   (((v) & 0x1) << 27)
#define BFM_POWER_5VCTRL_RSRVD5(v)                  BM_POWER_5VCTRL_RSRVD5
#define BF_POWER_5VCTRL_RSRVD5_V(e)                 BF_POWER_5VCTRL_RSRVD5(BV_POWER_5VCTRL_RSRVD5__##e)
#define BFM_POWER_5VCTRL_RSRVD5_V(v)                BM_POWER_5VCTRL_RSRVD5
#define BP_POWER_5VCTRL_HEADROOM_ADJ                24
#define BM_POWER_5VCTRL_HEADROOM_ADJ                0x7000000
#define BF_POWER_5VCTRL_HEADROOM_ADJ(v)             (((v) & 0x7) << 24)
#define BFM_POWER_5VCTRL_HEADROOM_ADJ(v)            BM_POWER_5VCTRL_HEADROOM_ADJ
#define BF_POWER_5VCTRL_HEADROOM_ADJ_V(e)           BF_POWER_5VCTRL_HEADROOM_ADJ(BV_POWER_5VCTRL_HEADROOM_ADJ__##e)
#define BFM_POWER_5VCTRL_HEADROOM_ADJ_V(v)          BM_POWER_5VCTRL_HEADROOM_ADJ
#define BP_POWER_5VCTRL_RSRVD4                      21
#define BM_POWER_5VCTRL_RSRVD4                      0xe00000
#define BF_POWER_5VCTRL_RSRVD4(v)                   (((v) & 0x7) << 21)
#define BFM_POWER_5VCTRL_RSRVD4(v)                  BM_POWER_5VCTRL_RSRVD4
#define BF_POWER_5VCTRL_RSRVD4_V(e)                 BF_POWER_5VCTRL_RSRVD4(BV_POWER_5VCTRL_RSRVD4__##e)
#define BFM_POWER_5VCTRL_RSRVD4_V(v)                BM_POWER_5VCTRL_RSRVD4
#define BP_POWER_5VCTRL_PWD_CHARGE_4P2              20
#define BM_POWER_5VCTRL_PWD_CHARGE_4P2              0x100000
#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v)           (((v) & 0x1) << 20)
#define BFM_POWER_5VCTRL_PWD_CHARGE_4P2(v)          BM_POWER_5VCTRL_PWD_CHARGE_4P2
#define BF_POWER_5VCTRL_PWD_CHARGE_4P2_V(e)         BF_POWER_5VCTRL_PWD_CHARGE_4P2(BV_POWER_5VCTRL_PWD_CHARGE_4P2__##e)
#define BFM_POWER_5VCTRL_PWD_CHARGE_4P2_V(v)        BM_POWER_5VCTRL_PWD_CHARGE_4P2
#define BP_POWER_5VCTRL_RSRVD3                      18
#define BM_POWER_5VCTRL_RSRVD3                      0xc0000
#define BF_POWER_5VCTRL_RSRVD3(v)                   (((v) & 0x3) << 18)
#define BFM_POWER_5VCTRL_RSRVD3(v)                  BM_POWER_5VCTRL_RSRVD3
#define BF_POWER_5VCTRL_RSRVD3_V(e)                 BF_POWER_5VCTRL_RSRVD3(BV_POWER_5VCTRL_RSRVD3__##e)
#define BFM_POWER_5VCTRL_RSRVD3_V(v)                BM_POWER_5VCTRL_RSRVD3
#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT           12
#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT           0x3f000
#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)        (((v) & 0x3f) << 12)
#define BFM_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)       BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT
#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT_V(e)      BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__##e)
#define BFM_POWER_5VCTRL_CHARGE_4P2_ILIMIT_V(v)     BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT
#define BP_POWER_5VCTRL_RSRVD2                      11
#define BM_POWER_5VCTRL_RSRVD2                      0x800
#define BF_POWER_5VCTRL_RSRVD2(v)                   (((v) & 0x1) << 11)
#define BFM_POWER_5VCTRL_RSRVD2(v)                  BM_POWER_5VCTRL_RSRVD2
#define BF_POWER_5VCTRL_RSRVD2_V(e)                 BF_POWER_5VCTRL_RSRVD2(BV_POWER_5VCTRL_RSRVD2__##e)
#define BFM_POWER_5VCTRL_RSRVD2_V(v)                BM_POWER_5VCTRL_RSRVD2
#define BP_POWER_5VCTRL_VBUSVALID_TRSH              8
#define BM_POWER_5VCTRL_VBUSVALID_TRSH              0x700
#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)           (((v) & 0x7) << 8)
#define BFM_POWER_5VCTRL_VBUSVALID_TRSH(v)          BM_POWER_5VCTRL_VBUSVALID_TRSH
#define BF_POWER_5VCTRL_VBUSVALID_TRSH_V(e)         BF_POWER_5VCTRL_VBUSVALID_TRSH(BV_POWER_5VCTRL_VBUSVALID_TRSH__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_TRSH_V(v)        BM_POWER_5VCTRL_VBUSVALID_TRSH
#define BP_POWER_5VCTRL_PWDN_5VBRNOUT               7
#define BM_POWER_5VCTRL_PWDN_5VBRNOUT               0x80
#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)            (((v) & 0x1) << 7)
#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT(v)           BM_POWER_5VCTRL_PWDN_5VBRNOUT
#define BF_POWER_5VCTRL_PWDN_5VBRNOUT_V(e)          BF_POWER_5VCTRL_PWDN_5VBRNOUT(BV_POWER_5VCTRL_PWDN_5VBRNOUT__##e)
#define BFM_POWER_5VCTRL_PWDN_5VBRNOUT_V(v)         BM_POWER_5VCTRL_PWDN_5VBRNOUT
#define BP_POWER_5VCTRL_ENABLE_LINREG_ILIMIT        6
#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT        0x40
#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v)     (((v) & 0x1) << 6)
#define BFM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v)    BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT
#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT_V(e)   BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(BV_POWER_5VCTRL_ENABLE_LINREG_ILIMIT__##e)
#define BFM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT_V(v)  BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT
#define BP_POWER_5VCTRL_DCDC_XFER                   5
#define BM_POWER_5VCTRL_DCDC_XFER                   0x20
#define BF_POWER_5VCTRL_DCDC_XFER(v)                (((v) & 0x1) << 5)
#define BFM_POWER_5VCTRL_DCDC_XFER(v)               BM_POWER_5VCTRL_DCDC_XFER
#define BF_POWER_5VCTRL_DCDC_XFER_V(e)              BF_POWER_5VCTRL_DCDC_XFER(BV_POWER_5VCTRL_DCDC_XFER__##e)
#define BFM_POWER_5VCTRL_DCDC_XFER_V(v)             BM_POWER_5VCTRL_DCDC_XFER
#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT          4
#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT          0x10
#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)       (((v) & 0x1) << 4)
#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT(v)      BM_POWER_5VCTRL_VBUSVALID_5VDETECT
#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT_V(e)     BF_POWER_5VCTRL_VBUSVALID_5VDETECT(BV_POWER_5VCTRL_VBUSVALID_5VDETECT__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_5VDETECT_V(v)    BM_POWER_5VCTRL_VBUSVALID_5VDETECT
#define BP_POWER_5VCTRL_VBUSVALID_TO_B              3
#define BM_POWER_5VCTRL_VBUSVALID_TO_B              0x8
#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)           (((v) & 0x1) << 3)
#define BFM_POWER_5VCTRL_VBUSVALID_TO_B(v)          BM_POWER_5VCTRL_VBUSVALID_TO_B
#define BF_POWER_5VCTRL_VBUSVALID_TO_B_V(e)         BF_POWER_5VCTRL_VBUSVALID_TO_B(BV_POWER_5VCTRL_VBUSVALID_TO_B__##e)
#define BFM_POWER_5VCTRL_VBUSVALID_TO_B_V(v)        BM_POWER_5VCTRL_VBUSVALID_TO_B
#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO              2
#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO              0x4
#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)           (((v) & 0x1) << 2)
#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)          BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(e)         BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(BV_POWER_5VCTRL_ILIMIT_EQ_ZERO__##e)
#define BFM_POWER_5VCTRL_ILIMIT_EQ_ZERO_V(v)        BM_POWER_5VCTRL_ILIMIT_EQ_ZERO
#define BP_POWER_5VCTRL_PWRUP_VBUS_CMPS             1
#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS             0x2
#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)          (((v) & 0x1) << 1)
#define BFM_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)         BM_POWER_5VCTRL_PWRUP_VBUS_CMPS
#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS_V(e)        BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(BV_POWER_5VCTRL_PWRUP_VBUS_CMPS__##e)
#define BFM_POWER_5VCTRL_PWRUP_VBUS_CMPS_V(v)       BM_POWER_5VCTRL_PWRUP_VBUS_CMPS
#define BP_POWER_5VCTRL_ENABLE_DCDC                 0
#define BM_POWER_5VCTRL_ENABLE_DCDC                 0x1
#define BF_POWER_5VCTRL_ENABLE_DCDC(v)              (((v) & 0x1) << 0)
#define BFM_POWER_5VCTRL_ENABLE_DCDC(v)             BM_POWER_5VCTRL_ENABLE_DCDC
#define BF_POWER_5VCTRL_ENABLE_DCDC_V(e)            BF_POWER_5VCTRL_ENABLE_DCDC(BV_POWER_5VCTRL_ENABLE_DCDC__##e)
#define BFM_POWER_5VCTRL_ENABLE_DCDC_V(v)           BM_POWER_5VCTRL_ENABLE_DCDC

#define HW_POWER_MINPWR                         HW(POWER_MINPWR)
#define HWA_POWER_MINPWR                        (0x80044000 + 0x20)
#define HWT_POWER_MINPWR                        HWIO_32_RW
#define HWN_POWER_MINPWR                        POWER_MINPWR
#define HWI_POWER_MINPWR                        
#define HW_POWER_MINPWR_SET                     HW(POWER_MINPWR_SET)
#define HWA_POWER_MINPWR_SET                    (HWA_POWER_MINPWR + 0x4)
#define HWT_POWER_MINPWR_SET                    HWIO_32_WO
#define HWN_POWER_MINPWR_SET                    POWER_MINPWR
#define HWI_POWER_MINPWR_SET                    
#define HW_POWER_MINPWR_CLR                     HW(POWER_MINPWR_CLR)
#define HWA_POWER_MINPWR_CLR                    (HWA_POWER_MINPWR + 0x8)
#define HWT_POWER_MINPWR_CLR                    HWIO_32_WO
#define HWN_POWER_MINPWR_CLR                    POWER_MINPWR
#define HWI_POWER_MINPWR_CLR                    
#define HW_POWER_MINPWR_TOG                     HW(POWER_MINPWR_TOG)
#define HWA_POWER_MINPWR_TOG                    (HWA_POWER_MINPWR + 0xc)
#define HWT_POWER_MINPWR_TOG                    HWIO_32_WO
#define HWN_POWER_MINPWR_TOG                    POWER_MINPWR
#define HWI_POWER_MINPWR_TOG                    
#define BP_POWER_MINPWR_RSRVD1                  15
#define BM_POWER_MINPWR_RSRVD1                  0xffff8000
#define BF_POWER_MINPWR_RSRVD1(v)               (((v) & 0x1ffff) << 15)
#define BFM_POWER_MINPWR_RSRVD1(v)              BM_POWER_MINPWR_RSRVD1
#define BF_POWER_MINPWR_RSRVD1_V(e)             BF_POWER_MINPWR_RSRVD1(BV_POWER_MINPWR_RSRVD1__##e)
#define BFM_POWER_MINPWR_RSRVD1_V(v)            BM_POWER_MINPWR_RSRVD1
#define BP_POWER_MINPWR_LOWPWR_4P2              14
#define BM_POWER_MINPWR_LOWPWR_4P2              0x4000
#define BF_POWER_MINPWR_LOWPWR_4P2(v)           (((v) & 0x1) << 14)
#define BFM_POWER_MINPWR_LOWPWR_4P2(v)          BM_POWER_MINPWR_LOWPWR_4P2
#define BF_POWER_MINPWR_LOWPWR_4P2_V(e)         BF_POWER_MINPWR_LOWPWR_4P2(BV_POWER_MINPWR_LOWPWR_4P2__##e)
#define BFM_POWER_MINPWR_LOWPWR_4P2_V(v)        BM_POWER_MINPWR_LOWPWR_4P2
#define BP_POWER_MINPWR_VDAC_DUMP_CTRL          13
#define BM_POWER_MINPWR_VDAC_DUMP_CTRL          0x2000
#define BF_POWER_MINPWR_VDAC_DUMP_CTRL(v)       (((v) & 0x1) << 13)
#define BFM_POWER_MINPWR_VDAC_DUMP_CTRL(v)      BM_POWER_MINPWR_VDAC_DUMP_CTRL
#define BF_POWER_MINPWR_VDAC_DUMP_CTRL_V(e)     BF_POWER_MINPWR_VDAC_DUMP_CTRL(BV_POWER_MINPWR_VDAC_DUMP_CTRL__##e)
#define BFM_POWER_MINPWR_VDAC_DUMP_CTRL_V(v)    BM_POWER_MINPWR_VDAC_DUMP_CTRL
#define BP_POWER_MINPWR_PWD_BO                  12
#define BM_POWER_MINPWR_PWD_BO                  0x1000
#define BF_POWER_MINPWR_PWD_BO(v)               (((v) & 0x1) << 12)
#define BFM_POWER_MINPWR_PWD_BO(v)              BM_POWER_MINPWR_PWD_BO
#define BF_POWER_MINPWR_PWD_BO_V(e)             BF_POWER_MINPWR_PWD_BO(BV_POWER_MINPWR_PWD_BO__##e)
#define BFM_POWER_MINPWR_PWD_BO_V(v)            BM_POWER_MINPWR_PWD_BO
#define BP_POWER_MINPWR_USE_VDDXTAL_VBG         11
#define BM_POWER_MINPWR_USE_VDDXTAL_VBG         0x800
#define BF_POWER_MINPWR_USE_VDDXTAL_VBG(v)      (((v) & 0x1) << 11)
#define BFM_POWER_MINPWR_USE_VDDXTAL_VBG(v)     BM_POWER_MINPWR_USE_VDDXTAL_VBG
#define BF_POWER_MINPWR_USE_VDDXTAL_VBG_V(e)    BF_POWER_MINPWR_USE_VDDXTAL_VBG(BV_POWER_MINPWR_USE_VDDXTAL_VBG__##e)
#define BFM_POWER_MINPWR_USE_VDDXTAL_VBG_V(v)   BM_POWER_MINPWR_USE_VDDXTAL_VBG
#define BP_POWER_MINPWR_PWD_ANA_CMPS            10
#define BM_POWER_MINPWR_PWD_ANA_CMPS            0x400
#define BF_POWER_MINPWR_PWD_ANA_CMPS(v)         (((v) & 0x1) << 10)
#define BFM_POWER_MINPWR_PWD_ANA_CMPS(v)        BM_POWER_MINPWR_PWD_ANA_CMPS
#define BF_POWER_MINPWR_PWD_ANA_CMPS_V(e)       BF_POWER_MINPWR_PWD_ANA_CMPS(BV_POWER_MINPWR_PWD_ANA_CMPS__##e)
#define BFM_POWER_MINPWR_PWD_ANA_CMPS_V(v)      BM_POWER_MINPWR_PWD_ANA_CMPS
#define BP_POWER_MINPWR_ENABLE_OSC              9
#define BM_POWER_MINPWR_ENABLE_OSC              0x200
#define BF_POWER_MINPWR_ENABLE_OSC(v)           (((v) & 0x1) << 9)
#define BFM_POWER_MINPWR_ENABLE_OSC(v)          BM_POWER_MINPWR_ENABLE_OSC
#define BF_POWER_MINPWR_ENABLE_OSC_V(e)         BF_POWER_MINPWR_ENABLE_OSC(BV_POWER_MINPWR_ENABLE_OSC__##e)
#define BFM_POWER_MINPWR_ENABLE_OSC_V(v)        BM_POWER_MINPWR_ENABLE_OSC
#define BP_POWER_MINPWR_SELECT_OSC              8
#define BM_POWER_MINPWR_SELECT_OSC              0x100
#define BF_POWER_MINPWR_SELECT_OSC(v)           (((v) & 0x1) << 8)
#define BFM_POWER_MINPWR_SELECT_OSC(v)          BM_POWER_MINPWR_SELECT_OSC
#define BF_POWER_MINPWR_SELECT_OSC_V(e)         BF_POWER_MINPWR_SELECT_OSC(BV_POWER_MINPWR_SELECT_OSC__##e)
#define BFM_POWER_MINPWR_SELECT_OSC_V(v)        BM_POWER_MINPWR_SELECT_OSC
#define BP_POWER_MINPWR_VBG_OFF                 7
#define BM_POWER_MINPWR_VBG_OFF                 0x80
#define BF_POWER_MINPWR_VBG_OFF(v)              (((v) & 0x1) << 7)
#define BFM_POWER_MINPWR_VBG_OFF(v)             BM_POWER_MINPWR_VBG_OFF
#define BF_POWER_MINPWR_VBG_OFF_V(e)            BF_POWER_MINPWR_VBG_OFF(BV_POWER_MINPWR_VBG_OFF__##e)
#define BFM_POWER_MINPWR_VBG_OFF_V(v)           BM_POWER_MINPWR_VBG_OFF
#define BP_POWER_MINPWR_DOUBLE_FETS             6
#define BM_POWER_MINPWR_DOUBLE_FETS             0x40
#define BF_POWER_MINPWR_DOUBLE_FETS(v)          (((v) & 0x1) << 6)
#define BFM_POWER_MINPWR_DOUBLE_FETS(v)         BM_POWER_MINPWR_DOUBLE_FETS
#define BF_POWER_MINPWR_DOUBLE_FETS_V(e)        BF_POWER_MINPWR_DOUBLE_FETS(BV_POWER_MINPWR_DOUBLE_FETS__##e)
#define BFM_POWER_MINPWR_DOUBLE_FETS_V(v)       BM_POWER_MINPWR_DOUBLE_FETS
#define BP_POWER_MINPWR_HALF_FETS               5
#define BM_POWER_MINPWR_HALF_FETS               0x20
#define BF_POWER_MINPWR_HALF_FETS(v)            (((v) & 0x1) << 5)
#define BFM_POWER_MINPWR_HALF_FETS(v)           BM_POWER_MINPWR_HALF_FETS
#define BF_POWER_MINPWR_HALF_FETS_V(e)          BF_POWER_MINPWR_HALF_FETS(BV_POWER_MINPWR_HALF_FETS__##e)
#define BFM_POWER_MINPWR_HALF_FETS_V(v)         BM_POWER_MINPWR_HALF_FETS
#define BP_POWER_MINPWR_LESSANA_I               4
#define BM_POWER_MINPWR_LESSANA_I               0x10
#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) & 0x1) << 4)
#define BFM_POWER_MINPWR_LESSANA_I(v)           BM_POWER_MINPWR_LESSANA_I
#define BF_POWER_MINPWR_LESSANA_I_V(e)          BF_POWER_MINPWR_LESSANA_I(BV_POWER_MINPWR_LESSANA_I__##e)
#define BFM_POWER_MINPWR_LESSANA_I_V(v)         BM_POWER_MINPWR_LESSANA_I
#define BP_POWER_MINPWR_PWD_XTAL24              3
#define BM_POWER_MINPWR_PWD_XTAL24              0x8
#define BF_POWER_MINPWR_PWD_XTAL24(v)           (((v) & 0x1) << 3)
#define BFM_POWER_MINPWR_PWD_XTAL24(v)          BM_POWER_MINPWR_PWD_XTAL24
#define BF_POWER_MINPWR_PWD_XTAL24_V(e)         BF_POWER_MINPWR_PWD_XTAL24(BV_POWER_MINPWR_PWD_XTAL24__##e)
#define BFM_POWER_MINPWR_PWD_XTAL24_V(v)        BM_POWER_MINPWR_PWD_XTAL24
#define BP_POWER_MINPWR_DC_STOPCLK              2
#define BM_POWER_MINPWR_DC_STOPCLK              0x4
#define BF_POWER_MINPWR_DC_STOPCLK(v)           (((v) & 0x1) << 2)
#define BFM_POWER_MINPWR_DC_STOPCLK(v)          BM_POWER_MINPWR_DC_STOPCLK
#define BF_POWER_MINPWR_DC_STOPCLK_V(e)         BF_POWER_MINPWR_DC_STOPCLK(BV_POWER_MINPWR_DC_STOPCLK__##e)
#define BFM_POWER_MINPWR_DC_STOPCLK_V(v)        BM_POWER_MINPWR_DC_STOPCLK
#define BP_POWER_MINPWR_EN_DC_PFM               1
#define BM_POWER_MINPWR_EN_DC_PFM               0x2
#define BF_POWER_MINPWR_EN_DC_PFM(v)            (((v) & 0x1) << 1)
#define BFM_POWER_MINPWR_EN_DC_PFM(v)           BM_POWER_MINPWR_EN_DC_PFM
#define BF_POWER_MINPWR_EN_DC_PFM_V(e)          BF_POWER_MINPWR_EN_DC_PFM(BV_POWER_MINPWR_EN_DC_PFM__##e)
#define BFM_POWER_MINPWR_EN_DC_PFM_V(v)         BM_POWER_MINPWR_EN_DC_PFM
#define BP_POWER_MINPWR_DC_HALFCLK              0
#define BM_POWER_MINPWR_DC_HALFCLK              0x1
#define BF_POWER_MINPWR_DC_HALFCLK(v)           (((v) & 0x1) << 0)
#define BFM_POWER_MINPWR_DC_HALFCLK(v)          BM_POWER_MINPWR_DC_HALFCLK
#define BF_POWER_MINPWR_DC_HALFCLK_V(e)         BF_POWER_MINPWR_DC_HALFCLK(BV_POWER_MINPWR_DC_HALFCLK__##e)
#define BFM_POWER_MINPWR_DC_HALFCLK_V(v)        BM_POWER_MINPWR_DC_HALFCLK

#define HW_POWER_CHARGE                                 HW(POWER_CHARGE)
#define HWA_POWER_CHARGE                                (0x80044000 + 0x30)
#define HWT_POWER_CHARGE                                HWIO_32_RW
#define HWN_POWER_CHARGE                                POWER_CHARGE
#define HWI_POWER_CHARGE                                
#define HW_POWER_CHARGE_SET                             HW(POWER_CHARGE_SET)
#define HWA_POWER_CHARGE_SET                            (HWA_POWER_CHARGE + 0x4)
#define HWT_POWER_CHARGE_SET                            HWIO_32_WO
#define HWN_POWER_CHARGE_SET                            POWER_CHARGE
#define HWI_POWER_CHARGE_SET                            
#define HW_POWER_CHARGE_CLR                             HW(POWER_CHARGE_CLR)
#define HWA_POWER_CHARGE_CLR                            (HWA_POWER_CHARGE + 0x8)
#define HWT_POWER_CHARGE_CLR                            HWIO_32_WO
#define HWN_POWER_CHARGE_CLR                            POWER_CHARGE
#define HWI_POWER_CHARGE_CLR                            
#define HW_POWER_CHARGE_TOG                             HW(POWER_CHARGE_TOG)
#define HWA_POWER_CHARGE_TOG                            (HWA_POWER_CHARGE + 0xc)
#define HWT_POWER_CHARGE_TOG                            HWIO_32_WO
#define HWN_POWER_CHARGE_TOG                            POWER_CHARGE
#define HWI_POWER_CHARGE_TOG                            
#define BP_POWER_CHARGE_RSRVD4                          27
#define BM_POWER_CHARGE_RSRVD4                          0xf8000000
#define BF_POWER_CHARGE_RSRVD4(v)                       (((v) & 0x1f) << 27)
#define BFM_POWER_CHARGE_RSRVD4(v)                      BM_POWER_CHARGE_RSRVD4
#define BF_POWER_CHARGE_RSRVD4_V(e)                     BF_POWER_CHARGE_RSRVD4(BV_POWER_CHARGE_RSRVD4__##e)
#define BFM_POWER_CHARGE_RSRVD4_V(v)                    BM_POWER_CHARGE_RSRVD4
#define BP_POWER_CHARGE_ADJ_VOLT                        24
#define BM_POWER_CHARGE_ADJ_VOLT                        0x7000000
#define BF_POWER_CHARGE_ADJ_VOLT(v)                     (((v) & 0x7) << 24)
#define BFM_POWER_CHARGE_ADJ_VOLT(v)                    BM_POWER_CHARGE_ADJ_VOLT
#define BF_POWER_CHARGE_ADJ_VOLT_V(e)                   BF_POWER_CHARGE_ADJ_VOLT(BV_POWER_CHARGE_ADJ_VOLT__##e)
#define BFM_POWER_CHARGE_ADJ_VOLT_V(v)                  BM_POWER_CHARGE_ADJ_VOLT
#define BP_POWER_CHARGE_RSRVD3                          23
#define BM_POWER_CHARGE_RSRVD3                          0x800000
#define BF_POWER_CHARGE_RSRVD3(v)                       (((v) & 0x1) << 23)
#define BFM_POWER_CHARGE_RSRVD3(v)                      BM_POWER_CHARGE_RSRVD3
#define BF_POWER_CHARGE_RSRVD3_V(e)                     BF_POWER_CHARGE_RSRVD3(BV_POWER_CHARGE_RSRVD3__##e)
#define BFM_POWER_CHARGE_RSRVD3_V(v)                    BM_POWER_CHARGE_RSRVD3
#define BP_POWER_CHARGE_ENABLE_LOAD                     22
#define BM_POWER_CHARGE_ENABLE_LOAD                     0x400000
#define BF_POWER_CHARGE_ENABLE_LOAD(v)                  (((v) & 0x1) << 22)
#define BFM_POWER_CHARGE_ENABLE_LOAD(v)                 BM_POWER_CHARGE_ENABLE_LOAD
#define BF_POWER_CHARGE_ENABLE_LOAD_V(e)                BF_POWER_CHARGE_ENABLE_LOAD(BV_POWER_CHARGE_ENABLE_LOAD__##e)
#define BFM_POWER_CHARGE_ENABLE_LOAD_V(v)               BM_POWER_CHARGE_ENABLE_LOAD
#define BP_POWER_CHARGE_ENABLE_CHARGER_RESISTORS        21
#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS        0x200000
#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v)     (((v) & 0x1) << 21)
#define BFM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v)    BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS
#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS_V(e)   BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(BV_POWER_CHARGE_ENABLE_CHARGER_RESISTORS__##e)
#define BFM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS_V(v)  BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS
#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT             20
#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT             0x100000
#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)          (((v) & 0x1) << 20)
#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT(v)         BM_POWER_CHARGE_ENABLE_FAULT_DETECT
#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT_V(e)        BF_POWER_CHARGE_ENABLE_FAULT_DETECT(BV_POWER_CHARGE_ENABLE_FAULT_DETECT__##e)
#define BFM_POWER_CHARGE_ENABLE_FAULT_DETECT_V(v)       BM_POWER_CHARGE_ENABLE_FAULT_DETECT
#define BP_POWER_CHARGE_CHRG_STS_OFF                    19
#define BM_POWER_CHARGE_CHRG_STS_OFF                    0x80000
#define BF_POWER_CHARGE_CHRG_STS_OFF(v)                 (((v) & 0x1) << 19)
#define BFM_POWER_CHARGE_CHRG_STS_OFF(v)                BM_POWER_CHARGE_CHRG_STS_OFF
#define BF_POWER_CHARGE_CHRG_STS_OFF_V(e)               BF_POWER_CHARGE_CHRG_STS_OFF(BV_POWER_CHARGE_CHRG_STS_OFF__##e)
#define BFM_POWER_CHARGE_CHRG_STS_OFF_V(v)              BM_POWER_CHARGE_CHRG_STS_OFF
#define BP_POWER_CHARGE_LIION_4P1                       18
#define BM_POWER_CHARGE_LIION_4P1                       0x40000
#define BF_POWER_CHARGE_LIION_4P1(v)                    (((v) & 0x1) << 18)
#define BFM_POWER_CHARGE_LIION_4P1(v)                   BM_POWER_CHARGE_LIION_4P1
#define BF_POWER_CHARGE_LIION_4P1_V(e)                  BF_POWER_CHARGE_LIION_4P1(BV_POWER_CHARGE_LIION_4P1__##e)
#define BFM_POWER_CHARGE_LIION_4P1_V(v)                 BM_POWER_CHARGE_LIION_4P1
#define BP_POWER_CHARGE_USE_EXTERN_R                    17
#define BM_POWER_CHARGE_USE_EXTERN_R                    0x20000
#define BF_POWER_CHARGE_USE_EXTERN_R(v)                 (((v) & 0x1) << 17)
#define BFM_POWER_CHARGE_USE_EXTERN_R(v)                BM_POWER_CHARGE_USE_EXTERN_R
#define BF_POWER_CHARGE_USE_EXTERN_R_V(e)               BF_POWER_CHARGE_USE_EXTERN_R(BV_POWER_CHARGE_USE_EXTERN_R__##e)
#define BFM_POWER_CHARGE_USE_EXTERN_R_V(v)              BM_POWER_CHARGE_USE_EXTERN_R
#define BP_POWER_CHARGE_PWD_BATTCHRG                    16
#define BM_POWER_CHARGE_PWD_BATTCHRG                    0x10000
#define BF_POWER_CHARGE_PWD_BATTCHRG(v)                 (((v) & 0x1) << 16)
#define BFM_POWER_CHARGE_PWD_BATTCHRG(v)                BM_POWER_CHARGE_PWD_BATTCHRG
#define BF_POWER_CHARGE_PWD_BATTCHRG_V(e)               BF_POWER_CHARGE_PWD_BATTCHRG(BV_POWER_CHARGE_PWD_BATTCHRG__##e)
#define BFM_POWER_CHARGE_PWD_BATTCHRG_V(v)              BM_POWER_CHARGE_PWD_BATTCHRG
#define BP_POWER_CHARGE_RSRVD2                          12
#define BM_POWER_CHARGE_RSRVD2                          0xf000
#define BF_POWER_CHARGE_RSRVD2(v)                       (((v) & 0xf) << 12)
#define BFM_POWER_CHARGE_RSRVD2(v)                      BM_POWER_CHARGE_RSRVD2
#define BF_POWER_CHARGE_RSRVD2_V(e)                     BF_POWER_CHARGE_RSRVD2(BV_POWER_CHARGE_RSRVD2__##e)
#define BFM_POWER_CHARGE_RSRVD2_V(v)                    BM_POWER_CHARGE_RSRVD2
#define BP_POWER_CHARGE_STOP_ILIMIT                     8
#define BM_POWER_CHARGE_STOP_ILIMIT                     0xf00
#define BF_POWER_CHARGE_STOP_ILIMIT(v)                  (((v) & 0xf) << 8)
#define BFM_POWER_CHARGE_STOP_ILIMIT(v)                 BM_POWER_CHARGE_STOP_ILIMIT
#define BF_POWER_CHARGE_STOP_ILIMIT_V(e)                BF_POWER_CHARGE_STOP_ILIMIT(BV_POWER_CHARGE_STOP_ILIMIT__##e)
#define BFM_POWER_CHARGE_STOP_ILIMIT_V(v)               BM_POWER_CHARGE_STOP_ILIMIT
#define BP_POWER_CHARGE_RSRVD1                          6
#define BM_POWER_CHARGE_RSRVD1                          0xc0
#define BF_POWER_CHARGE_RSRVD1(v)                       (((v) & 0x3) << 6)
#define BFM_POWER_CHARGE_RSRVD1(v)                      BM_POWER_CHARGE_RSRVD1
#define BF_POWER_CHARGE_RSRVD1_V(e)                     BF_POWER_CHARGE_RSRVD1(BV_POWER_CHARGE_RSRVD1__##e)
#define BFM_POWER_CHARGE_RSRVD1_V(v)                    BM_POWER_CHARGE_RSRVD1
#define BP_POWER_CHARGE_BATTCHRG_I                      0
#define BM_POWER_CHARGE_BATTCHRG_I                      0x3f
#define BF_POWER_CHARGE_BATTCHRG_I(v)                   (((v) & 0x3f) << 0)
#define BFM_POWER_CHARGE_BATTCHRG_I(v)                  BM_POWER_CHARGE_BATTCHRG_I
#define BF_POWER_CHARGE_BATTCHRG_I_V(e)                 BF_POWER_CHARGE_BATTCHRG_I(BV_POWER_CHARGE_BATTCHRG_I__##e)
#define BFM_POWER_CHARGE_BATTCHRG_I_V(v)                BM_POWER_CHARGE_BATTCHRG_I

#define HW_POWER_VDDDCTRL                           HW(POWER_VDDDCTRL)
#define HWA_POWER_VDDDCTRL                          (0x80044000 + 0x40)
#define HWT_POWER_VDDDCTRL                          HWIO_32_RW
#define HWN_POWER_VDDDCTRL                          POWER_VDDDCTRL
#define HWI_POWER_VDDDCTRL                          
#define BP_POWER_VDDDCTRL_ADJTN                     28
#define BM_POWER_VDDDCTRL_ADJTN                     0xf0000000
#define BF_POWER_VDDDCTRL_ADJTN(v)                  (((v) & 0xf) << 28)
#define BFM_POWER_VDDDCTRL_ADJTN(v)                 BM_POWER_VDDDCTRL_ADJTN
#define BF_POWER_VDDDCTRL_ADJTN_V(e)                BF_POWER_VDDDCTRL_ADJTN(BV_POWER_VDDDCTRL_ADJTN__##e)
#define BFM_POWER_VDDDCTRL_ADJTN_V(v)               BM_POWER_VDDDCTRL_ADJTN
#define BP_POWER_VDDDCTRL_RSRVD4                    24
#define BM_POWER_VDDDCTRL_RSRVD4                    0xf000000
#define BF_POWER_VDDDCTRL_RSRVD4(v)                 (((v) & 0xf) << 24)
#define BFM_POWER_VDDDCTRL_RSRVD4(v)                BM_POWER_VDDDCTRL_RSRVD4
#define BF_POWER_VDDDCTRL_RSRVD4_V(e)               BF_POWER_VDDDCTRL_RSRVD4(BV_POWER_VDDDCTRL_RSRVD4__##e)
#define BFM_POWER_VDDDCTRL_RSRVD4_V(v)              BM_POWER_VDDDCTRL_RSRVD4
#define BP_POWER_VDDDCTRL_PWDN_BRNOUT               23
#define BM_POWER_VDDDCTRL_PWDN_BRNOUT               0x800000
#define BF_POWER_VDDDCTRL_PWDN_BRNOUT(v)            (((v) & 0x1) << 23)
#define BFM_POWER_VDDDCTRL_PWDN_BRNOUT(v)           BM_POWER_VDDDCTRL_PWDN_BRNOUT
#define BF_POWER_VDDDCTRL_PWDN_BRNOUT_V(e)          BF_POWER_VDDDCTRL_PWDN_BRNOUT(BV_POWER_VDDDCTRL_PWDN_BRNOUT__##e)
#define BFM_POWER_VDDDCTRL_PWDN_BRNOUT_V(v)         BM_POWER_VDDDCTRL_PWDN_BRNOUT
#define BP_POWER_VDDDCTRL_DISABLE_STEPPING          22
#define BM_POWER_VDDDCTRL_DISABLE_STEPPING          0x400000
#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 22)
#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING(v)      BM_POWER_VDDDCTRL_DISABLE_STEPPING
#define BF_POWER_VDDDCTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDDCTRL_DISABLE_STEPPING(BV_POWER_VDDDCTRL_DISABLE_STEPPING__##e)
#define BFM_POWER_VDDDCTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDDCTRL_DISABLE_STEPPING
#define BP_POWER_VDDDCTRL_ENABLE_LINREG             21
#define BM_POWER_VDDDCTRL_ENABLE_LINREG             0x200000
#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 21)
#define BFM_POWER_VDDDCTRL_ENABLE_LINREG(v)         BM_POWER_VDDDCTRL_ENABLE_LINREG
#define BF_POWER_VDDDCTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDDCTRL_ENABLE_LINREG(BV_POWER_VDDDCTRL_ENABLE_LINREG__##e)
#define BFM_POWER_VDDDCTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDDCTRL_ENABLE_LINREG
#define BP_POWER_VDDDCTRL_DISABLE_FET               20
#define BM_POWER_VDDDCTRL_DISABLE_FET               0x100000
#define BF_POWER_VDDDCTRL_DISABLE_FET(v)            (((v) & 0x1) << 20)
#define BFM_POWER_VDDDCTRL_DISABLE_FET(v)           BM_POWER_VDDDCTRL_DISABLE_FET
#define BF_POWER_VDDDCTRL_DISABLE_FET_V(e)          BF_POWER_VDDDCTRL_DISABLE_FET(BV_POWER_VDDDCTRL_DISABLE_FET__##e)
#define BFM_POWER_VDDDCTRL_DISABLE_FET_V(v)         BM_POWER_VDDDCTRL_DISABLE_FET
#define BP_POWER_VDDDCTRL_RSRVD3                    18
#define BM_POWER_VDDDCTRL_RSRVD3                    0xc0000
#define BF_POWER_VDDDCTRL_RSRVD3(v)                 (((v) & 0x3) << 18)
#define BFM_POWER_VDDDCTRL_RSRVD3(v)                BM_POWER_VDDDCTRL_RSRVD3
#define BF_POWER_VDDDCTRL_RSRVD3_V(e)               BF_POWER_VDDDCTRL_RSRVD3(BV_POWER_VDDDCTRL_RSRVD3__##e)
#define BFM_POWER_VDDDCTRL_RSRVD3_V(v)              BM_POWER_VDDDCTRL_RSRVD3
#define BP_POWER_VDDDCTRL_LINREG_OFFSET             16
#define BM_POWER_VDDDCTRL_LINREG_OFFSET             0x30000
#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 16)
#define BFM_POWER_VDDDCTRL_LINREG_OFFSET(v)         BM_POWER_VDDDCTRL_LINREG_OFFSET
#define BF_POWER_VDDDCTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDDCTRL_LINREG_OFFSET(BV_POWER_VDDDCTRL_LINREG_OFFSET__##e)
#define BFM_POWER_VDDDCTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDDCTRL_LINREG_OFFSET
#define BP_POWER_VDDDCTRL_RSRVD2                    11
#define BM_POWER_VDDDCTRL_RSRVD2                    0xf800
#define BF_POWER_VDDDCTRL_RSRVD2(v)                 (((v) & 0x1f) << 11)
#define BFM_POWER_VDDDCTRL_RSRVD2(v)                BM_POWER_VDDDCTRL_RSRVD2
#define BF_POWER_VDDDCTRL_RSRVD2_V(e)               BF_POWER_VDDDCTRL_RSRVD2(BV_POWER_VDDDCTRL_RSRVD2__##e)
#define BFM_POWER_VDDDCTRL_RSRVD2_V(v)              BM_POWER_VDDDCTRL_RSRVD2
#define BP_POWER_VDDDCTRL_BO_OFFSET                 8
#define BM_POWER_VDDDCTRL_BO_OFFSET                 0x700
#define BF_POWER_VDDDCTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
#define BFM_POWER_VDDDCTRL_BO_OFFSET(v)             BM_POWER_VDDDCTRL_BO_OFFSET
#define BF_POWER_VDDDCTRL_BO_OFFSET_V(e)            BF_POWER_VDDDCTRL_BO_OFFSET(BV_POWER_VDDDCTRL_BO_OFFSET__##e)
#define BFM_POWER_VDDDCTRL_BO_OFFSET_V(v)           BM_POWER_VDDDCTRL_BO_OFFSET
#define BP_POWER_VDDDCTRL_RSRVD1                    5
#define BM_POWER_VDDDCTRL_RSRVD1                    0xe0
#define BF_POWER_VDDDCTRL_RSRVD1(v)                 (((v) & 0x7) << 5)
#define BFM_POWER_VDDDCTRL_RSRVD1(v)                BM_POWER_VDDDCTRL_RSRVD1
#define BF_POWER_VDDDCTRL_RSRVD1_V(e)               BF_POWER_VDDDCTRL_RSRVD1(BV_POWER_VDDDCTRL_RSRVD1__##e)
#define BFM_POWER_VDDDCTRL_RSRVD1_V(v)              BM_POWER_VDDDCTRL_RSRVD1
#define BP_POWER_VDDDCTRL_TRG                       0
#define BM_POWER_VDDDCTRL_TRG                       0x1f
#define BF_POWER_VDDDCTRL_TRG(v)                    (((v) & 0x1f) << 0)
#define BFM_POWER_VDDDCTRL_TRG(v)                   BM_POWER_VDDDCTRL_TRG
#define BF_POWER_VDDDCTRL_TRG_V(e)                  BF_POWER_VDDDCTRL_TRG(BV_POWER_VDDDCTRL_TRG__##e)
#define BFM_POWER_VDDDCTRL_TRG_V(v)                 BM_POWER_VDDDCTRL_TRG

#define HW_POWER_VDDACTRL                           HW(POWER_VDDACTRL)
#define HWA_POWER_VDDACTRL                          (0x80044000 + 0x50)
#define HWT_POWER_VDDACTRL                          HWIO_32_RW
#define HWN_POWER_VDDACTRL                          POWER_VDDACTRL
#define HWI_POWER_VDDACTRL                          
#define BP_POWER_VDDACTRL_RSRVD4                    20
#define BM_POWER_VDDACTRL_RSRVD4                    0xfff00000
#define BF_POWER_VDDACTRL_RSRVD4(v)                 (((v) & 0xfff) << 20)
#define BFM_POWER_VDDACTRL_RSRVD4(v)                BM_POWER_VDDACTRL_RSRVD4
#define BF_POWER_VDDACTRL_RSRVD4_V(e)               BF_POWER_VDDACTRL_RSRVD4(BV_POWER_VDDACTRL_RSRVD4__##e)
#define BFM_POWER_VDDACTRL_RSRVD4_V(v)              BM_POWER_VDDACTRL_RSRVD4
#define BP_POWER_VDDACTRL_PWDN_BRNOUT               19
#define BM_POWER_VDDACTRL_PWDN_BRNOUT               0x80000
#define BF_POWER_VDDACTRL_PWDN_BRNOUT(v)            (((v) & 0x1) << 19)
#define BFM_POWER_VDDACTRL_PWDN_BRNOUT(v)           BM_POWER_VDDACTRL_PWDN_BRNOUT
#define BF_POWER_VDDACTRL_PWDN_BRNOUT_V(e)          BF_POWER_VDDACTRL_PWDN_BRNOUT(BV_POWER_VDDACTRL_PWDN_BRNOUT__##e)
#define BFM_POWER_VDDACTRL_PWDN_BRNOUT_V(v)         BM_POWER_VDDACTRL_PWDN_BRNOUT
#define BP_POWER_VDDACTRL_DISABLE_STEPPING          18
#define BM_POWER_VDDACTRL_DISABLE_STEPPING          0x40000
#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)       (((v) & 0x1) << 18)
#define BFM_POWER_VDDACTRL_DISABLE_STEPPING(v)      BM_POWER_VDDACTRL_DISABLE_STEPPING
#define BF_POWER_VDDACTRL_DISABLE_STEPPING_V(e)     BF_POWER_VDDACTRL_DISABLE_STEPPING(BV_POWER_VDDACTRL_DISABLE_STEPPING__##e)
#define BFM_POWER_VDDACTRL_DISABLE_STEPPING_V(v)    BM_POWER_VDDACTRL_DISABLE_STEPPING
#define BP_POWER_VDDACTRL_ENABLE_LINREG             17
#define BM_POWER_VDDACTRL_ENABLE_LINREG             0x20000
#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)          (((v) & 0x1) << 17)
#define BFM_POWER_VDDACTRL_ENABLE_LINREG(v)         BM_POWER_VDDACTRL_ENABLE_LINREG
#define BF_POWER_VDDACTRL_ENABLE_LINREG_V(e)        BF_POWER_VDDACTRL_ENABLE_LINREG(BV_POWER_VDDACTRL_ENABLE_LINREG__##e)
#define BFM_POWER_VDDACTRL_ENABLE_LINREG_V(v)       BM_POWER_VDDACTRL_ENABLE_LINREG
#define BP_POWER_VDDACTRL_DISABLE_FET               16
#define BM_POWER_VDDACTRL_DISABLE_FET               0x10000
#define BF_POWER_VDDACTRL_DISABLE_FET(v)            (((v) & 0x1) << 16)
#define BFM_POWER_VDDACTRL_DISABLE_FET(v)           BM_POWER_VDDACTRL_DISABLE_FET
#define BF_POWER_VDDACTRL_DISABLE_FET_V(e)          BF_POWER_VDDACTRL_DISABLE_FET(BV_POWER_VDDACTRL_DISABLE_FET__##e)
#define BFM_POWER_VDDACTRL_DISABLE_FET_V(v)         BM_POWER_VDDACTRL_DISABLE_FET
#define BP_POWER_VDDACTRL_RSRVD3                    14
#define BM_POWER_VDDACTRL_RSRVD3                    0xc000
#define BF_POWER_VDDACTRL_RSRVD3(v)                 (((v) & 0x3) << 14)
#define BFM_POWER_VDDACTRL_RSRVD3(v)                BM_POWER_VDDACTRL_RSRVD3
#define BF_POWER_VDDACTRL_RSRVD3_V(e)               BF_POWER_VDDACTRL_RSRVD3(BV_POWER_VDDACTRL_RSRVD3__##e)
#define BFM_POWER_VDDACTRL_RSRVD3_V(v)              BM_POWER_VDDACTRL_RSRVD3
#define BP_POWER_VDDACTRL_LINREG_OFFSET             12
#define BM_POWER_VDDACTRL_LINREG_OFFSET             0x3000
#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)          (((v) & 0x3) << 12)
#define BFM_POWER_VDDACTRL_LINREG_OFFSET(v)         BM_POWER_VDDACTRL_LINREG_OFFSET
#define BF_POWER_VDDACTRL_LINREG_OFFSET_V(e)        BF_POWER_VDDACTRL_LINREG_OFFSET(BV_POWER_VDDACTRL_LINREG_OFFSET__##e)
#define BFM_POWER_VDDACTRL_LINREG_OFFSET_V(v)       BM_POWER_VDDACTRL_LINREG_OFFSET
#define BP_POWER_VDDACTRL_RSRVD2                    11
#define BM_POWER_VDDACTRL_RSRVD2                    0x800
#define BF_POWER_VDDACTRL_RSRVD2(v)                 (((v) & 0x1) << 11)
#define BFM_POWER_VDDACTRL_RSRVD2(v)                BM_POWER_VDDACTRL_RSRVD2
#define BF_POWER_VDDACTRL_RSRVD2_V(e)               BF_POWER_VDDACTRL_RSRVD2(BV_POWER_VDDACTRL_RSRVD2__##e)
#define BFM_POWER_VDDACTRL_RSRVD2_V(v)              BM_POWER_VDDACTRL_RSRVD2
#define BP_POWER_VDDACTRL_BO_OFFSET                 8
#define BM_POWER_VDDACTRL_BO_OFFSET                 0x700
#define BF_POWER_VDDACTRL_BO_OFFSET(v)              (((v) & 0x7) << 8)
#define BFM_POWER_VDDACTRL_BO_OFFSET(v)             BM_POWER_VDDACTRL_BO_OFFSET
#define BF_POWER_VDDACTRL_BO_OFFSET_V(e)            BF_POWER_VDDACTRL_BO_OFFSET(BV_POWER_VDDACTRL_BO_OFFSET__##e)
#define BFM_POWER_VDDACTRL_BO_OFFSET_V(v)           BM_POWER_VDDACTRL_BO_OFFSET
#define BP_POWER_VDDACTRL_RSRVD1                    5
#define BM_POWER_VDDACTRL_RSRVD1                    0xe0
#define BF_POWER_VDDACTRL_RSRVD1(v)                 (((v) & 0x7) << 5)
#define BFM_POWER_VDDACTRL_RSRVD1(v)                BM_POWER_VDDACTRL_RSRVD1
#define BF_POWER_VDDACTRL_RSRVD1_V(e)               BF_POWER_VDDACTRL_RSRVD1(BV_POWER_VDDACTRL_RSRVD1__##e)
#define BFM_POWER_VDDACTRL_RSRVD1_V(v)              BM_POWER_VDDACTRL_RSRVD1
#define BP_POWER_VDDACTRL_TRG                       0
#define BM_POWER_VDDACTRL_TRG                       0x1f
#define BF_POWER_VDDACTRL_TRG(v)                    (((v) & 0x1f) << 0)
#define BFM_POWER_VDDACTRL_TRG(v)                   BM_POWER_VDDACTRL_TRG
#define BF_POWER_VDDACTRL_TRG_V(e)                  BF_POWER_VDDACTRL_TRG(BV_POWER_VDDACTRL_TRG__##e)
#define BFM_POWER_VDDACTRL_TRG_V(v)                 BM_POWER_VDDACTRL_TRG

#define HW_POWER_VDDIOCTRL                          HW(POWER_VDDIOCTRL)
#define HWA_POWER_VDDIOCTRL                         (0x80044000 + 0x60)
#define HWT_POWER_VDDIOCTRL                         HWIO_32_RW
#define HWN_POWER_VDDIOCTRL                         POWER_VDDIOCTRL
#define HWI_POWER_VDDIOCTRL                         
#define BP_POWER_VDDIOCTRL_RSRVD5                   24
#define BM_POWER_VDDIOCTRL_RSRVD5                   0xff000000
#define BF_POWER_VDDIOCTRL_RSRVD5(v)                (((v) & 0xff) << 24)
#define BFM_POWER_VDDIOCTRL_RSRVD5(v)               BM_POWER_VDDIOCTRL_RSRVD5
#define BF_POWER_VDDIOCTRL_RSRVD5_V(e)              BF_POWER_VDDIOCTRL_RSRVD5(BV_POWER_VDDIOCTRL_RSRVD5__##e)
#define BFM_POWER_VDDIOCTRL_RSRVD5_V(v)             BM_POWER_VDDIOCTRL_RSRVD5
#define BP_POWER_VDDIOCTRL_ADJTN                    20
#define BM_POWER_VDDIOCTRL_ADJTN                    0xf00000
#define BF_POWER_VDDIOCTRL_ADJTN(v)                 (((v) & 0xf) << 20)
#define BFM_POWER_VDDIOCTRL_ADJTN(v)                BM_POWER_VDDIOCTRL_ADJTN
#define BF_POWER_VDDIOCTRL_ADJTN_V(e)               BF_POWER_VDDIOCTRL_ADJTN(BV_POWER_VDDIOCTRL_ADJTN__##e)
#define BFM_POWER_VDDIOCTRL_ADJTN_V(v)              BM_POWER_VDDIOCTRL_ADJTN
#define BP_POWER_VDDIOCTRL_RSRVD4                   19
#define BM_POWER_VDDIOCTRL_RSRVD4                   0x80000
#define BF_POWER_VDDIOCTRL_RSRVD4(v)                (((v) & 0x1) << 19)
#define BFM_POWER_VDDIOCTRL_RSRVD4(v)               BM_POWER_VDDIOCTRL_RSRVD4
#define BF_POWER_VDDIOCTRL_RSRVD4_V(e)              BF_POWER_VDDIOCTRL_RSRVD4(BV_POWER_VDDIOCTRL_RSRVD4__##e)
#define BFM_POWER_VDDIOCTRL_RSRVD4_V(v)             BM_POWER_VDDIOCTRL_RSRVD4
#define BP_POWER_VDDIOCTRL_PWDN_BRNOUT              18
#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT              0x40000
#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT(v)           (((v) & 0x1) << 18)
#define BFM_POWER_VDDIOCTRL_PWDN_BRNOUT(v)          BM_POWER_VDDIOCTRL_PWDN_BRNOUT
#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT_V(e)         BF_POWER_VDDIOCTRL_PWDN_BRNOUT(BV_POWER_VDDIOCTRL_PWDN_BRNOUT__##e)
#define BFM_POWER_VDDIOCTRL_PWDN_BRNOUT_V(v)        BM_POWER_VDDIOCTRL_PWDN_BRNOUT
#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING         17
#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING         0x20000
#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)      (((v) & 0x1) << 17)
#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING(v)     BM_POWER_VDDIOCTRL_DISABLE_STEPPING
#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING_V(e)    BF_POWER_VDDIOCTRL_DISABLE_STEPPING(BV_POWER_VDDIOCTRL_DISABLE_STEPPING__##e)
#define BFM_POWER_VDDIOCTRL_DISABLE_STEPPING_V(v)   BM_POWER_VDDIOCTRL_DISABLE_STEPPING
#define BP_POWER_VDDIOCTRL_DISABLE_FET              16
#define BM_POWER_VDDIOCTRL_DISABLE_FET              0x10000
#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)           (((v) & 0x1) << 16)
#define BFM_POWER_VDDIOCTRL_DISABLE_FET(v)          BM_POWER_VDDIOCTRL_DISABLE_FET
#define BF_POWER_VDDIOCTRL_DISABLE_FET_V(e)         BF_POWER_VDDIOCTRL_DISABLE_FET(BV_POWER_VDDIOCTRL_DISABLE_FET__##e)
#define BFM_POWER_VDDIOCTRL_DISABLE_FET_V(v)        BM_POWER_VDDIOCTRL_DISABLE_FET
#define BP_POWER_VDDIOCTRL_RSRVD3                   14
#define BM_POWER_VDDIOCTRL_RSRVD3                   0xc000
#define BF_POWER_VDDIOCTRL_RSRVD3(v)                (((v) & 0x3) << 14)
#define BFM_POWER_VDDIOCTRL_RSRVD3(v)               BM_POWER_VDDIOCTRL_RSRVD3
#define BF_POWER_VDDIOCTRL_RSRVD3_V(e)              BF_POWER_VDDIOCTRL_RSRVD3(BV_POWER_VDDIOCTRL_RSRVD3__##e)
#define BFM_POWER_VDDIOCTRL_RSRVD3_V(v)             BM_POWER_VDDIOCTRL_RSRVD3
#define BP_POWER_VDDIOCTRL_LINREG_OFFSET            12
#define BM_POWER_VDDIOCTRL_LINREG_OFFSET            0x3000
#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)         (((v) & 0x3) << 12)
#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET(v)        BM_POWER_VDDIOCTRL_LINREG_OFFSET
#define BF_POWER_VDDIOCTRL_LINREG_OFFSET_V(e)       BF_POWER_VDDIOCTRL_LINREG_OFFSET(BV_POWER_VDDIOCTRL_LINREG_OFFSET__##e)
#define BFM_POWER_VDDIOCTRL_LINREG_OFFSET_V(v)      BM_POWER_VDDIOCTRL_LINREG_OFFSET
#define BP_POWER_VDDIOCTRL_RSRVD2                   11
#define BM_POWER_VDDIOCTRL_RSRVD2                   0x800
#define BF_POWER_VDDIOCTRL_RSRVD2(v)                (((v) & 0x1) << 11)
#define BFM_POWER_VDDIOCTRL_RSRVD2(v)               BM_POWER_VDDIOCTRL_RSRVD2
#define BF_POWER_VDDIOCTRL_RSRVD2_V(e)              BF_POWER_VDDIOCTRL_RSRVD2(BV_POWER_VDDIOCTRL_RSRVD2__##e)
#define BFM_POWER_VDDIOCTRL_RSRVD2_V(v)             BM_POWER_VDDIOCTRL_RSRVD2
#define BP_POWER_VDDIOCTRL_BO_OFFSET                8
#define BM_POWER_VDDIOCTRL_BO_OFFSET                0x700
#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)             (((v) & 0x7) << 8)
#define BFM_POWER_VDDIOCTRL_BO_OFFSET(v)            BM_POWER_VDDIOCTRL_BO_OFFSET
#define BF_POWER_VDDIOCTRL_BO_OFFSET_V(e)           BF_POWER_VDDIOCTRL_BO_OFFSET(BV_POWER_VDDIOCTRL_BO_OFFSET__##e)
#define BFM_POWER_VDDIOCTRL_BO_OFFSET_V(v)          BM_POWER_VDDIOCTRL_BO_OFFSET
#define BP_POWER_VDDIOCTRL_RSRVD1                   5
#define BM_POWER_VDDIOCTRL_RSRVD1                   0xe0
#define BF_POWER_VDDIOCTRL_RSRVD1(v)                (((v) & 0x7) << 5)
#define BFM_POWER_VDDIOCTRL_RSRVD1(v)               BM_POWER_VDDIOCTRL_RSRVD1
#define BF_POWER_VDDIOCTRL_RSRVD1_V(e)              BF_POWER_VDDIOCTRL_RSRVD1(BV_POWER_VDDIOCTRL_RSRVD1__##e)
#define BFM_POWER_VDDIOCTRL_RSRVD1_V(v)             BM_POWER_VDDIOCTRL_RSRVD1
#define BP_POWER_VDDIOCTRL_TRG                      0
#define BM_POWER_VDDIOCTRL_TRG                      0x1f
#define BF_POWER_VDDIOCTRL_TRG(v)                   (((v) & 0x1f) << 0)
#define BFM_POWER_VDDIOCTRL_TRG(v)                  BM_POWER_VDDIOCTRL_TRG
#define BF_POWER_VDDIOCTRL_TRG_V(e)                 BF_POWER_VDDIOCTRL_TRG(BV_POWER_VDDIOCTRL_TRG__##e)
#define BFM_POWER_VDDIOCTRL_TRG_V(v)                BM_POWER_VDDIOCTRL_TRG

#define HW_POWER_VDDMEMCTRL                         HW(POWER_VDDMEMCTRL)
#define HWA_POWER_VDDMEMCTRL                        (0x80044000 + 0x70)
#define HWT_POWER_VDDMEMCTRL                        HWIO_32_RW
#define HWN_POWER_VDDMEMCTRL                        POWER_VDDMEMCTRL
#define HWI_POWER_VDDMEMCTRL                        
#define BP_POWER_VDDMEMCTRL_RSRVD2                  11
#define BM_POWER_VDDMEMCTRL_RSRVD2                  0xfffff800
#define BF_POWER_VDDMEMCTRL_RSRVD2(v)               (((v) & 0x1fffff) << 11)
#define BFM_POWER_VDDMEMCTRL_RSRVD2(v)              BM_POWER_VDDMEMCTRL_RSRVD2
#define BF_POWER_VDDMEMCTRL_RSRVD2_V(e)             BF_POWER_VDDMEMCTRL_RSRVD2(BV_POWER_VDDMEMCTRL_RSRVD2__##e)
#define BFM_POWER_VDDMEMCTRL_RSRVD2_V(v)            BM_POWER_VDDMEMCTRL_RSRVD2
#define BP_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE         10
#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE         0x400
#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)      (((v) & 0x1) << 10)
#define BFM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)     BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE
#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE_V(e)    BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(BV_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE__##e)
#define BFM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE_V(v)   BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE
#define BP_POWER_VDDMEMCTRL_ENABLE_ILIMIT           9
#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT           0x200
#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)        (((v) & 0x1) << 9)
#define BFM_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)       BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT
#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT_V(e)      BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(BV_POWER_VDDMEMCTRL_ENABLE_ILIMIT__##e)
#define BFM_POWER_VDDMEMCTRL_ENABLE_ILIMIT_V(v)     BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT
#define BP_POWER_VDDMEMCTRL_ENABLE_LINREG           8
#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG           0x100
#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG(v)        (((v) & 0x1) << 8)
#define BFM_POWER_VDDMEMCTRL_ENABLE_LINREG(v)       BM_POWER_VDDMEMCTRL_ENABLE_LINREG
#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG_V(e)      BF_POWER_VDDMEMCTRL_ENABLE_LINREG(BV_POWER_VDDMEMCTRL_ENABLE_LINREG__##e)
#define BFM_POWER_VDDMEMCTRL_ENABLE_LINREG_V(v)     BM_POWER_VDDMEMCTRL_ENABLE_LINREG
#define BP_POWER_VDDMEMCTRL_RSRVD1                  5
#define BM_POWER_VDDMEMCTRL_RSRVD1                  0xe0
#define BF_POWER_VDDMEMCTRL_RSRVD1(v)               (((v) & 0x7) << 5)
#define BFM_POWER_VDDMEMCTRL_RSRVD1(v)              BM_POWER_VDDMEMCTRL_RSRVD1
#define BF_POWER_VDDMEMCTRL_RSRVD1_V(e)             BF_POWER_VDDMEMCTRL_RSRVD1(BV_POWER_VDDMEMCTRL_RSRVD1__##e)
#define BFM_POWER_VDDMEMCTRL_RSRVD1_V(v)            BM_POWER_VDDMEMCTRL_RSRVD1
#define BP_POWER_VDDMEMCTRL_TRG                     0
#define BM_POWER_VDDMEMCTRL_TRG                     0x1f
#define BF_POWER_VDDMEMCTRL_TRG(v)                  (((v) & 0x1f) << 0)
#define BFM_POWER_VDDMEMCTRL_TRG(v)                 BM_POWER_VDDMEMCTRL_TRG
#define BF_POWER_VDDMEMCTRL_TRG_V(e)                BF_POWER_VDDMEMCTRL_TRG(BV_POWER_VDDMEMCTRL_TRG__##e)
#define BFM_POWER_VDDMEMCTRL_TRG_V(v)               BM_POWER_VDDMEMCTRL_TRG

#define HW_POWER_DCDC4P2                        HW(POWER_DCDC4P2)
#define HWA_POWER_DCDC4P2                       (0x80044000 + 0x80)
#define HWT_POWER_DCDC4P2                       HWIO_32_RW
#define HWN_POWER_DCDC4P2                       POWER_DCDC4P2
#define HWI_POWER_DCDC4P2                       
#define BP_POWER_DCDC4P2_DROPOUT_CTRL           28
#define BM_POWER_DCDC4P2_DROPOUT_CTRL           0xf0000000
#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v)        (((v) & 0xf) << 28)
#define BFM_POWER_DCDC4P2_DROPOUT_CTRL(v)       BM_POWER_DCDC4P2_DROPOUT_CTRL
#define BF_POWER_DCDC4P2_DROPOUT_CTRL_V(e)      BF_POWER_DCDC4P2_DROPOUT_CTRL(BV_POWER_DCDC4P2_DROPOUT_CTRL__##e)
#define BFM_POWER_DCDC4P2_DROPOUT_CTRL_V(v)     BM_POWER_DCDC4P2_DROPOUT_CTRL
#define BP_POWER_DCDC4P2_RSRVD5                 26
#define BM_POWER_DCDC4P2_RSRVD5                 0xc000000
#define BF_POWER_DCDC4P2_RSRVD5(v)              (((v) & 0x3) << 26)
#define BFM_POWER_DCDC4P2_RSRVD5(v)             BM_POWER_DCDC4P2_RSRVD5
#define BF_POWER_DCDC4P2_RSRVD5_V(e)            BF_POWER_DCDC4P2_RSRVD5(BV_POWER_DCDC4P2_RSRVD5__##e)
#define BFM_POWER_DCDC4P2_RSRVD5_V(v)           BM_POWER_DCDC4P2_RSRVD5
#define BP_POWER_DCDC4P2_ISTEAL_THRESH          24
#define BM_POWER_DCDC4P2_ISTEAL_THRESH          0x3000000
#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v)       (((v) & 0x3) << 24)
#define BFM_POWER_DCDC4P2_ISTEAL_THRESH(v)      BM_POWER_DCDC4P2_ISTEAL_THRESH
#define BF_POWER_DCDC4P2_ISTEAL_THRESH_V(e)     BF_POWER_DCDC4P2_ISTEAL_THRESH(BV_POWER_DCDC4P2_ISTEAL_THRESH__##e)
#define BFM_POWER_DCDC4P2_ISTEAL_THRESH_V(v)    BM_POWER_DCDC4P2_ISTEAL_THRESH
#define BP_POWER_DCDC4P2_ENABLE_4P2             23
#define BM_POWER_DCDC4P2_ENABLE_4P2             0x800000
#define BF_POWER_DCDC4P2_ENABLE_4P2(v)          (((v) & 0x1) << 23)
#define BFM_POWER_DCDC4P2_ENABLE_4P2(v)         BM_POWER_DCDC4P2_ENABLE_4P2
#define BF_POWER_DCDC4P2_ENABLE_4P2_V(e)        BF_POWER_DCDC4P2_ENABLE_4P2(BV_POWER_DCDC4P2_ENABLE_4P2__##e)
#define BFM_POWER_DCDC4P2_ENABLE_4P2_V(v)       BM_POWER_DCDC4P2_ENABLE_4P2
#define BP_POWER_DCDC4P2_ENABLE_DCDC            22
#define BM_POWER_DCDC4P2_ENABLE_DCDC            0x400000
#define BF_POWER_DCDC4P2_ENABLE_DCDC(v)         (((v) & 0x1) << 22)
#define BFM_POWER_DCDC4P2_ENABLE_DCDC(v)        BM_POWER_DCDC4P2_ENABLE_DCDC
#define BF_POWER_DCDC4P2_ENABLE_DCDC_V(e)       BF_POWER_DCDC4P2_ENABLE_DCDC(BV_POWER_DCDC4P2_ENABLE_DCDC__##e)
#define BFM_POWER_DCDC4P2_ENABLE_DCDC_V(v)      BM_POWER_DCDC4P2_ENABLE_DCDC
#define BP_POWER_DCDC4P2_HYST_DIR               21
#define BM_POWER_DCDC4P2_HYST_DIR               0x200000
#define BF_POWER_DCDC4P2_HYST_DIR(v)            (((v) & 0x1) << 21)
#define BFM_POWER_DCDC4P2_HYST_DIR(v)           BM_POWER_DCDC4P2_HYST_DIR
#define BF_POWER_DCDC4P2_HYST_DIR_V(e)          BF_POWER_DCDC4P2_HYST_DIR(BV_POWER_DCDC4P2_HYST_DIR__##e)
#define BFM_POWER_DCDC4P2_HYST_DIR_V(v)         BM_POWER_DCDC4P2_HYST_DIR
#define BP_POWER_DCDC4P2_HYST_THRESH            20
#define BM_POWER_DCDC4P2_HYST_THRESH            0x100000
#define BF_POWER_DCDC4P2_HYST_THRESH(v)         (((v) & 0x1) << 20)
#define BFM_POWER_DCDC4P2_HYST_THRESH(v)        BM_POWER_DCDC4P2_HYST_THRESH
#define BF_POWER_DCDC4P2_HYST_THRESH_V(e)       BF_POWER_DCDC4P2_HYST_THRESH(BV_POWER_DCDC4P2_HYST_THRESH__##e)
#define BFM_POWER_DCDC4P2_HYST_THRESH_V(v)      BM_POWER_DCDC4P2_HYST_THRESH
#define BP_POWER_DCDC4P2_RSRVD3                 19
#define BM_POWER_DCDC4P2_RSRVD3                 0x80000
#define BF_POWER_DCDC4P2_RSRVD3(v)              (((v) & 0x1) << 19)
#define BFM_POWER_DCDC4P2_RSRVD3(v)             BM_POWER_DCDC4P2_RSRVD3
#define BF_POWER_DCDC4P2_RSRVD3_V(e)            BF_POWER_DCDC4P2_RSRVD3(BV_POWER_DCDC4P2_RSRVD3__##e)
#define BFM_POWER_DCDC4P2_RSRVD3_V(v)           BM_POWER_DCDC4P2_RSRVD3
#define BP_POWER_DCDC4P2_TRG                    16
#define BM_POWER_DCDC4P2_TRG                    0x70000
#define BF_POWER_DCDC4P2_TRG(v)                 (((v) & 0x7) << 16)
#define BFM_POWER_DCDC4P2_TRG(v)                BM_POWER_DCDC4P2_TRG
#define BF_POWER_DCDC4P2_TRG_V(e)               BF_POWER_DCDC4P2_TRG(BV_POWER_DCDC4P2_TRG__##e)
#define BFM_POWER_DCDC4P2_TRG_V(v)              BM_POWER_DCDC4P2_TRG
#define BP_POWER_DCDC4P2_RSRVD2                 13
#define BM_POWER_DCDC4P2_RSRVD2                 0xe000
#define BF_POWER_DCDC4P2_RSRVD2(v)              (((v) & 0x7) << 13)
#define BFM_POWER_DCDC4P2_RSRVD2(v)             BM_POWER_DCDC4P2_RSRVD2
#define BF_POWER_DCDC4P2_RSRVD2_V(e)            BF_POWER_DCDC4P2_RSRVD2(BV_POWER_DCDC4P2_RSRVD2__##e)
#define BFM_POWER_DCDC4P2_RSRVD2_V(v)           BM_POWER_DCDC4P2_RSRVD2
#define BP_POWER_DCDC4P2_BO                     8
#define BM_POWER_DCDC4P2_BO                     0x1f00
#define BF_POWER_DCDC4P2_BO(v)                  (((v) & 0x1f) << 8)
#define BFM_POWER_DCDC4P2_BO(v)                 BM_POWER_DCDC4P2_BO
#define BF_POWER_DCDC4P2_BO_V(e)                BF_POWER_DCDC4P2_BO(BV_POWER_DCDC4P2_BO__##e)
#define BFM_POWER_DCDC4P2_BO_V(v)               BM_POWER_DCDC4P2_BO
#define BP_POWER_DCDC4P2_RSRVD1                 5
#define BM_POWER_DCDC4P2_RSRVD1                 0xe0
#define BF_POWER_DCDC4P2_RSRVD1(v)              (((v) & 0x7) << 5)
#define BFM_POWER_DCDC4P2_RSRVD1(v)             BM_POWER_DCDC4P2_RSRVD1
#define BF_POWER_DCDC4P2_RSRVD1_V(e)            BF_POWER_DCDC4P2_RSRVD1(BV_POWER_DCDC4P2_RSRVD1__##e)
#define BFM_POWER_DCDC4P2_RSRVD1_V(v)           BM_POWER_DCDC4P2_RSRVD1
#define BP_POWER_DCDC4P2_CMPTRIP                0
#define BM_POWER_DCDC4P2_CMPTRIP                0x1f
#define BF_POWER_DCDC4P2_CMPTRIP(v)             (((v) & 0x1f) << 0)
#define BFM_POWER_DCDC4P2_CMPTRIP(v)            BM_POWER_DCDC4P2_CMPTRIP
#define BF_POWER_DCDC4P2_CMPTRIP_V(e)           BF_POWER_DCDC4P2_CMPTRIP(BV_POWER_DCDC4P2_CMPTRIP__##e)
#define BFM_POWER_DCDC4P2_CMPTRIP_V(v)          BM_POWER_DCDC4P2_CMPTRIP

#define HW_POWER_MISC                       HW(POWER_MISC)
#define HWA_POWER_MISC                      (0x80044000 + 0x90)
#define HWT_POWER_MISC                      HWIO_32_RW
#define HWN_POWER_MISC                      POWER_MISC
#define HWI_POWER_MISC                      
#define BP_POWER_MISC_RSRVD2                7
#define BM_POWER_MISC_RSRVD2                0xffffff80
#define BF_POWER_MISC_RSRVD2(v)             (((v) & 0x1ffffff) << 7)
#define BFM_POWER_MISC_RSRVD2(v)            BM_POWER_MISC_RSRVD2
#define BF_POWER_MISC_RSRVD2_V(e)           BF_POWER_MISC_RSRVD2(BV_POWER_MISC_RSRVD2__##e)
#define BFM_POWER_MISC_RSRVD2_V(v)          BM_POWER_MISC_RSRVD2
#define BP_POWER_MISC_FREQSEL               4
#define BM_POWER_MISC_FREQSEL               0x70
#define BF_POWER_MISC_FREQSEL(v)            (((v) & 0x7) << 4)
#define BFM_POWER_MISC_FREQSEL(v)           BM_POWER_MISC_FREQSEL
#define BF_POWER_MISC_FREQSEL_V(e)          BF_POWER_MISC_FREQSEL(BV_POWER_MISC_FREQSEL__##e)
#define BFM_POWER_MISC_FREQSEL_V(v)         BM_POWER_MISC_FREQSEL
#define BP_POWER_MISC_RSRVD1                3
#define BM_POWER_MISC_RSRVD1                0x8
#define BF_POWER_MISC_RSRVD1(v)             (((v) & 0x1) << 3)
#define BFM_POWER_MISC_RSRVD1(v)            BM_POWER_MISC_RSRVD1
#define BF_POWER_MISC_RSRVD1_V(e)           BF_POWER_MISC_RSRVD1(BV_POWER_MISC_RSRVD1__##e)
#define BFM_POWER_MISC_RSRVD1_V(v)          BM_POWER_MISC_RSRVD1
#define BP_POWER_MISC_DELAY_TIMING          2
#define BM_POWER_MISC_DELAY_TIMING          0x4
#define BF_POWER_MISC_DELAY_TIMING(v)       (((v) & 0x1) << 2)
#define BFM_POWER_MISC_DELAY_TIMING(v)      BM_POWER_MISC_DELAY_TIMING
#define BF_POWER_MISC_DELAY_TIMING_V(e)     BF_POWER_MISC_DELAY_TIMING(BV_POWER_MISC_DELAY_TIMING__##e)
#define BFM_POWER_MISC_DELAY_TIMING_V(v)    BM_POWER_MISC_DELAY_TIMING
#define BP_POWER_MISC_TEST                  1
#define BM_POWER_MISC_TEST                  0x2
#define BF_POWER_MISC_TEST(v)               (((v) & 0x1) << 1)
#define BFM_POWER_MISC_TEST(v)              BM_POWER_MISC_TEST
#define BF_POWER_MISC_TEST_V(e)             BF_POWER_MISC_TEST(BV_POWER_MISC_TEST__##e)
#define BFM_POWER_MISC_TEST_V(v)            BM_POWER_MISC_TEST
#define BP_POWER_MISC_SEL_PLLCLK            0
#define BM_POWER_MISC_SEL_PLLCLK            0x1
#define BF_POWER_MISC_SEL_PLLCLK(v)         (((v) & 0x1) << 0)
#define BFM_POWER_MISC_SEL_PLLCLK(v)        BM_POWER_MISC_SEL_PLLCLK
#define BF_POWER_MISC_SEL_PLLCLK_V(e)       BF_POWER_MISC_SEL_PLLCLK(BV_POWER_MISC_SEL_PLLCLK__##e)
#define BFM_POWER_MISC_SEL_PLLCLK_V(v)      BM_POWER_MISC_SEL_PLLCLK

#define HW_POWER_DCLIMITS                       HW(POWER_DCLIMITS)
#define HWA_POWER_DCLIMITS                      (0x80044000 + 0xa0)
#define HWT_POWER_DCLIMITS                      HWIO_32_RW
#define HWN_POWER_DCLIMITS                      POWER_DCLIMITS
#define HWI_POWER_DCLIMITS                      
#define BP_POWER_DCLIMITS_RSRVD3                16
#define BM_POWER_DCLIMITS_RSRVD3                0xffff0000
#define BF_POWER_DCLIMITS_RSRVD3(v)             (((v) & 0xffff) << 16)
#define BFM_POWER_DCLIMITS_RSRVD3(v)            BM_POWER_DCLIMITS_RSRVD3
#define BF_POWER_DCLIMITS_RSRVD3_V(e)           BF_POWER_DCLIMITS_RSRVD3(BV_POWER_DCLIMITS_RSRVD3__##e)
#define BFM_POWER_DCLIMITS_RSRVD3_V(v)          BM_POWER_DCLIMITS_RSRVD3
#define BP_POWER_DCLIMITS_RSRVD2                15
#define BM_POWER_DCLIMITS_RSRVD2                0x8000
#define BF_POWER_DCLIMITS_RSRVD2(v)             (((v) & 0x1) << 15)
#define BFM_POWER_DCLIMITS_RSRVD2(v)            BM_POWER_DCLIMITS_RSRVD2
#define BF_POWER_DCLIMITS_RSRVD2_V(e)           BF_POWER_DCLIMITS_RSRVD2(BV_POWER_DCLIMITS_RSRVD2__##e)
#define BFM_POWER_DCLIMITS_RSRVD2_V(v)          BM_POWER_DCLIMITS_RSRVD2
#define BP_POWER_DCLIMITS_POSLIMIT_BUCK         8
#define BM_POWER_DCLIMITS_POSLIMIT_BUCK         0x7f00
#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)      (((v) & 0x7f) << 8)
#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK(v)     BM_POWER_DCLIMITS_POSLIMIT_BUCK
#define BF_POWER_DCLIMITS_POSLIMIT_BUCK_V(e)    BF_POWER_DCLIMITS_POSLIMIT_BUCK(BV_POWER_DCLIMITS_POSLIMIT_BUCK__##e)
#define BFM_POWER_DCLIMITS_POSLIMIT_BUCK_V(v)   BM_POWER_DCLIMITS_POSLIMIT_BUCK
#define BP_POWER_DCLIMITS_RSRVD1                7
#define BM_POWER_DCLIMITS_RSRVD1                0x80
#define BF_POWER_DCLIMITS_RSRVD1(v)             (((v) & 0x1) << 7)
#define BFM_POWER_DCLIMITS_RSRVD1(v)            BM_POWER_DCLIMITS_RSRVD1
#define BF_POWER_DCLIMITS_RSRVD1_V(e)           BF_POWER_DCLIMITS_RSRVD1(BV_POWER_DCLIMITS_RSRVD1__##e)
#define BFM_POWER_DCLIMITS_RSRVD1_V(v)          BM_POWER_DCLIMITS_RSRVD1
#define BP_POWER_DCLIMITS_NEGLIMIT              0
#define BM_POWER_DCLIMITS_NEGLIMIT              0x7f
#define BF_POWER_DCLIMITS_NEGLIMIT(v)           (((v) & 0x7f) << 0)
#define BFM_POWER_DCLIMITS_NEGLIMIT(v)          BM_POWER_DCLIMITS_NEGLIMIT
#define BF_POWER_DCLIMITS_NEGLIMIT_V(e)         BF_POWER_DCLIMITS_NEGLIMIT(BV_POWER_DCLIMITS_NEGLIMIT__##e)
#define BFM_POWER_DCLIMITS_NEGLIMIT_V(v)        BM_POWER_DCLIMITS_NEGLIMIT

#define HW_POWER_LOOPCTRL                       HW(POWER_LOOPCTRL)
#define HWA_POWER_LOOPCTRL                      (0x80044000 + 0xb0)
#define HWT_POWER_LOOPCTRL                      HWIO_32_RW
#define HWN_POWER_LOOPCTRL                      POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL                      
#define HW_POWER_LOOPCTRL_SET                   HW(POWER_LOOPCTRL_SET)
#define HWA_POWER_LOOPCTRL_SET                  (HWA_POWER_LOOPCTRL + 0x4)
#define HWT_POWER_LOOPCTRL_SET                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_SET                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_SET                  
#define HW_POWER_LOOPCTRL_CLR                   HW(POWER_LOOPCTRL_CLR)
#define HWA_POWER_LOOPCTRL_CLR                  (HWA_POWER_LOOPCTRL + 0x8)
#define HWT_POWER_LOOPCTRL_CLR                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_CLR                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_CLR                  
#define HW_POWER_LOOPCTRL_TOG                   HW(POWER_LOOPCTRL_TOG)
#define HWA_POWER_LOOPCTRL_TOG                  (HWA_POWER_LOOPCTRL + 0xc)
#define HWT_POWER_LOOPCTRL_TOG                  HWIO_32_WO
#define HWN_POWER_LOOPCTRL_TOG                  POWER_LOOPCTRL
#define HWI_POWER_LOOPCTRL_TOG                  
#define BP_POWER_LOOPCTRL_RSRVD3                21
#define BM_POWER_LOOPCTRL_RSRVD3                0xffe00000
#define BF_POWER_LOOPCTRL_RSRVD3(v)             (((v) & 0x7ff) << 21)
#define BFM_POWER_LOOPCTRL_RSRVD3(v)            BM_POWER_LOOPCTRL_RSRVD3
#define BF_POWER_LOOPCTRL_RSRVD3_V(e)           BF_POWER_LOOPCTRL_RSRVD3(BV_POWER_LOOPCTRL_RSRVD3__##e)
#define BFM_POWER_LOOPCTRL_RSRVD3_V(v)          BM_POWER_LOOPCTRL_RSRVD3
#define BP_POWER_LOOPCTRL_TOGGLE_DIF            20
#define BM_POWER_LOOPCTRL_TOGGLE_DIF            0x100000
#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)         (((v) & 0x1) << 20)
#define BFM_POWER_LOOPCTRL_TOGGLE_DIF(v)        BM_POWER_LOOPCTRL_TOGGLE_DIF
#define BF_POWER_LOOPCTRL_TOGGLE_DIF_V(e)       BF_POWER_LOOPCTRL_TOGGLE_DIF(BV_POWER_LOOPCTRL_TOGGLE_DIF__##e)
#define BFM_POWER_LOOPCTRL_TOGGLE_DIF_V(v)      BM_POWER_LOOPCTRL_TOGGLE_DIF
#define BP_POWER_LOOPCTRL_HYST_SIGN             19
#define BM_POWER_LOOPCTRL_HYST_SIGN             0x80000
#define BF_POWER_LOOPCTRL_HYST_SIGN(v)          (((v) & 0x1) << 19)
#define BFM_POWER_LOOPCTRL_HYST_SIGN(v)         BM_POWER_LOOPCTRL_HYST_SIGN
#define BF_POWER_LOOPCTRL_HYST_SIGN_V(e)        BF_POWER_LOOPCTRL_HYST_SIGN(BV_POWER_LOOPCTRL_HYST_SIGN__##e)
#define BFM_POWER_LOOPCTRL_HYST_SIGN_V(v)       BM_POWER_LOOPCTRL_HYST_SIGN
#define BP_POWER_LOOPCTRL_EN_CM_HYST            18
#define BM_POWER_LOOPCTRL_EN_CM_HYST            0x40000
#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)         (((v) & 0x1) << 18)
#define BFM_POWER_LOOPCTRL_EN_CM_HYST(v)        BM_POWER_LOOPCTRL_EN_CM_HYST
#define BF_POWER_LOOPCTRL_EN_CM_HYST_V(e)       BF_POWER_LOOPCTRL_EN_CM_HYST(BV_POWER_LOOPCTRL_EN_CM_HYST__##e)
#define BFM_POWER_LOOPCTRL_EN_CM_HYST_V(v)      BM_POWER_LOOPCTRL_EN_CM_HYST
#define BP_POWER_LOOPCTRL_EN_DF_HYST            17
#define BM_POWER_LOOPCTRL_EN_DF_HYST            0x20000
#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)         (((v) & 0x1) << 17)
#define BFM_POWER_LOOPCTRL_EN_DF_HYST(v)        BM_POWER_LOOPCTRL_EN_DF_HYST
#define BF_POWER_LOOPCTRL_EN_DF_HYST_V(e)       BF_POWER_LOOPCTRL_EN_DF_HYST(BV_POWER_LOOPCTRL_EN_DF_HYST__##e)
#define BFM_POWER_LOOPCTRL_EN_DF_HYST_V(v)      BM_POWER_LOOPCTRL_EN_DF_HYST
#define BP_POWER_LOOPCTRL_CM_HYST_THRESH        16
#define BM_POWER_LOOPCTRL_CM_HYST_THRESH        0x10000
#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v)     (((v) & 0x1) << 16)
#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH(v)    BM_POWER_LOOPCTRL_CM_HYST_THRESH
#define BF_POWER_LOOPCTRL_CM_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_CM_HYST_THRESH(BV_POWER_LOOPCTRL_CM_HYST_THRESH__##e)
#define BFM_POWER_LOOPCTRL_CM_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_CM_HYST_THRESH
#define BP_POWER_LOOPCTRL_DF_HYST_THRESH        15
#define BM_POWER_LOOPCTRL_DF_HYST_THRESH        0x8000
#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v)     (((v) & 0x1) << 15)
#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH(v)    BM_POWER_LOOPCTRL_DF_HYST_THRESH
#define BF_POWER_LOOPCTRL_DF_HYST_THRESH_V(e)   BF_POWER_LOOPCTRL_DF_HYST_THRESH(BV_POWER_LOOPCTRL_DF_HYST_THRESH__##e)
#define BFM_POWER_LOOPCTRL_DF_HYST_THRESH_V(v)  BM_POWER_LOOPCTRL_DF_HYST_THRESH
#define BP_POWER_LOOPCTRL_RCSCALE_THRESH        14
#define BM_POWER_LOOPCTRL_RCSCALE_THRESH        0x4000
#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v)     (((v) & 0x1) << 14)
#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH(v)    BM_POWER_LOOPCTRL_RCSCALE_THRESH
#define BF_POWER_LOOPCTRL_RCSCALE_THRESH_V(e)   BF_POWER_LOOPCTRL_RCSCALE_THRESH(BV_POWER_LOOPCTRL_RCSCALE_THRESH__##e)
#define BFM_POWER_LOOPCTRL_RCSCALE_THRESH_V(v)  BM_POWER_LOOPCTRL_RCSCALE_THRESH
#define BP_POWER_LOOPCTRL_EN_RCSCALE            12
#define BM_POWER_LOOPCTRL_EN_RCSCALE            0x3000
#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)         (((v) & 0x3) << 12)
#define BFM_POWER_LOOPCTRL_EN_RCSCALE(v)        BM_POWER_LOOPCTRL_EN_RCSCALE
#define BF_POWER_LOOPCTRL_EN_RCSCALE_V(e)       BF_POWER_LOOPCTRL_EN_RCSCALE(BV_POWER_LOOPCTRL_EN_RCSCALE__##e)
#define BFM_POWER_LOOPCTRL_EN_RCSCALE_V(v)      BM_POWER_LOOPCTRL_EN_RCSCALE
#define BP_POWER_LOOPCTRL_RSRVD2                11
#define BM_POWER_LOOPCTRL_RSRVD2                0x800
#define BF_POWER_LOOPCTRL_RSRVD2(v)             (((v) & 0x1) << 11)
#define BFM_POWER_LOOPCTRL_RSRVD2(v)            BM_POWER_LOOPCTRL_RSRVD2
#define BF_POWER_LOOPCTRL_RSRVD2_V(e)           BF_POWER_LOOPCTRL_RSRVD2(BV_POWER_LOOPCTRL_RSRVD2__##e)
#define BFM_POWER_LOOPCTRL_RSRVD2_V(v)          BM_POWER_LOOPCTRL_RSRVD2
#define BP_POWER_LOOPCTRL_DC_FF                 8
#define BM_POWER_LOOPCTRL_DC_FF                 0x700
#define BF_POWER_LOOPCTRL_DC_FF(v)              (((v) & 0x7) << 8)
#define BFM_POWER_LOOPCTRL_DC_FF(v)             BM_POWER_LOOPCTRL_DC_FF
#define BF_POWER_LOOPCTRL_DC_FF_V(e)            BF_POWER_LOOPCTRL_DC_FF(BV_POWER_LOOPCTRL_DC_FF__##e)
#define BFM_POWER_LOOPCTRL_DC_FF_V(v)           BM_POWER_LOOPCTRL_DC_FF
#define BP_POWER_LOOPCTRL_DC_R                  4
#define BM_POWER_LOOPCTRL_DC_R                  0xf0
#define BF_POWER_LOOPCTRL_DC_R(v)               (((v) & 0xf) << 4)
#define BFM_POWER_LOOPCTRL_DC_R(v)              BM_POWER_LOOPCTRL_DC_R
#define BF_POWER_LOOPCTRL_DC_R_V(e)             BF_POWER_LOOPCTRL_DC_R(BV_POWER_LOOPCTRL_DC_R__##e)
#define BFM_POWER_LOOPCTRL_DC_R_V(v)            BM_POWER_LOOPCTRL_DC_R
#define BP_POWER_LOOPCTRL_RSRVD1                2
#define BM_POWER_LOOPCTRL_RSRVD1                0xc
#define BF_POWER_LOOPCTRL_RSRVD1(v)             (((v) & 0x3) << 2)
#define BFM_POWER_LOOPCTRL_RSRVD1(v)            BM_POWER_LOOPCTRL_RSRVD1
#define BF_POWER_LOOPCTRL_RSRVD1_V(e)           BF_POWER_LOOPCTRL_RSRVD1(BV_POWER_LOOPCTRL_RSRVD1__##e)
#define BFM_POWER_LOOPCTRL_RSRVD1_V(v)          BM_POWER_LOOPCTRL_RSRVD1
#define BP_POWER_LOOPCTRL_DC_C                  0
#define BM_POWER_LOOPCTRL_DC_C                  0x3
#define BF_POWER_LOOPCTRL_DC_C(v)               (((v) & 0x3) << 0)
#define BFM_POWER_LOOPCTRL_DC_C(v)              BM_POWER_LOOPCTRL_DC_C
#define BF_POWER_LOOPCTRL_DC_C_V(e)             BF_POWER_LOOPCTRL_DC_C(BV_POWER_LOOPCTRL_DC_C__##e)
#define BFM_POWER_LOOPCTRL_DC_C_V(v)            BM_POWER_LOOPCTRL_DC_C

#define HW_POWER_STS                        HW(POWER_STS)
#define HWA_POWER_STS                       (0x80044000 + 0xc0)
#define HWT_POWER_STS                       HWIO_32_RW
#define HWN_POWER_STS                       POWER_STS
#define HWI_POWER_STS                       
#define BP_POWER_STS_RSRVD3                 30
#define BM_POWER_STS_RSRVD3                 0xc0000000
#define BF_POWER_STS_RSRVD3(v)              (((v) & 0x3) << 30)
#define BFM_POWER_STS_RSRVD3(v)             BM_POWER_STS_RSRVD3
#define BF_POWER_STS_RSRVD3_V(e)            BF_POWER_STS_RSRVD3(BV_POWER_STS_RSRVD3__##e)
#define BFM_POWER_STS_RSRVD3_V(v)           BM_POWER_STS_RSRVD3
#define BP_POWER_STS_PWRUP_SOURCE           24
#define BM_POWER_STS_PWRUP_SOURCE           0x3f000000
#define BF_POWER_STS_PWRUP_SOURCE(v)        (((v) & 0x3f) << 24)
#define BFM_POWER_STS_PWRUP_SOURCE(v)       BM_POWER_STS_PWRUP_SOURCE
#define BF_POWER_STS_PWRUP_SOURCE_V(e)      BF_POWER_STS_PWRUP_SOURCE(BV_POWER_STS_PWRUP_SOURCE__##e)
#define BFM_POWER_STS_PWRUP_SOURCE_V(v)     BM_POWER_STS_PWRUP_SOURCE
#define BP_POWER_STS_RSRVD2                 22
#define BM_POWER_STS_RSRVD2                 0xc00000
#define BF_POWER_STS_RSRVD2(v)              (((v) & 0x3) << 22)
#define BFM_POWER_STS_RSRVD2(v)             BM_POWER_STS_RSRVD2
#define BF_POWER_STS_RSRVD2_V(e)            BF_POWER_STS_RSRVD2(BV_POWER_STS_RSRVD2__##e)
#define BFM_POWER_STS_RSRVD2_V(v)           BM_POWER_STS_RSRVD2
#define BP_POWER_STS_PSWITCH                20
#define BM_POWER_STS_PSWITCH                0x300000
#define BF_POWER_STS_PSWITCH(v)             (((v) & 0x3) << 20)
#define BFM_POWER_STS_PSWITCH(v)            BM_POWER_STS_PSWITCH
#define BF_POWER_STS_PSWITCH_V(e)           BF_POWER_STS_PSWITCH(BV_POWER_STS_PSWITCH__##e)
#define BFM_POWER_STS_PSWITCH_V(v)          BM_POWER_STS_PSWITCH
#define BP_POWER_STS_RSRVD1                 18
#define BM_POWER_STS_RSRVD1                 0xc0000
#define BF_POWER_STS_RSRVD1(v)              (((v) & 0x3) << 18)
#define BFM_POWER_STS_RSRVD1(v)             BM_POWER_STS_RSRVD1
#define BF_POWER_STS_RSRVD1_V(e)            BF_POWER_STS_RSRVD1(BV_POWER_STS_RSRVD1__##e)
#define BFM_POWER_STS_RSRVD1_V(v)           BM_POWER_STS_RSRVD1
#define BP_POWER_STS_AVALID_STATUS          17
#define BM_POWER_STS_AVALID_STATUS          0x20000
#define BF_POWER_STS_AVALID_STATUS(v)       (((v) & 0x1) << 17)
#define BFM_POWER_STS_AVALID_STATUS(v)      BM_POWER_STS_AVALID_STATUS
#define BF_POWER_STS_AVALID_STATUS_V(e)     BF_POWER_STS_AVALID_STATUS(BV_POWER_STS_AVALID_STATUS__##e)
#define BFM_POWER_STS_AVALID_STATUS_V(v)    BM_POWER_STS_AVALID_STATUS
#define BP_POWER_STS_BVALID_STATUS          16
#define BM_POWER_STS_BVALID_STATUS          0x10000
#define BF_POWER_STS_BVALID_STATUS(v)       (((v) & 0x1) << 16)
#define BFM_POWER_STS_BVALID_STATUS(v)      BM_POWER_STS_BVALID_STATUS
#define BF_POWER_STS_BVALID_STATUS_V(e)     BF_POWER_STS_BVALID_STATUS(BV_POWER_STS_BVALID_STATUS__##e)
#define BFM_POWER_STS_BVALID_STATUS_V(v)    BM_POWER_STS_BVALID_STATUS
#define BP_POWER_STS_VBUSVALID_STATUS       15
#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) & 0x1) << 15)
#define BFM_POWER_STS_VBUSVALID_STATUS(v)   BM_POWER_STS_VBUSVALID_STATUS
#define BF_POWER_STS_VBUSVALID_STATUS_V(e)  BF_POWER_STS_VBUSVALID_STATUS(BV_POWER_STS_VBUSVALID_STATUS__##e)
#define BFM_POWER_STS_VBUSVALID_STATUS_V(v) BM_POWER_STS_VBUSVALID_STATUS
#define BP_POWER_STS_SESSEND_STATUS         14
#define BM_POWER_STS_SESSEND_STATUS         0x4000
#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) & 0x1) << 14)
#define BFM_POWER_STS_SESSEND_STATUS(v)     BM_POWER_STS_SESSEND_STATUS
#define BF_POWER_STS_SESSEND_STATUS_V(e)    BF_POWER_STS_SESSEND_STATUS(BV_POWER_STS_SESSEND_STATUS__##e)
#define BFM_POWER_STS_SESSEND_STATUS_V(v)   BM_POWER_STS_SESSEND_STATUS
#define BP_POWER_STS_BATT_BO                13
#define BM_POWER_STS_BATT_BO                0x2000
#define BF_POWER_STS_BATT_BO(v)             (((v) & 0x1) << 13)
#define BFM_POWER_STS_BATT_BO(v)            BM_POWER_STS_BATT_BO
#define BF_POWER_STS_BATT_BO_V(e)           BF_POWER_STS_BATT_BO(BV_POWER_STS_BATT_BO__##e)
#define BFM_POWER_STS_BATT_BO_V(v)          BM_POWER_STS_BATT_BO
#define BP_POWER_STS_VDD5V_FAULT            12
#define BM_POWER_STS_VDD5V_FAULT            0x1000
#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) & 0x1) << 12)
#define BFM_POWER_STS_VDD5V_FAULT(v)        BM_POWER_STS_VDD5V_FAULT
#define BF_POWER_STS_VDD5V_FAULT_V(e)       BF_POWER_STS_VDD5V_FAULT(BV_POWER_STS_VDD5V_FAULT__##e)
#define BFM_POWER_STS_VDD5V_FAULT_V(v)      BM_POWER_STS_VDD5V_FAULT
#define BP_POWER_STS_CHRGSTS                11
#define BM_POWER_STS_CHRGSTS                0x800
#define BF_POWER_STS_CHRGSTS(v)             (((v) & 0x1) << 11)
#define BFM_POWER_STS_CHRGSTS(v)            BM_POWER_STS_CHRGSTS
#define BF_POWER_STS_CHRGSTS_V(e)           BF_POWER_STS_CHRGSTS(BV_POWER_STS_CHRGSTS__##e)
#define BFM_POWER_STS_CHRGSTS_V(v)          BM_POWER_STS_CHRGSTS
#define BP_POWER_STS_DCDC_4P2_BO            10
#define BM_POWER_STS_DCDC_4P2_BO            0x400
#define BF_POWER_STS_DCDC_4P2_BO(v)         (((v) & 0x1) << 10)
#define BFM_POWER_STS_DCDC_4P2_BO(v)        BM_POWER_STS_DCDC_4P2_BO
#define BF_POWER_STS_DCDC_4P2_BO_V(e)       BF_POWER_STS_DCDC_4P2_BO(BV_POWER_STS_DCDC_4P2_BO__##e)
#define BFM_POWER_STS_DCDC_4P2_BO_V(v)      BM_POWER_STS_DCDC_4P2_BO
#define BP_POWER_STS_DC_OK                  9
#define BM_POWER_STS_DC_OK                  0x200
#define BF_POWER_STS_DC_OK(v)               (((v) & 0x1) << 9)
#define BFM_POWER_STS_DC_OK(v)              BM_POWER_STS_DC_OK
#define BF_POWER_STS_DC_OK_V(e)             BF_POWER_STS_DC_OK(BV_POWER_STS_DC_OK__##e)
#define BFM_POWER_STS_DC_OK_V(v)            BM_POWER_STS_DC_OK
#define BP_POWER_STS_VDDIO_BO               8
#define BM_POWER_STS_VDDIO_BO               0x100
#define BF_POWER_STS_VDDIO_BO(v)            (((v) & 0x1) << 8)
#define BFM_POWER_STS_VDDIO_BO(v)           BM_POWER_STS_VDDIO_BO
#define BF_POWER_STS_VDDIO_BO_V(e)          BF_POWER_STS_VDDIO_BO(BV_POWER_STS_VDDIO_BO__##e)
#define BFM_POWER_STS_VDDIO_BO_V(v)         BM_POWER_STS_VDDIO_BO
#define BP_POWER_STS_VDDA_BO                7
#define BM_POWER_STS_VDDA_BO                0x80
#define BF_POWER_STS_VDDA_BO(v)             (((v) & 0x1) << 7)
#define BFM_POWER_STS_VDDA_BO(v)            BM_POWER_STS_VDDA_BO
#define BF_POWER_STS_VDDA_BO_V(e)           BF_POWER_STS_VDDA_BO(BV_POWER_STS_VDDA_BO__##e)
#define BFM_POWER_STS_VDDA_BO_V(v)          BM_POWER_STS_VDDA_BO
#define BP_POWER_STS_VDDD_BO                6
#define BM_POWER_STS_VDDD_BO                0x40
#define BF_POWER_STS_VDDD_BO(v)             (((v) & 0x1) << 6)
#define BFM_POWER_STS_VDDD_BO(v)            BM_POWER_STS_VDDD_BO
#define BF_POWER_STS_VDDD_BO_V(e)           BF_POWER_STS_VDDD_BO(BV_POWER_STS_VDDD_BO__##e)
#define BFM_POWER_STS_VDDD_BO_V(v)          BM_POWER_STS_VDDD_BO
#define BP_POWER_STS_VDD5V_GT_VDDIO         5
#define BM_POWER_STS_VDD5V_GT_VDDIO         0x20
#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) & 0x1) << 5)
#define BFM_POWER_STS_VDD5V_GT_VDDIO(v)     BM_POWER_STS_VDD5V_GT_VDDIO
#define BF_POWER_STS_VDD5V_GT_VDDIO_V(e)    BF_POWER_STS_VDD5V_GT_VDDIO(BV_POWER_STS_VDD5V_GT_VDDIO__##e)
#define BFM_POWER_STS_VDD5V_GT_VDDIO_V(v)   BM_POWER_STS_VDD5V_GT_VDDIO
#define BP_POWER_STS_VDD5V_DROOP            4
#define BM_POWER_STS_VDD5V_DROOP            0x10
#define BF_POWER_STS_VDD5V_DROOP(v)         (((v) & 0x1) << 4)
#define BFM_POWER_STS_VDD5V_DROOP(v)        BM_POWER_STS_VDD5V_DROOP
#define BF_POWER_STS_VDD5V_DROOP_V(e)       BF_POWER_STS_VDD5V_DROOP(BV_POWER_STS_VDD5V_DROOP__##e)
#define BFM_POWER_STS_VDD5V_DROOP_V(v)      BM_POWER_STS_VDD5V_DROOP
#define BP_POWER_STS_AVALID                 3
#define BM_POWER_STS_AVALID                 0x8
#define BF_POWER_STS_AVALID(v)              (((v) & 0x1) << 3)
#define BFM_POWER_STS_AVALID(v)             BM_POWER_STS_AVALID
#define BF_POWER_STS_AVALID_V(e)            BF_POWER_STS_AVALID(BV_POWER_STS_AVALID__##e)
#define BFM_POWER_STS_AVALID_V(v)           BM_POWER_STS_AVALID
#define BP_POWER_STS_BVALID                 2
#define BM_POWER_STS_BVALID                 0x4
#define BF_POWER_STS_BVALID(v)              (((v) & 0x1) << 2)
#define BFM_POWER_STS_BVALID(v)             BM_POWER_STS_BVALID
#define BF_POWER_STS_BVALID_V(e)            BF_POWER_STS_BVALID(BV_POWER_STS_BVALID__##e)
#define BFM_POWER_STS_BVALID_V(v)           BM_POWER_STS_BVALID
#define BP_POWER_STS_VBUSVALID              1
#define BM_POWER_STS_VBUSVALID              0x2
#define BF_POWER_STS_VBUSVALID(v)           (((v) & 0x1) << 1)
#define BFM_POWER_STS_VBUSVALID(v)          BM_POWER_STS_VBUSVALID
#define BF_POWER_STS_VBUSVALID_V(e)         BF_POWER_STS_VBUSVALID(BV_POWER_STS_VBUSVALID__##e)
#define BFM_POWER_STS_VBUSVALID_V(v)        BM_POWER_STS_VBUSVALID
#define BP_POWER_STS_SESSEND                0
#define BM_POWER_STS_SESSEND                0x1
#define BF_POWER_STS_SESSEND(v)             (((v) & 0x1) << 0)
#define BFM_POWER_STS_SESSEND(v)            BM_POWER_STS_SESSEND
#define BF_POWER_STS_SESSEND_V(e)           BF_POWER_STS_SESSEND(BV_POWER_STS_SESSEND__##e)
#define BFM_POWER_STS_SESSEND_V(v)          BM_POWER_STS_SESSEND

#define HW_POWER_SPEED              HW(POWER_SPEED)
#define HWA_POWER_SPEED             (0x80044000 + 0xd0)
#define HWT_POWER_SPEED             HWIO_32_RW
#define HWN_POWER_SPEED             POWER_SPEED
#define HWI_POWER_SPEED             
#define HW_POWER_SPEED_SET          HW(POWER_SPEED_SET)
#define HWA_POWER_SPEED_SET         (HWA_POWER_SPEED + 0x4)
#define HWT_POWER_SPEED_SET         HWIO_32_WO
#define HWN_POWER_SPEED_SET         POWER_SPEED
#define HWI_POWER_SPEED_SET         
#define HW_POWER_SPEED_CLR          HW(POWER_SPEED_CLR)
#define HWA_POWER_SPEED_CLR         (HWA_POWER_SPEED + 0x8)
#define HWT_POWER_SPEED_CLR         HWIO_32_WO
#define HWN_POWER_SPEED_CLR         POWER_SPEED
#define HWI_POWER_SPEED_CLR         
#define HW_POWER_SPEED_TOG          HW(POWER_SPEED_TOG)
#define HWA_POWER_SPEED_TOG         (HWA_POWER_SPEED + 0xc)
#define HWT_POWER_SPEED_TOG         HWIO_32_WO
#define HWN_POWER_SPEED_TOG         POWER_SPEED
#define HWI_POWER_SPEED_TOG         
#define BP_POWER_SPEED_RSRVD1       24
#define BM_POWER_SPEED_RSRVD1       0xff000000
#define BF_POWER_SPEED_RSRVD1(v)    (((v) & 0xff) << 24)
#define BFM_POWER_SPEED_RSRVD1(v)   BM_POWER_SPEED_RSRVD1
#define BF_POWER_SPEED_RSRVD1_V(e)  BF_POWER_SPEED_RSRVD1(BV_POWER_SPEED_RSRVD1__##e)
#define BFM_POWER_SPEED_RSRVD1_V(v) BM_POWER_SPEED_RSRVD1
#define BP_POWER_SPEED_STATUS       16
#define BM_POWER_SPEED_STATUS       0xff0000
#define BF_POWER_SPEED_STATUS(v)    (((v) & 0xff) << 16)
#define BFM_POWER_SPEED_STATUS(v)   BM_POWER_SPEED_STATUS
#define BF_POWER_SPEED_STATUS_V(e)  BF_POWER_SPEED_STATUS(BV_POWER_SPEED_STATUS__##e)
#define BFM_POWER_SPEED_STATUS_V(v) BM_POWER_SPEED_STATUS
#define BP_POWER_SPEED_RSRVD0       2
#define BM_POWER_SPEED_RSRVD0       0xfffc
#define BF_POWER_SPEED_RSRVD0(v)    (((v) & 0x3fff) << 2)
#define BFM_POWER_SPEED_RSRVD0(v)   BM_POWER_SPEED_RSRVD0
#define BF_POWER_SPEED_RSRVD0_V(e)  BF_POWER_SPEED_RSRVD0(BV_POWER_SPEED_RSRVD0__##e)
#define BFM_POWER_SPEED_RSRVD0_V(v) BM_POWER_SPEED_RSRVD0
#define BP_POWER_SPEED_CTRL         0
#define BM_POWER_SPEED_CTRL         0x3
#define BF_POWER_SPEED_CTRL(v)      (((v) & 0x3) << 0)
#define BFM_POWER_SPEED_CTRL(v)     BM_POWER_SPEED_CTRL
#define BF_POWER_SPEED_CTRL_V(e)    BF_POWER_SPEED_CTRL(BV_POWER_SPEED_CTRL__##e)
#define BFM_POWER_SPEED_CTRL_V(v)   BM_POWER_SPEED_CTRL

#define HW_POWER_BATTMONITOR                        HW(POWER_BATTMONITOR)
#define HWA_POWER_BATTMONITOR                       (0x80044000 + 0xe0)
#define HWT_POWER_BATTMONITOR                       HWIO_32_RW
#define HWN_POWER_BATTMONITOR                       POWER_BATTMONITOR
#define HWI_POWER_BATTMONITOR                       
#define BP_POWER_BATTMONITOR_RSRVD3                 26
#define BM_POWER_BATTMONITOR_RSRVD3                 0xfc000000
#define BF_POWER_BATTMONITOR_RSRVD3(v)              (((v) & 0x3f) << 26)
#define BFM_POWER_BATTMONITOR_RSRVD3(v)             BM_POWER_BATTMONITOR_RSRVD3
#define BF_POWER_BATTMONITOR_RSRVD3_V(e)            BF_POWER_BATTMONITOR_RSRVD3(BV_POWER_BATTMONITOR_RSRVD3__##e)
#define BFM_POWER_BATTMONITOR_RSRVD3_V(v)           BM_POWER_BATTMONITOR_RSRVD3
#define BP_POWER_BATTMONITOR_BATT_VAL               16
#define BM_POWER_BATTMONITOR_BATT_VAL               0x3ff0000
#define BF_POWER_BATTMONITOR_BATT_VAL(v)            (((v) & 0x3ff) << 16)
#define BFM_POWER_BATTMONITOR_BATT_VAL(v)           BM_POWER_BATTMONITOR_BATT_VAL
#define BF_POWER_BATTMONITOR_BATT_VAL_V(e)          BF_POWER_BATTMONITOR_BATT_VAL(BV_POWER_BATTMONITOR_BATT_VAL__##e)
#define BFM_POWER_BATTMONITOR_BATT_VAL_V(v)         BM_POWER_BATTMONITOR_BATT_VAL
#define BP_POWER_BATTMONITOR_RSRVD2                 11
#define BM_POWER_BATTMONITOR_RSRVD2                 0xf800
#define BF_POWER_BATTMONITOR_RSRVD2(v)              (((v) & 0x1f) << 11)
#define BFM_POWER_BATTMONITOR_RSRVD2(v)             BM_POWER_BATTMONITOR_RSRVD2
#define BF_POWER_BATTMONITOR_RSRVD2_V(e)            BF_POWER_BATTMONITOR_RSRVD2(BV_POWER_BATTMONITOR_RSRVD2__##e)
#define BFM_POWER_BATTMONITOR_RSRVD2_V(v)           BM_POWER_BATTMONITOR_RSRVD2
#define BP_POWER_BATTMONITOR_EN_BATADJ              10
#define BM_POWER_BATTMONITOR_EN_BATADJ              0x400
#define BF_POWER_BATTMONITOR_EN_BATADJ(v)           (((v) & 0x1) << 10)
#define BFM_POWER_BATTMONITOR_EN_BATADJ(v)          BM_POWER_BATTMONITOR_EN_BATADJ
#define BF_POWER_BATTMONITOR_EN_BATADJ_V(e)         BF_POWER_BATTMONITOR_EN_BATADJ(BV_POWER_BATTMONITOR_EN_BATADJ__##e)
#define BFM_POWER_BATTMONITOR_EN_BATADJ_V(v)        BM_POWER_BATTMONITOR_EN_BATADJ
#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT        9
#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT        0x200
#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)     (((v) & 0x1) << 9)
#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v)    BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(e)   BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(BV_POWER_BATTMONITOR_PWDN_BATTBRNOUT__##e)
#define BFM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_V(v)  BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT
#define BP_POWER_BATTMONITOR_BRWNOUT_PWD            8
#define BM_POWER_BATTMONITOR_BRWNOUT_PWD            0x100
#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)         (((v) & 0x1) << 8)
#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD(v)        BM_POWER_BATTMONITOR_BRWNOUT_PWD
#define BF_POWER_BATTMONITOR_BRWNOUT_PWD_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_PWD(BV_POWER_BATTMONITOR_BRWNOUT_PWD__##e)
#define BFM_POWER_BATTMONITOR_BRWNOUT_PWD_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_PWD
#define BP_POWER_BATTMONITOR_RSRVD1                 5
#define BM_POWER_BATTMONITOR_RSRVD1                 0xe0
#define BF_POWER_BATTMONITOR_RSRVD1(v)              (((v) & 0x7) << 5)
#define BFM_POWER_BATTMONITOR_RSRVD1(v)             BM_POWER_BATTMONITOR_RSRVD1
#define BF_POWER_BATTMONITOR_RSRVD1_V(e)            BF_POWER_BATTMONITOR_RSRVD1(BV_POWER_BATTMONITOR_RSRVD1__##e)
#define BFM_POWER_BATTMONITOR_RSRVD1_V(v)           BM_POWER_BATTMONITOR_RSRVD1
#define BP_POWER_BATTMONITOR_BRWNOUT_LVL            0
#define BM_POWER_BATTMONITOR_BRWNOUT_LVL            0x1f
#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)         (((v) & 0x1f) << 0)
#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL(v)        BM_POWER_BATTMONITOR_BRWNOUT_LVL
#define BF_POWER_BATTMONITOR_BRWNOUT_LVL_V(e)       BF_POWER_BATTMONITOR_BRWNOUT_LVL(BV_POWER_BATTMONITOR_BRWNOUT_LVL__##e)
#define BFM_POWER_BATTMONITOR_BRWNOUT_LVL_V(v)      BM_POWER_BATTMONITOR_BRWNOUT_LVL

#define HW_POWER_RESET                  HW(POWER_RESET)
#define HWA_POWER_RESET                 (0x80044000 + 0x100)
#define HWT_POWER_RESET                 HWIO_32_RW
#define HWN_POWER_RESET                 POWER_RESET
#define HWI_POWER_RESET                 
#define HW_POWER_RESET_SET              HW(POWER_RESET_SET)
#define HWA_POWER_RESET_SET             (HWA_POWER_RESET + 0x4)
#define HWT_POWER_RESET_SET             HWIO_32_WO
#define HWN_POWER_RESET_SET             POWER_RESET
#define HWI_POWER_RESET_SET             
#define HW_POWER_RESET_CLR              HW(POWER_RESET_CLR)
#define HWA_POWER_RESET_CLR             (HWA_POWER_RESET + 0x8)
#define HWT_POWER_RESET_CLR             HWIO_32_WO
#define HWN_POWER_RESET_CLR             POWER_RESET
#define HWI_POWER_RESET_CLR             
#define HW_POWER_RESET_TOG              HW(POWER_RESET_TOG)
#define HWA_POWER_RESET_TOG             (HWA_POWER_RESET + 0xc)
#define HWT_POWER_RESET_TOG             HWIO_32_WO
#define HWN_POWER_RESET_TOG             POWER_RESET
#define HWI_POWER_RESET_TOG             
#define BP_POWER_RESET_UNLOCK           16
#define BM_POWER_RESET_UNLOCK           0xffff0000
#define BV_POWER_RESET_UNLOCK__KEY      0x3e77
#define BF_POWER_RESET_UNLOCK(v)        (((v) & 0xffff) << 16)
#define BFM_POWER_RESET_UNLOCK(v)       BM_POWER_RESET_UNLOCK
#define BF_POWER_RESET_UNLOCK_V(e)      BF_POWER_RESET_UNLOCK(BV_POWER_RESET_UNLOCK__##e)
#define BFM_POWER_RESET_UNLOCK_V(v)     BM_POWER_RESET_UNLOCK
#define BP_POWER_RESET_RSRVD1           2
#define BM_POWER_RESET_RSRVD1           0xfffc
#define BF_POWER_RESET_RSRVD1(v)        (((v) & 0x3fff) << 2)
#define BFM_POWER_RESET_RSRVD1(v)       BM_POWER_RESET_RSRVD1
#define BF_POWER_RESET_RSRVD1_V(e)      BF_POWER_RESET_RSRVD1(BV_POWER_RESET_RSRVD1__##e)
#define BFM_POWER_RESET_RSRVD1_V(v)     BM_POWER_RESET_RSRVD1
#define BP_POWER_RESET_PWD_OFF          1
#define BM_POWER_RESET_PWD_OFF          0x2
#define BF_POWER_RESET_PWD_OFF(v)       (((v) & 0x1) << 1)
#define BFM_POWER_RESET_PWD_OFF(v)      BM_POWER_RESET_PWD_OFF
#define BF_POWER_RESET_PWD_OFF_V(e)     BF_POWER_RESET_PWD_OFF(BV_POWER_RESET_PWD_OFF__##e)
#define BFM_POWER_RESET_PWD_OFF_V(v)    BM_POWER_RESET_PWD_OFF
#define BP_POWER_RESET_PWD              0
#define BM_POWER_RESET_PWD              0x1
#define BF_POWER_RESET_PWD(v)           (((v) & 0x1) << 0)
#define BFM_POWER_RESET_PWD(v)          BM_POWER_RESET_PWD
#define BF_POWER_RESET_PWD_V(e)         BF_POWER_RESET_PWD(BV_POWER_RESET_PWD__##e)
#define BFM_POWER_RESET_PWD_V(v)        BM_POWER_RESET_PWD

#define HW_POWER_DEBUG                          HW(POWER_DEBUG)
#define HWA_POWER_DEBUG                         (0x80044000 + 0x110)
#define HWT_POWER_DEBUG                         HWIO_32_RW
#define HWN_POWER_DEBUG                         POWER_DEBUG
#define HWI_POWER_DEBUG                         
#define HW_POWER_DEBUG_SET                      HW(POWER_DEBUG_SET)
#define HWA_POWER_DEBUG_SET                     (HWA_POWER_DEBUG + 0x4)
#define HWT_POWER_DEBUG_SET                     HWIO_32_WO
#define HWN_POWER_DEBUG_SET                     POWER_DEBUG
#define HWI_POWER_DEBUG_SET                     
#define HW_POWER_DEBUG_CLR                      HW(POWER_DEBUG_CLR)
#define HWA_POWER_DEBUG_CLR                     (HWA_POWER_DEBUG + 0x8)
#define HWT_POWER_DEBUG_CLR                     HWIO_32_WO
#define HWN_POWER_DEBUG_CLR                     POWER_DEBUG
#define HWI_POWER_DEBUG_CLR                     
#define HW_POWER_DEBUG_TOG                      HW(POWER_DEBUG_TOG)
#define HWA_POWER_DEBUG_TOG                     (HWA_POWER_DEBUG + 0xc)
#define HWT_POWER_DEBUG_TOG                     HWIO_32_WO
#define HWN_POWER_DEBUG_TOG                     POWER_DEBUG
#define HWI_POWER_DEBUG_TOG                     
#define BP_POWER_DEBUG_RSRVD0                   4
#define BM_POWER_DEBUG_RSRVD0                   0xfffffff0
#define BF_POWER_DEBUG_RSRVD0(v)                (((v) & 0xfffffff) << 4)
#define BFM_POWER_DEBUG_RSRVD0(v)               BM_POWER_DEBUG_RSRVD0
#define BF_POWER_DEBUG_RSRVD0_V(e)              BF_POWER_DEBUG_RSRVD0(BV_POWER_DEBUG_RSRVD0__##e)
#define BFM_POWER_DEBUG_RSRVD0_V(v)             BM_POWER_DEBUG_RSRVD0
#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK         3
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK         0x8
#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)      (((v) & 0x1) << 3)
#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK(v)     BM_POWER_DEBUG_VBUSVALIDPIOLOCK
#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK_V(e)    BF_POWER_DEBUG_VBUSVALIDPIOLOCK(BV_POWER_DEBUG_VBUSVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_VBUSVALIDPIOLOCK_V(v)   BM_POWER_DEBUG_VBUSVALIDPIOLOCK
#define BP_POWER_DEBUG_AVALIDPIOLOCK            2
#define BM_POWER_DEBUG_AVALIDPIOLOCK            0x4
#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)         (((v) & 0x1) << 2)
#define BFM_POWER_DEBUG_AVALIDPIOLOCK(v)        BM_POWER_DEBUG_AVALIDPIOLOCK
#define BF_POWER_DEBUG_AVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_AVALIDPIOLOCK(BV_POWER_DEBUG_AVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_AVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_AVALIDPIOLOCK
#define BP_POWER_DEBUG_BVALIDPIOLOCK            1
#define BM_POWER_DEBUG_BVALIDPIOLOCK            0x2
#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)         (((v) & 0x1) << 1)
#define BFM_POWER_DEBUG_BVALIDPIOLOCK(v)        BM_POWER_DEBUG_BVALIDPIOLOCK
#define BF_POWER_DEBUG_BVALIDPIOLOCK_V(e)       BF_POWER_DEBUG_BVALIDPIOLOCK(BV_POWER_DEBUG_BVALIDPIOLOCK__##e)
#define BFM_POWER_DEBUG_BVALIDPIOLOCK_V(v)      BM_POWER_DEBUG_BVALIDPIOLOCK
#define BP_POWER_DEBUG_SESSENDPIOLOCK           0
#define BM_POWER_DEBUG_SESSENDPIOLOCK           0x1
#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)        (((v) & 0x1) << 0)
#define BFM_POWER_DEBUG_SESSENDPIOLOCK(v)       BM_POWER_DEBUG_SESSENDPIOLOCK
#define BF_POWER_DEBUG_SESSENDPIOLOCK_V(e)      BF_POWER_DEBUG_SESSENDPIOLOCK(BV_POWER_DEBUG_SESSENDPIOLOCK__##e)
#define BFM_POWER_DEBUG_SESSENDPIOLOCK_V(v)     BM_POWER_DEBUG_SESSENDPIOLOCK

#define HW_POWER_SPECIAL            HW(POWER_SPECIAL)
#define HWA_POWER_SPECIAL           (0x80044000 + 0x120)
#define HWT_POWER_SPECIAL           HWIO_32_RW
#define HWN_POWER_SPECIAL           POWER_SPECIAL
#define HWI_POWER_SPECIAL           
#define HW_POWER_SPECIAL_SET        HW(POWER_SPECIAL_SET)
#define HWA_POWER_SPECIAL_SET       (HWA_POWER_SPECIAL + 0x4)
#define HWT_POWER_SPECIAL_SET       HWIO_32_WO
#define HWN_POWER_SPECIAL_SET       POWER_SPECIAL
#define HWI_POWER_SPECIAL_SET       
#define HW_POWER_SPECIAL_CLR        HW(POWER_SPECIAL_CLR)
#define HWA_POWER_SPECIAL_CLR       (HWA_POWER_SPECIAL + 0x8)
#define HWT_POWER_SPECIAL_CLR       HWIO_32_WO
#define HWN_POWER_SPECIAL_CLR       POWER_SPECIAL
#define HWI_POWER_SPECIAL_CLR       
#define HW_POWER_SPECIAL_TOG        HW(POWER_SPECIAL_TOG)
#define HWA_POWER_SPECIAL_TOG       (HWA_POWER_SPECIAL + 0xc)
#define HWT_POWER_SPECIAL_TOG       HWIO_32_WO
#define HWN_POWER_SPECIAL_TOG       POWER_SPECIAL
#define HWI_POWER_SPECIAL_TOG       
#define BP_POWER_SPECIAL_TEST       0
#define BM_POWER_SPECIAL_TEST       0xffffffff
#define BF_POWER_SPECIAL_TEST(v)    (((v) & 0xffffffff) << 0)
#define BFM_POWER_SPECIAL_TEST(v)   BM_POWER_SPECIAL_TEST
#define BF_POWER_SPECIAL_TEST_V(e)  BF_POWER_SPECIAL_TEST(BV_POWER_SPECIAL_TEST__##e)
#define BFM_POWER_SPECIAL_TEST_V(v) BM_POWER_SPECIAL_TEST

#define HW_POWER_VERSION                HW(POWER_VERSION)
#define HWA_POWER_VERSION               (0x80044000 + 0x130)
#define HWT_POWER_VERSION               HWIO_32_RW
#define HWN_POWER_VERSION               POWER_VERSION
#define HWI_POWER_VERSION               
#define BP_POWER_VERSION_MAJOR          24
#define BM_POWER_VERSION_MAJOR          0xff000000
#define BF_POWER_VERSION_MAJOR(v)       (((v) & 0xff) << 24)
#define BFM_POWER_VERSION_MAJOR(v)      BM_POWER_VERSION_MAJOR
#define BF_POWER_VERSION_MAJOR_V(e)     BF_POWER_VERSION_MAJOR(BV_POWER_VERSION_MAJOR__##e)
#define BFM_POWER_VERSION_MAJOR_V(v)    BM_POWER_VERSION_MAJOR
#define BP_POWER_VERSION_MINOR          16
#define BM_POWER_VERSION_MINOR          0xff0000
#define BF_POWER_VERSION_MINOR(v)       (((v) & 0xff) << 16)
#define BFM_POWER_VERSION_MINOR(v)      BM_POWER_VERSION_MINOR
#define BF_POWER_VERSION_MINOR_V(e)     BF_POWER_VERSION_MINOR(BV_POWER_VERSION_MINOR__##e)
#define BFM_POWER_VERSION_MINOR_V(v)    BM_POWER_VERSION_MINOR
#define BP_POWER_VERSION_STEP           0
#define BM_POWER_VERSION_STEP           0xffff
#define BF_POWER_VERSION_STEP(v)        (((v) & 0xffff) << 0)
#define BFM_POWER_VERSION_STEP(v)       BM_POWER_VERSION_STEP
#define BF_POWER_VERSION_STEP_V(e)      BF_POWER_VERSION_STEP(BV_POWER_VERSION_STEP__##e)
#define BFM_POWER_VERSION_STEP_V(v)     BM_POWER_VERSION_STEP

#endif /* __HEADERGEN_IMX233_POWER_H__*/
