/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * stmp3600 version: 2.4.0
 * stmp3600 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_STMP3600_SSP_H__
#define __HEADERGEN_STMP3600_SSP_H__

#define HW_SSP_CTRL0                        HW(SSP_CTRL0)
#define HWA_SSP_CTRL0                       (0x80010000 + 0x0)
#define HWT_SSP_CTRL0                       HWIO_32_RW
#define HWN_SSP_CTRL0                       SSP_CTRL0
#define HWI_SSP_CTRL0                       
#define HW_SSP_CTRL0_SET                    HW(SSP_CTRL0_SET)
#define HWA_SSP_CTRL0_SET                   (HWA_SSP_CTRL0 + 0x4)
#define HWT_SSP_CTRL0_SET                   HWIO_32_WO
#define HWN_SSP_CTRL0_SET                   SSP_CTRL0
#define HWI_SSP_CTRL0_SET                   
#define HW_SSP_CTRL0_CLR                    HW(SSP_CTRL0_CLR)
#define HWA_SSP_CTRL0_CLR                   (HWA_SSP_CTRL0 + 0x8)
#define HWT_SSP_CTRL0_CLR                   HWIO_32_WO
#define HWN_SSP_CTRL0_CLR                   SSP_CTRL0
#define HWI_SSP_CTRL0_CLR                   
#define HW_SSP_CTRL0_TOG                    HW(SSP_CTRL0_TOG)
#define HWA_SSP_CTRL0_TOG                   (HWA_SSP_CTRL0 + 0xc)
#define HWT_SSP_CTRL0_TOG                   HWIO_32_WO
#define HWN_SSP_CTRL0_TOG                   SSP_CTRL0
#define HWI_SSP_CTRL0_TOG                   
#define BP_SSP_CTRL0_SFTRST                 31
#define BM_SSP_CTRL0_SFTRST                 0x80000000
#define BF_SSP_CTRL0_SFTRST(v)              (((v) & 0x1) << 31)
#define BFM_SSP_CTRL0_SFTRST(v)             BM_SSP_CTRL0_SFTRST
#define BF_SSP_CTRL0_SFTRST_V(e)            BF_SSP_CTRL0_SFTRST(BV_SSP_CTRL0_SFTRST__##e)
#define BFM_SSP_CTRL0_SFTRST_V(v)           BM_SSP_CTRL0_SFTRST
#define BP_SSP_CTRL0_CLKGATE                30
#define BM_SSP_CTRL0_CLKGATE                0x40000000
#define BF_SSP_CTRL0_CLKGATE(v)             (((v) & 0x1) << 30)
#define BFM_SSP_CTRL0_CLKGATE(v)            BM_SSP_CTRL0_CLKGATE
#define BF_SSP_CTRL0_CLKGATE_V(e)           BF_SSP_CTRL0_CLKGATE(BV_SSP_CTRL0_CLKGATE__##e)
#define BFM_SSP_CTRL0_CLKGATE_V(v)          BM_SSP_CTRL0_CLKGATE
#define BP_SSP_CTRL0_RUN                    29
#define BM_SSP_CTRL0_RUN                    0x20000000
#define BF_SSP_CTRL0_RUN(v)                 (((v) & 0x1) << 29)
#define BFM_SSP_CTRL0_RUN(v)                BM_SSP_CTRL0_RUN
#define BF_SSP_CTRL0_RUN_V(e)               BF_SSP_CTRL0_RUN(BV_SSP_CTRL0_RUN__##e)
#define BFM_SSP_CTRL0_RUN_V(v)              BM_SSP_CTRL0_RUN
#define BP_SSP_CTRL0_HALF_DUPLEX            28
#define BM_SSP_CTRL0_HALF_DUPLEX            0x10000000
#define BF_SSP_CTRL0_HALF_DUPLEX(v)         (((v) & 0x1) << 28)
#define BFM_SSP_CTRL0_HALF_DUPLEX(v)        BM_SSP_CTRL0_HALF_DUPLEX
#define BF_SSP_CTRL0_HALF_DUPLEX_V(e)       BF_SSP_CTRL0_HALF_DUPLEX(BV_SSP_CTRL0_HALF_DUPLEX__##e)
#define BFM_SSP_CTRL0_HALF_DUPLEX_V(v)      BM_SSP_CTRL0_HALF_DUPLEX
#define BP_SSP_CTRL0_LOCK_CS                27
#define BM_SSP_CTRL0_LOCK_CS                0x8000000
#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) & 0x1) << 27)
#define BFM_SSP_CTRL0_LOCK_CS(v)            BM_SSP_CTRL0_LOCK_CS
#define BF_SSP_CTRL0_LOCK_CS_V(e)           BF_SSP_CTRL0_LOCK_CS(BV_SSP_CTRL0_LOCK_CS__##e)
#define BFM_SSP_CTRL0_LOCK_CS_V(v)          BM_SSP_CTRL0_LOCK_CS
#define BP_SSP_CTRL0_IGNORE_CRC             26
#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) & 0x1) << 26)
#define BFM_SSP_CTRL0_IGNORE_CRC(v)         BM_SSP_CTRL0_IGNORE_CRC
#define BF_SSP_CTRL0_IGNORE_CRC_V(e)        BF_SSP_CTRL0_IGNORE_CRC(BV_SSP_CTRL0_IGNORE_CRC__##e)
#define BFM_SSP_CTRL0_IGNORE_CRC_V(v)       BM_SSP_CTRL0_IGNORE_CRC
#define BP_SSP_CTRL0_READ                   25
#define BM_SSP_CTRL0_READ                   0x2000000
#define BF_SSP_CTRL0_READ(v)                (((v) & 0x1) << 25)
#define BFM_SSP_CTRL0_READ(v)               BM_SSP_CTRL0_READ
#define BF_SSP_CTRL0_READ_V(e)              BF_SSP_CTRL0_READ(BV_SSP_CTRL0_READ__##e)
#define BFM_SSP_CTRL0_READ_V(v)             BM_SSP_CTRL0_READ
#define BP_SSP_CTRL0_DATA_XFER              24
#define BM_SSP_CTRL0_DATA_XFER              0x1000000
#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) & 0x1) << 24)
#define BFM_SSP_CTRL0_DATA_XFER(v)          BM_SSP_CTRL0_DATA_XFER
#define BF_SSP_CTRL0_DATA_XFER_V(e)         BF_SSP_CTRL0_DATA_XFER(BV_SSP_CTRL0_DATA_XFER__##e)
#define BFM_SSP_CTRL0_DATA_XFER_V(v)        BM_SSP_CTRL0_DATA_XFER
#define BP_SSP_CTRL0_SDIO_IRQ               23
#define BM_SSP_CTRL0_SDIO_IRQ               0x800000
#define BF_SSP_CTRL0_SDIO_IRQ(v)            (((v) & 0x1) << 23)
#define BFM_SSP_CTRL0_SDIO_IRQ(v)           BM_SSP_CTRL0_SDIO_IRQ
#define BF_SSP_CTRL0_SDIO_IRQ_V(e)          BF_SSP_CTRL0_SDIO_IRQ(BV_SSP_CTRL0_SDIO_IRQ__##e)
#define BFM_SSP_CTRL0_SDIO_IRQ_V(v)         BM_SSP_CTRL0_SDIO_IRQ
#define BP_SSP_CTRL0_BUS_WIDTH              22
#define BM_SSP_CTRL0_BUS_WIDTH              0x400000
#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) & 0x1) << 22)
#define BFM_SSP_CTRL0_BUS_WIDTH(v)          BM_SSP_CTRL0_BUS_WIDTH
#define BF_SSP_CTRL0_BUS_WIDTH_V(e)         BF_SSP_CTRL0_BUS_WIDTH(BV_SSP_CTRL0_BUS_WIDTH__##e)
#define BFM_SSP_CTRL0_BUS_WIDTH_V(v)        BM_SSP_CTRL0_BUS_WIDTH
#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) & 0x1) << 21)
#define BFM_SSP_CTRL0_WAIT_FOR_IRQ(v)       BM_SSP_CTRL0_WAIT_FOR_IRQ
#define BF_SSP_CTRL0_WAIT_FOR_IRQ_V(e)      BF_SSP_CTRL0_WAIT_FOR_IRQ(BV_SSP_CTRL0_WAIT_FOR_IRQ__##e)
#define BFM_SSP_CTRL0_WAIT_FOR_IRQ_V(v)     BM_SSP_CTRL0_WAIT_FOR_IRQ
#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) & 0x1) << 20)
#define BFM_SSP_CTRL0_WAIT_FOR_CMD(v)       BM_SSP_CTRL0_WAIT_FOR_CMD
#define BF_SSP_CTRL0_WAIT_FOR_CMD_V(e)      BF_SSP_CTRL0_WAIT_FOR_CMD(BV_SSP_CTRL0_WAIT_FOR_CMD__##e)
#define BFM_SSP_CTRL0_WAIT_FOR_CMD_V(v)     BM_SSP_CTRL0_WAIT_FOR_CMD
#define BP_SSP_CTRL0_LONG_RESP              19
#define BM_SSP_CTRL0_LONG_RESP              0x80000
#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) & 0x1) << 19)
#define BFM_SSP_CTRL0_LONG_RESP(v)          BM_SSP_CTRL0_LONG_RESP
#define BF_SSP_CTRL0_LONG_RESP_V(e)         BF_SSP_CTRL0_LONG_RESP(BV_SSP_CTRL0_LONG_RESP__##e)
#define BFM_SSP_CTRL0_LONG_RESP_V(v)        BM_SSP_CTRL0_LONG_RESP
#define BP_SSP_CTRL0_CHECK_RESP             18
#define BM_SSP_CTRL0_CHECK_RESP             0x40000
#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) & 0x1) << 18)
#define BFM_SSP_CTRL0_CHECK_RESP(v)         BM_SSP_CTRL0_CHECK_RESP
#define BF_SSP_CTRL0_CHECK_RESP_V(e)        BF_SSP_CTRL0_CHECK_RESP(BV_SSP_CTRL0_CHECK_RESP__##e)
#define BFM_SSP_CTRL0_CHECK_RESP_V(v)       BM_SSP_CTRL0_CHECK_RESP
#define BP_SSP_CTRL0_GET_RESP               17
#define BM_SSP_CTRL0_GET_RESP               0x20000
#define BF_SSP_CTRL0_GET_RESP(v)            (((v) & 0x1) << 17)
#define BFM_SSP_CTRL0_GET_RESP(v)           BM_SSP_CTRL0_GET_RESP
#define BF_SSP_CTRL0_GET_RESP_V(e)          BF_SSP_CTRL0_GET_RESP(BV_SSP_CTRL0_GET_RESP__##e)
#define BFM_SSP_CTRL0_GET_RESP_V(v)         BM_SSP_CTRL0_GET_RESP
#define BP_SSP_CTRL0_ENABLE                 16
#define BM_SSP_CTRL0_ENABLE                 0x10000
#define BF_SSP_CTRL0_ENABLE(v)              (((v) & 0x1) << 16)
#define BFM_SSP_CTRL0_ENABLE(v)             BM_SSP_CTRL0_ENABLE
#define BF_SSP_CTRL0_ENABLE_V(e)            BF_SSP_CTRL0_ENABLE(BV_SSP_CTRL0_ENABLE__##e)
#define BFM_SSP_CTRL0_ENABLE_V(v)           BM_SSP_CTRL0_ENABLE
#define BP_SSP_CTRL0_XFER_COUNT             0
#define BM_SSP_CTRL0_XFER_COUNT             0xffff
#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) & 0xffff) << 0)
#define BFM_SSP_CTRL0_XFER_COUNT(v)         BM_SSP_CTRL0_XFER_COUNT
#define BF_SSP_CTRL0_XFER_COUNT_V(e)        BF_SSP_CTRL0_XFER_COUNT(BV_SSP_CTRL0_XFER_COUNT__##e)
#define BFM_SSP_CTRL0_XFER_COUNT_V(v)       BM_SSP_CTRL0_XFER_COUNT

#define HW_SSP_CMD0                                 HW(SSP_CMD0)
#define HWA_SSP_CMD0                                (0x80010000 + 0x10)
#define HWT_SSP_CMD0                                HWIO_32_RW
#define HWN_SSP_CMD0                                SSP_CMD0
#define HWI_SSP_CMD0                                
#define HW_SSP_CMD0_SET                             HW(SSP_CMD0_SET)
#define HWA_SSP_CMD0_SET                            (HWA_SSP_CMD0 + 0x4)
#define HWT_SSP_CMD0_SET                            HWIO_32_WO
#define HWN_SSP_CMD0_SET                            SSP_CMD0
#define HWI_SSP_CMD0_SET                            
#define HW_SSP_CMD0_CLR                             HW(SSP_CMD0_CLR)
#define HWA_SSP_CMD0_CLR                            (HWA_SSP_CMD0 + 0x8)
#define HWT_SSP_CMD0_CLR                            HWIO_32_WO
#define HWN_SSP_CMD0_CLR                            SSP_CMD0
#define HWI_SSP_CMD0_CLR                            
#define HW_SSP_CMD0_TOG                             HW(SSP_CMD0_TOG)
#define HWA_SSP_CMD0_TOG                            (HWA_SSP_CMD0 + 0xc)
#define HWT_SSP_CMD0_TOG                            HWIO_32_WO
#define HWN_SSP_CMD0_TOG                            SSP_CMD0
#define HWI_SSP_CMD0_TOG                            
#define BP_SSP_CMD0_CMD                             0
#define BM_SSP_CMD0_CMD                             0xff
#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
#define BF_SSP_CMD0_CMD(v)                          (((v) & 0xff) << 0)
#define BFM_SSP_CMD0_CMD(v)                         BM_SSP_CMD0_CMD
#define BF_SSP_CMD0_CMD_V(e)                        BF_SSP_CMD0_CMD(BV_SSP_CMD0_CMD__##e)
#define BFM_SSP_CMD0_CMD_V(v)                       BM_SSP_CMD0_CMD

#define HW_SSP_CMD1                 HW(SSP_CMD1)
#define HWA_SSP_CMD1                (0x80010000 + 0x20)
#define HWT_SSP_CMD1                HWIO_32_RW
#define HWN_SSP_CMD1                SSP_CMD1
#define HWI_SSP_CMD1                
#define BP_SSP_CMD1_CMD_ARG         0
#define BM_SSP_CMD1_CMD_ARG         0xffffffff
#define BF_SSP_CMD1_CMD_ARG(v)      (((v) & 0xffffffff) << 0)
#define BFM_SSP_CMD1_CMD_ARG(v)     BM_SSP_CMD1_CMD_ARG
#define BF_SSP_CMD1_CMD_ARG_V(e)    BF_SSP_CMD1_CMD_ARG(BV_SSP_CMD1_CMD_ARG__##e)
#define BFM_SSP_CMD1_CMD_ARG_V(v)   BM_SSP_CMD1_CMD_ARG

#define HW_SSP_COMPREF                  HW(SSP_COMPREF)
#define HWA_SSP_COMPREF                 (0x80010000 + 0x30)
#define HWT_SSP_COMPREF                 HWIO_32_RW
#define HWN_SSP_COMPREF                 SSP_COMPREF
#define HWI_SSP_COMPREF                 
#define BP_SSP_COMPREF_REFERENCE        0
#define BM_SSP_COMPREF_REFERENCE        0xffffffff
#define BF_SSP_COMPREF_REFERENCE(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_COMPREF_REFERENCE(v)    BM_SSP_COMPREF_REFERENCE
#define BF_SSP_COMPREF_REFERENCE_V(e)   BF_SSP_COMPREF_REFERENCE(BV_SSP_COMPREF_REFERENCE__##e)
#define BFM_SSP_COMPREF_REFERENCE_V(v)  BM_SSP_COMPREF_REFERENCE

#define HW_SSP_COMPMASK             HW(SSP_COMPMASK)
#define HWA_SSP_COMPMASK            (0x80010000 + 0x40)
#define HWT_SSP_COMPMASK            HWIO_32_RW
#define HWN_SSP_COMPMASK            SSP_COMPMASK
#define HWI_SSP_COMPMASK            
#define BP_SSP_COMPMASK_MASK        0
#define BM_SSP_COMPMASK_MASK        0xffffffff
#define BF_SSP_COMPMASK_MASK(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_COMPMASK_MASK(v)    BM_SSP_COMPMASK_MASK
#define BF_SSP_COMPMASK_MASK_V(e)   BF_SSP_COMPMASK_MASK(BV_SSP_COMPMASK_MASK__##e)
#define BFM_SSP_COMPMASK_MASK_V(v)  BM_SSP_COMPMASK_MASK

#define HW_SSP_TIMING                       HW(SSP_TIMING)
#define HWA_SSP_TIMING                      (0x80010000 + 0x50)
#define HWT_SSP_TIMING                      HWIO_32_RW
#define HWN_SSP_TIMING                      SSP_TIMING
#define HWI_SSP_TIMING                      
#define BP_SSP_TIMING_TIMEOUT               16
#define BM_SSP_TIMING_TIMEOUT               0xffff0000
#define BF_SSP_TIMING_TIMEOUT(v)            (((v) & 0xffff) << 16)
#define BFM_SSP_TIMING_TIMEOUT(v)           BM_SSP_TIMING_TIMEOUT
#define BF_SSP_TIMING_TIMEOUT_V(e)          BF_SSP_TIMING_TIMEOUT(BV_SSP_TIMING_TIMEOUT__##e)
#define BFM_SSP_TIMING_TIMEOUT_V(v)         BM_SSP_TIMING_TIMEOUT
#define BP_SSP_TIMING_CLOCK_DIVIDE          8
#define BM_SSP_TIMING_CLOCK_DIVIDE          0xff00
#define BF_SSP_TIMING_CLOCK_DIVIDE(v)       (((v) & 0xff) << 8)
#define BFM_SSP_TIMING_CLOCK_DIVIDE(v)      BM_SSP_TIMING_CLOCK_DIVIDE
#define BF_SSP_TIMING_CLOCK_DIVIDE_V(e)     BF_SSP_TIMING_CLOCK_DIVIDE(BV_SSP_TIMING_CLOCK_DIVIDE__##e)
#define BFM_SSP_TIMING_CLOCK_DIVIDE_V(v)    BM_SSP_TIMING_CLOCK_DIVIDE
#define BP_SSP_TIMING_CLOCK_RATE            0
#define BM_SSP_TIMING_CLOCK_RATE            0xff
#define BF_SSP_TIMING_CLOCK_RATE(v)         (((v) & 0xff) << 0)
#define BFM_SSP_TIMING_CLOCK_RATE(v)        BM_SSP_TIMING_CLOCK_RATE
#define BF_SSP_TIMING_CLOCK_RATE_V(e)       BF_SSP_TIMING_CLOCK_RATE(BV_SSP_TIMING_CLOCK_RATE__##e)
#define BFM_SSP_TIMING_CLOCK_RATE_V(v)      BM_SSP_TIMING_CLOCK_RATE

#define HW_SSP_CTRL1                            HW(SSP_CTRL1)
#define HWA_SSP_CTRL1                           (0x80010000 + 0x60)
#define HWT_SSP_CTRL1                           HWIO_32_RW
#define HWN_SSP_CTRL1                           SSP_CTRL1
#define HWI_SSP_CTRL1                           
#define HW_SSP_CTRL1_SET                        HW(SSP_CTRL1_SET)
#define HWA_SSP_CTRL1_SET                       (HWA_SSP_CTRL1 + 0x4)
#define HWT_SSP_CTRL1_SET                       HWIO_32_WO
#define HWN_SSP_CTRL1_SET                       SSP_CTRL1
#define HWI_SSP_CTRL1_SET                       
#define HW_SSP_CTRL1_CLR                        HW(SSP_CTRL1_CLR)
#define HWA_SSP_CTRL1_CLR                       (HWA_SSP_CTRL1 + 0x8)
#define HWT_SSP_CTRL1_CLR                       HWIO_32_WO
#define HWN_SSP_CTRL1_CLR                       SSP_CTRL1
#define HWI_SSP_CTRL1_CLR                       
#define HW_SSP_CTRL1_TOG                        HW(SSP_CTRL1_TOG)
#define HWA_SSP_CTRL1_TOG                       (HWA_SSP_CTRL1 + 0xc)
#define HWT_SSP_CTRL1_TOG                       HWIO_32_WO
#define HWN_SSP_CTRL1_TOG                       SSP_CTRL1
#define HWI_SSP_CTRL1_TOG                       
#define BP_SSP_CTRL1_SDIO_IRQ                   31
#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) & 0x1) << 31)
#define BFM_SSP_CTRL1_SDIO_IRQ(v)               BM_SSP_CTRL1_SDIO_IRQ
#define BF_SSP_CTRL1_SDIO_IRQ_V(e)              BF_SSP_CTRL1_SDIO_IRQ(BV_SSP_CTRL1_SDIO_IRQ__##e)
#define BFM_SSP_CTRL1_SDIO_IRQ_V(v)             BM_SSP_CTRL1_SDIO_IRQ
#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) & 0x1) << 30)
#define BFM_SSP_CTRL1_SDIO_IRQ_EN(v)            BM_SSP_CTRL1_SDIO_IRQ_EN
#define BF_SSP_CTRL1_SDIO_IRQ_EN_V(e)           BF_SSP_CTRL1_SDIO_IRQ_EN(BV_SSP_CTRL1_SDIO_IRQ_EN__##e)
#define BFM_SSP_CTRL1_SDIO_IRQ_EN_V(v)          BM_SSP_CTRL1_SDIO_IRQ_EN
#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) & 0x1) << 29)
#define BFM_SSP_CTRL1_RESP_ERR_IRQ(v)           BM_SSP_CTRL1_RESP_ERR_IRQ
#define BF_SSP_CTRL1_RESP_ERR_IRQ_V(e)          BF_SSP_CTRL1_RESP_ERR_IRQ(BV_SSP_CTRL1_RESP_ERR_IRQ__##e)
#define BFM_SSP_CTRL1_RESP_ERR_IRQ_V(v)         BM_SSP_CTRL1_RESP_ERR_IRQ
#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) & 0x1) << 28)
#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN(v)        BM_SSP_CTRL1_RESP_ERR_IRQ_EN
#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN_V(e)       BF_SSP_CTRL1_RESP_ERR_IRQ_EN(BV_SSP_CTRL1_RESP_ERR_IRQ_EN__##e)
#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN_V(v)      BM_SSP_CTRL1_RESP_ERR_IRQ_EN
#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) & 0x1) << 27)
#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ__##e)
#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 26)
#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN__##e)
#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) & 0x1) << 25)
#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ__##e)
#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 24)
#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN__##e)
#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) & 0x1) << 23)
#define BFM_SSP_CTRL1_DATA_CRC_IRQ(v)           BM_SSP_CTRL1_DATA_CRC_IRQ
#define BF_SSP_CTRL1_DATA_CRC_IRQ_V(e)          BF_SSP_CTRL1_DATA_CRC_IRQ(BV_SSP_CTRL1_DATA_CRC_IRQ__##e)
#define BFM_SSP_CTRL1_DATA_CRC_IRQ_V(v)         BM_SSP_CTRL1_DATA_CRC_IRQ
#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) & 0x1) << 22)
#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN(v)        BM_SSP_CTRL1_DATA_CRC_IRQ_EN
#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN_V(e)       BF_SSP_CTRL1_DATA_CRC_IRQ_EN(BV_SSP_CTRL1_DATA_CRC_IRQ_EN__##e)
#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN_V(v)      BM_SSP_CTRL1_DATA_CRC_IRQ_EN
#define BP_SSP_CTRL1_XMIT_IRQ                   21
#define BM_SSP_CTRL1_XMIT_IRQ                   0x200000
#define BF_SSP_CTRL1_XMIT_IRQ(v)                (((v) & 0x1) << 21)
#define BFM_SSP_CTRL1_XMIT_IRQ(v)               BM_SSP_CTRL1_XMIT_IRQ
#define BF_SSP_CTRL1_XMIT_IRQ_V(e)              BF_SSP_CTRL1_XMIT_IRQ(BV_SSP_CTRL1_XMIT_IRQ__##e)
#define BFM_SSP_CTRL1_XMIT_IRQ_V(v)             BM_SSP_CTRL1_XMIT_IRQ
#define BP_SSP_CTRL1_XMIT_IRQ_EN                20
#define BM_SSP_CTRL1_XMIT_IRQ_EN                0x100000
#define BF_SSP_CTRL1_XMIT_IRQ_EN(v)             (((v) & 0x1) << 20)
#define BFM_SSP_CTRL1_XMIT_IRQ_EN(v)            BM_SSP_CTRL1_XMIT_IRQ_EN
#define BF_SSP_CTRL1_XMIT_IRQ_EN_V(e)           BF_SSP_CTRL1_XMIT_IRQ_EN(BV_SSP_CTRL1_XMIT_IRQ_EN__##e)
#define BFM_SSP_CTRL1_XMIT_IRQ_EN_V(v)          BM_SSP_CTRL1_XMIT_IRQ_EN
#define BP_SSP_CTRL1_RECV_IRQ                   19
#define BM_SSP_CTRL1_RECV_IRQ                   0x80000
#define BF_SSP_CTRL1_RECV_IRQ(v)                (((v) & 0x1) << 19)
#define BFM_SSP_CTRL1_RECV_IRQ(v)               BM_SSP_CTRL1_RECV_IRQ
#define BF_SSP_CTRL1_RECV_IRQ_V(e)              BF_SSP_CTRL1_RECV_IRQ(BV_SSP_CTRL1_RECV_IRQ__##e)
#define BFM_SSP_CTRL1_RECV_IRQ_V(v)             BM_SSP_CTRL1_RECV_IRQ
#define BP_SSP_CTRL1_RECV_IRQ_EN                18
#define BM_SSP_CTRL1_RECV_IRQ_EN                0x40000
#define BF_SSP_CTRL1_RECV_IRQ_EN(v)             (((v) & 0x1) << 18)
#define BFM_SSP_CTRL1_RECV_IRQ_EN(v)            BM_SSP_CTRL1_RECV_IRQ_EN
#define BF_SSP_CTRL1_RECV_IRQ_EN_V(e)           BF_SSP_CTRL1_RECV_IRQ_EN(BV_SSP_CTRL1_RECV_IRQ_EN__##e)
#define BFM_SSP_CTRL1_RECV_IRQ_EN_V(v)          BM_SSP_CTRL1_RECV_IRQ_EN
#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) & 0x1) << 17)
#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)       BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(e)      BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ__##e)
#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(v)     BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) & 0x1) << 16)
#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(e)   BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN__##e)
#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(v)  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ            15
#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ            0x8000
#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v)         (((v) & 0x1) << 15)
#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ(v)        BM_SSP_CTRL1_RECV_OVRFLW_IRQ
#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_V(e)       BF_SSP_CTRL1_RECV_OVRFLW_IRQ(BV_SSP_CTRL1_RECV_OVRFLW_IRQ__##e)
#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_V(v)      BM_SSP_CTRL1_RECV_OVRFLW_IRQ
#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         14
#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         0x4000
#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)      (((v) & 0x1) << 14)
#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)     BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN
#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN_V(e)    BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(BV_SSP_CTRL1_RECV_OVRFLW_IRQ_EN__##e)
#define BFM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN_V(v)   BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN
#define BP_SSP_CTRL1_DMA_ENABLE                 13
#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) & 0x1) << 13)
#define BFM_SSP_CTRL1_DMA_ENABLE(v)             BM_SSP_CTRL1_DMA_ENABLE
#define BF_SSP_CTRL1_DMA_ENABLE_V(e)            BF_SSP_CTRL1_DMA_ENABLE(BV_SSP_CTRL1_DMA_ENABLE__##e)
#define BFM_SSP_CTRL1_DMA_ENABLE_V(v)           BM_SSP_CTRL1_DMA_ENABLE
#define BP_SSP_CTRL1_LOOPBACK                   12
#define BM_SSP_CTRL1_LOOPBACK                   0x1000
#define BF_SSP_CTRL1_LOOPBACK(v)                (((v) & 0x1) << 12)
#define BFM_SSP_CTRL1_LOOPBACK(v)               BM_SSP_CTRL1_LOOPBACK
#define BF_SSP_CTRL1_LOOPBACK_V(e)              BF_SSP_CTRL1_LOOPBACK(BV_SSP_CTRL1_LOOPBACK__##e)
#define BFM_SSP_CTRL1_LOOPBACK_V(v)             BM_SSP_CTRL1_LOOPBACK
#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) & 0x1) << 11)
#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE(v)      BM_SSP_CTRL1_SLAVE_OUT_DISABLE
#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE_V(e)     BF_SSP_CTRL1_SLAVE_OUT_DISABLE(BV_SSP_CTRL1_SLAVE_OUT_DISABLE__##e)
#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE_V(v)    BM_SSP_CTRL1_SLAVE_OUT_DISABLE
#define BP_SSP_CTRL1_PHASE                      10
#define BM_SSP_CTRL1_PHASE                      0x400
#define BF_SSP_CTRL1_PHASE(v)                   (((v) & 0x1) << 10)
#define BFM_SSP_CTRL1_PHASE(v)                  BM_SSP_CTRL1_PHASE
#define BF_SSP_CTRL1_PHASE_V(e)                 BF_SSP_CTRL1_PHASE(BV_SSP_CTRL1_PHASE__##e)
#define BFM_SSP_CTRL1_PHASE_V(v)                BM_SSP_CTRL1_PHASE
#define BP_SSP_CTRL1_POLARITY                   9
#define BM_SSP_CTRL1_POLARITY                   0x200
#define BF_SSP_CTRL1_POLARITY(v)                (((v) & 0x1) << 9)
#define BFM_SSP_CTRL1_POLARITY(v)               BM_SSP_CTRL1_POLARITY
#define BF_SSP_CTRL1_POLARITY_V(e)              BF_SSP_CTRL1_POLARITY(BV_SSP_CTRL1_POLARITY__##e)
#define BFM_SSP_CTRL1_POLARITY_V(v)             BM_SSP_CTRL1_POLARITY
#define BP_SSP_CTRL1_SLAVE_MODE                 8
#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) & 0x1) << 8)
#define BFM_SSP_CTRL1_SLAVE_MODE(v)             BM_SSP_CTRL1_SLAVE_MODE
#define BF_SSP_CTRL1_SLAVE_MODE_V(e)            BF_SSP_CTRL1_SLAVE_MODE(BV_SSP_CTRL1_SLAVE_MODE__##e)
#define BFM_SSP_CTRL1_SLAVE_MODE_V(v)           BM_SSP_CTRL1_SLAVE_MODE
#define BP_SSP_CTRL1_WORD_LENGTH                4
#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) & 0xf) << 4)
#define BFM_SSP_CTRL1_WORD_LENGTH(v)            BM_SSP_CTRL1_WORD_LENGTH
#define BF_SSP_CTRL1_WORD_LENGTH_V(e)           BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__##e)
#define BFM_SSP_CTRL1_WORD_LENGTH_V(v)          BM_SSP_CTRL1_WORD_LENGTH
#define BP_SSP_CTRL1_SSP_MODE                   0
#define BM_SSP_CTRL1_SSP_MODE                   0xf
#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
#define BV_SSP_CTRL1_SSP_MODE__MICROWIRE        0x2
#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) & 0xf) << 0)
#define BFM_SSP_CTRL1_SSP_MODE(v)               BM_SSP_CTRL1_SSP_MODE
#define BF_SSP_CTRL1_SSP_MODE_V(e)              BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__##e)
#define BFM_SSP_CTRL1_SSP_MODE_V(v)             BM_SSP_CTRL1_SSP_MODE

#define HW_SSP_DATA             HW(SSP_DATA)
#define HWA_SSP_DATA            (0x80010000 + 0x70)
#define HWT_SSP_DATA            HWIO_32_RW
#define HWN_SSP_DATA            SSP_DATA
#define HWI_SSP_DATA            
#define BP_SSP_DATA_DATA        0
#define BM_SSP_DATA_DATA        0xffffffff
#define BF_SSP_DATA_DATA(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_DATA_DATA(v)    BM_SSP_DATA_DATA
#define BF_SSP_DATA_DATA_V(e)   BF_SSP_DATA_DATA(BV_SSP_DATA_DATA__##e)
#define BFM_SSP_DATA_DATA_V(v)  BM_SSP_DATA_DATA

#define HW_SSP_SDRESP0              HW(SSP_SDRESP0)
#define HWA_SSP_SDRESP0             (0x80010000 + 0x80)
#define HWT_SSP_SDRESP0             HWIO_32_RW
#define HWN_SSP_SDRESP0             SSP_SDRESP0
#define HWI_SSP_SDRESP0             
#define BP_SSP_SDRESP0_RESP0        0
#define BM_SSP_SDRESP0_RESP0        0xffffffff
#define BF_SSP_SDRESP0_RESP0(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_SDRESP0_RESP0(v)    BM_SSP_SDRESP0_RESP0
#define BF_SSP_SDRESP0_RESP0_V(e)   BF_SSP_SDRESP0_RESP0(BV_SSP_SDRESP0_RESP0__##e)
#define BFM_SSP_SDRESP0_RESP0_V(v)  BM_SSP_SDRESP0_RESP0

#define HW_SSP_SDRESP1              HW(SSP_SDRESP1)
#define HWA_SSP_SDRESP1             (0x80010000 + 0x90)
#define HWT_SSP_SDRESP1             HWIO_32_RW
#define HWN_SSP_SDRESP1             SSP_SDRESP1
#define HWI_SSP_SDRESP1             
#define BP_SSP_SDRESP1_RESP1        0
#define BM_SSP_SDRESP1_RESP1        0xffffffff
#define BF_SSP_SDRESP1_RESP1(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_SDRESP1_RESP1(v)    BM_SSP_SDRESP1_RESP1
#define BF_SSP_SDRESP1_RESP1_V(e)   BF_SSP_SDRESP1_RESP1(BV_SSP_SDRESP1_RESP1__##e)
#define BFM_SSP_SDRESP1_RESP1_V(v)  BM_SSP_SDRESP1_RESP1

#define HW_SSP_SDRESP2              HW(SSP_SDRESP2)
#define HWA_SSP_SDRESP2             (0x80010000 + 0xa0)
#define HWT_SSP_SDRESP2             HWIO_32_RW
#define HWN_SSP_SDRESP2             SSP_SDRESP2
#define HWI_SSP_SDRESP2             
#define BP_SSP_SDRESP2_RESP2        0
#define BM_SSP_SDRESP2_RESP2        0xffffffff
#define BF_SSP_SDRESP2_RESP2(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_SDRESP2_RESP2(v)    BM_SSP_SDRESP2_RESP2
#define BF_SSP_SDRESP2_RESP2_V(e)   BF_SSP_SDRESP2_RESP2(BV_SSP_SDRESP2_RESP2__##e)
#define BFM_SSP_SDRESP2_RESP2_V(v)  BM_SSP_SDRESP2_RESP2

#define HW_SSP_SDRESP3              HW(SSP_SDRESP3)
#define HWA_SSP_SDRESP3             (0x80010000 + 0xb0)
#define HWT_SSP_SDRESP3             HWIO_32_RW
#define HWN_SSP_SDRESP3             SSP_SDRESP3
#define HWI_SSP_SDRESP3             
#define BP_SSP_SDRESP3_RESP3        0
#define BM_SSP_SDRESP3_RESP3        0xffffffff
#define BF_SSP_SDRESP3_RESP3(v)     (((v) & 0xffffffff) << 0)
#define BFM_SSP_SDRESP3_RESP3(v)    BM_SSP_SDRESP3_RESP3
#define BF_SSP_SDRESP3_RESP3_V(e)   BF_SSP_SDRESP3_RESP3(BV_SSP_SDRESP3_RESP3__##e)
#define BFM_SSP_SDRESP3_RESP3_V(v)  BM_SSP_SDRESP3_RESP3

#define HW_SSP_STATUS                           HW(SSP_STATUS)
#define HWA_SSP_STATUS                          (0x80010000 + 0xc0)
#define HWT_SSP_STATUS                          HWIO_32_RW
#define HWN_SSP_STATUS                          SSP_STATUS
#define HWI_SSP_STATUS                          
#define BP_SSP_STATUS_PRESENT                   31
#define BM_SSP_STATUS_PRESENT                   0x80000000
#define BF_SSP_STATUS_PRESENT(v)                (((v) & 0x1) << 31)
#define BFM_SSP_STATUS_PRESENT(v)               BM_SSP_STATUS_PRESENT
#define BF_SSP_STATUS_PRESENT_V(e)              BF_SSP_STATUS_PRESENT(BV_SSP_STATUS_PRESENT__##e)
#define BFM_SSP_STATUS_PRESENT_V(v)             BM_SSP_STATUS_PRESENT
#define BP_SSP_STATUS_MS_PRESENT                30
#define BM_SSP_STATUS_MS_PRESENT                0x40000000
#define BF_SSP_STATUS_MS_PRESENT(v)             (((v) & 0x1) << 30)
#define BFM_SSP_STATUS_MS_PRESENT(v)            BM_SSP_STATUS_MS_PRESENT
#define BF_SSP_STATUS_MS_PRESENT_V(e)           BF_SSP_STATUS_MS_PRESENT(BV_SSP_STATUS_MS_PRESENT__##e)
#define BFM_SSP_STATUS_MS_PRESENT_V(v)          BM_SSP_STATUS_MS_PRESENT
#define BP_SSP_STATUS_SD_PRESENT                29
#define BM_SSP_STATUS_SD_PRESENT                0x20000000
#define BF_SSP_STATUS_SD_PRESENT(v)             (((v) & 0x1) << 29)
#define BFM_SSP_STATUS_SD_PRESENT(v)            BM_SSP_STATUS_SD_PRESENT
#define BF_SSP_STATUS_SD_PRESENT_V(e)           BF_SSP_STATUS_SD_PRESENT(BV_SSP_STATUS_SD_PRESENT__##e)
#define BFM_SSP_STATUS_SD_PRESENT_V(v)          BM_SSP_STATUS_SD_PRESENT
#define BP_SSP_STATUS_CARD_DETECT               28
#define BM_SSP_STATUS_CARD_DETECT               0x10000000
#define BF_SSP_STATUS_CARD_DETECT(v)            (((v) & 0x1) << 28)
#define BFM_SSP_STATUS_CARD_DETECT(v)           BM_SSP_STATUS_CARD_DETECT
#define BF_SSP_STATUS_CARD_DETECT_V(e)          BF_SSP_STATUS_CARD_DETECT(BV_SSP_STATUS_CARD_DETECT__##e)
#define BFM_SSP_STATUS_CARD_DETECT_V(v)         BM_SSP_STATUS_CARD_DETECT
#define BP_SSP_STATUS_RECV_COUNT                24
#define BM_SSP_STATUS_RECV_COUNT                0xf000000
#define BF_SSP_STATUS_RECV_COUNT(v)             (((v) & 0xf) << 24)
#define BFM_SSP_STATUS_RECV_COUNT(v)            BM_SSP_STATUS_RECV_COUNT
#define BF_SSP_STATUS_RECV_COUNT_V(e)           BF_SSP_STATUS_RECV_COUNT(BV_SSP_STATUS_RECV_COUNT__##e)
#define BFM_SSP_STATUS_RECV_COUNT_V(v)          BM_SSP_STATUS_RECV_COUNT
#define BP_SSP_STATUS_XMIT_COUNT                20
#define BM_SSP_STATUS_XMIT_COUNT                0xf00000
#define BF_SSP_STATUS_XMIT_COUNT(v)             (((v) & 0xf) << 20)
#define BFM_SSP_STATUS_XMIT_COUNT(v)            BM_SSP_STATUS_XMIT_COUNT
#define BF_SSP_STATUS_XMIT_COUNT_V(e)           BF_SSP_STATUS_XMIT_COUNT(BV_SSP_STATUS_XMIT_COUNT__##e)
#define BFM_SSP_STATUS_XMIT_COUNT_V(v)          BM_SSP_STATUS_XMIT_COUNT
#define BP_SSP_STATUS_DMAREQ                    19
#define BM_SSP_STATUS_DMAREQ                    0x80000
#define BF_SSP_STATUS_DMAREQ(v)                 (((v) & 0x1) << 19)
#define BFM_SSP_STATUS_DMAREQ(v)                BM_SSP_STATUS_DMAREQ
#define BF_SSP_STATUS_DMAREQ_V(e)               BF_SSP_STATUS_DMAREQ(BV_SSP_STATUS_DMAREQ__##e)
#define BFM_SSP_STATUS_DMAREQ_V(v)              BM_SSP_STATUS_DMAREQ
#define BP_SSP_STATUS_DMAEND                    18
#define BM_SSP_STATUS_DMAEND                    0x40000
#define BF_SSP_STATUS_DMAEND(v)                 (((v) & 0x1) << 18)
#define BFM_SSP_STATUS_DMAEND(v)                BM_SSP_STATUS_DMAEND
#define BF_SSP_STATUS_DMAEND_V(e)               BF_SSP_STATUS_DMAEND(BV_SSP_STATUS_DMAEND__##e)
#define BFM_SSP_STATUS_DMAEND_V(v)              BM_SSP_STATUS_DMAEND
#define BP_SSP_STATUS_SDIO_IRQ                  17
#define BM_SSP_STATUS_SDIO_IRQ                  0x20000
#define BF_SSP_STATUS_SDIO_IRQ(v)               (((v) & 0x1) << 17)
#define BFM_SSP_STATUS_SDIO_IRQ(v)              BM_SSP_STATUS_SDIO_IRQ
#define BF_SSP_STATUS_SDIO_IRQ_V(e)             BF_SSP_STATUS_SDIO_IRQ(BV_SSP_STATUS_SDIO_IRQ__##e)
#define BFM_SSP_STATUS_SDIO_IRQ_V(v)            BM_SSP_STATUS_SDIO_IRQ
#define BP_SSP_STATUS_RESP_CRC_ERR              16
#define BM_SSP_STATUS_RESP_CRC_ERR              0x10000
#define BF_SSP_STATUS_RESP_CRC_ERR(v)           (((v) & 0x1) << 16)
#define BFM_SSP_STATUS_RESP_CRC_ERR(v)          BM_SSP_STATUS_RESP_CRC_ERR
#define BF_SSP_STATUS_RESP_CRC_ERR_V(e)         BF_SSP_STATUS_RESP_CRC_ERR(BV_SSP_STATUS_RESP_CRC_ERR__##e)
#define BFM_SSP_STATUS_RESP_CRC_ERR_V(v)        BM_SSP_STATUS_RESP_CRC_ERR
#define BP_SSP_STATUS_RESP_ERR                  15
#define BM_SSP_STATUS_RESP_ERR                  0x8000
#define BF_SSP_STATUS_RESP_ERR(v)               (((v) & 0x1) << 15)
#define BFM_SSP_STATUS_RESP_ERR(v)              BM_SSP_STATUS_RESP_ERR
#define BF_SSP_STATUS_RESP_ERR_V(e)             BF_SSP_STATUS_RESP_ERR(BV_SSP_STATUS_RESP_ERR__##e)
#define BFM_SSP_STATUS_RESP_ERR_V(v)            BM_SSP_STATUS_RESP_ERR
#define BP_SSP_STATUS_RESP_TIMEOUT              14
#define BM_SSP_STATUS_RESP_TIMEOUT              0x4000
#define BF_SSP_STATUS_RESP_TIMEOUT(v)           (((v) & 0x1) << 14)
#define BFM_SSP_STATUS_RESP_TIMEOUT(v)          BM_SSP_STATUS_RESP_TIMEOUT
#define BF_SSP_STATUS_RESP_TIMEOUT_V(e)         BF_SSP_STATUS_RESP_TIMEOUT(BV_SSP_STATUS_RESP_TIMEOUT__##e)
#define BFM_SSP_STATUS_RESP_TIMEOUT_V(v)        BM_SSP_STATUS_RESP_TIMEOUT
#define BP_SSP_STATUS_DATA_CRC_ERR              13
#define BM_SSP_STATUS_DATA_CRC_ERR              0x2000
#define BF_SSP_STATUS_DATA_CRC_ERR(v)           (((v) & 0x1) << 13)
#define BFM_SSP_STATUS_DATA_CRC_ERR(v)          BM_SSP_STATUS_DATA_CRC_ERR
#define BF_SSP_STATUS_DATA_CRC_ERR_V(e)         BF_SSP_STATUS_DATA_CRC_ERR(BV_SSP_STATUS_DATA_CRC_ERR__##e)
#define BFM_SSP_STATUS_DATA_CRC_ERR_V(v)        BM_SSP_STATUS_DATA_CRC_ERR
#define BP_SSP_STATUS_TIMEOUT                   12
#define BM_SSP_STATUS_TIMEOUT                   0x1000
#define BF_SSP_STATUS_TIMEOUT(v)                (((v) & 0x1) << 12)
#define BFM_SSP_STATUS_TIMEOUT(v)               BM_SSP_STATUS_TIMEOUT
#define BF_SSP_STATUS_TIMEOUT_V(e)              BF_SSP_STATUS_TIMEOUT(BV_SSP_STATUS_TIMEOUT__##e)
#define BFM_SSP_STATUS_TIMEOUT_V(v)             BM_SSP_STATUS_TIMEOUT
#define BP_SSP_STATUS_RECV_TIMEOUT_STAT         11
#define BM_SSP_STATUS_RECV_TIMEOUT_STAT         0x800
#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)      (((v) & 0x1) << 11)
#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT(v)     BM_SSP_STATUS_RECV_TIMEOUT_STAT
#define BF_SSP_STATUS_RECV_TIMEOUT_STAT_V(e)    BF_SSP_STATUS_RECV_TIMEOUT_STAT(BV_SSP_STATUS_RECV_TIMEOUT_STAT__##e)
#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT_V(v)   BM_SSP_STATUS_RECV_TIMEOUT_STAT
#define BP_SSP_STATUS_RECV_DATA_STAT            10
#define BM_SSP_STATUS_RECV_DATA_STAT            0x400
#define BF_SSP_STATUS_RECV_DATA_STAT(v)         (((v) & 0x1) << 10)
#define BFM_SSP_STATUS_RECV_DATA_STAT(v)        BM_SSP_STATUS_RECV_DATA_STAT
#define BF_SSP_STATUS_RECV_DATA_STAT_V(e)       BF_SSP_STATUS_RECV_DATA_STAT(BV_SSP_STATUS_RECV_DATA_STAT__##e)
#define BFM_SSP_STATUS_RECV_DATA_STAT_V(v)      BM_SSP_STATUS_RECV_DATA_STAT
#define BP_SSP_STATUS_RECV_OVRFLW               9
#define BM_SSP_STATUS_RECV_OVRFLW               0x200
#define BF_SSP_STATUS_RECV_OVRFLW(v)            (((v) & 0x1) << 9)
#define BFM_SSP_STATUS_RECV_OVRFLW(v)           BM_SSP_STATUS_RECV_OVRFLW
#define BF_SSP_STATUS_RECV_OVRFLW_V(e)          BF_SSP_STATUS_RECV_OVRFLW(BV_SSP_STATUS_RECV_OVRFLW__##e)
#define BFM_SSP_STATUS_RECV_OVRFLW_V(v)         BM_SSP_STATUS_RECV_OVRFLW
#define BP_SSP_STATUS_RECV_FULL                 8
#define BM_SSP_STATUS_RECV_FULL                 0x100
#define BF_SSP_STATUS_RECV_FULL(v)              (((v) & 0x1) << 8)
#define BFM_SSP_STATUS_RECV_FULL(v)             BM_SSP_STATUS_RECV_FULL
#define BF_SSP_STATUS_RECV_FULL_V(e)            BF_SSP_STATUS_RECV_FULL(BV_SSP_STATUS_RECV_FULL__##e)
#define BFM_SSP_STATUS_RECV_FULL_V(v)           BM_SSP_STATUS_RECV_FULL
#define BP_SSP_STATUS_RECV_NOT_EMPTY            7
#define BM_SSP_STATUS_RECV_NOT_EMPTY            0x80
#define BF_SSP_STATUS_RECV_NOT_EMPTY(v)         (((v) & 0x1) << 7)
#define BFM_SSP_STATUS_RECV_NOT_EMPTY(v)        BM_SSP_STATUS_RECV_NOT_EMPTY
#define BF_SSP_STATUS_RECV_NOT_EMPTY_V(e)       BF_SSP_STATUS_RECV_NOT_EMPTY(BV_SSP_STATUS_RECV_NOT_EMPTY__##e)
#define BFM_SSP_STATUS_RECV_NOT_EMPTY_V(v)      BM_SSP_STATUS_RECV_NOT_EMPTY
#define BP_SSP_STATUS_XMIT_NOT_FULL             6
#define BM_SSP_STATUS_XMIT_NOT_FULL             0x40
#define BF_SSP_STATUS_XMIT_NOT_FULL(v)          (((v) & 0x1) << 6)
#define BFM_SSP_STATUS_XMIT_NOT_FULL(v)         BM_SSP_STATUS_XMIT_NOT_FULL
#define BF_SSP_STATUS_XMIT_NOT_FULL_V(e)        BF_SSP_STATUS_XMIT_NOT_FULL(BV_SSP_STATUS_XMIT_NOT_FULL__##e)
#define BFM_SSP_STATUS_XMIT_NOT_FULL_V(v)       BM_SSP_STATUS_XMIT_NOT_FULL
#define BP_SSP_STATUS_XMIT_EMPTY                5
#define BM_SSP_STATUS_XMIT_EMPTY                0x20
#define BF_SSP_STATUS_XMIT_EMPTY(v)             (((v) & 0x1) << 5)
#define BFM_SSP_STATUS_XMIT_EMPTY(v)            BM_SSP_STATUS_XMIT_EMPTY
#define BF_SSP_STATUS_XMIT_EMPTY_V(e)           BF_SSP_STATUS_XMIT_EMPTY(BV_SSP_STATUS_XMIT_EMPTY__##e)
#define BFM_SSP_STATUS_XMIT_EMPTY_V(v)          BM_SSP_STATUS_XMIT_EMPTY
#define BP_SSP_STATUS_XMIT_UNDRFLW              4
#define BM_SSP_STATUS_XMIT_UNDRFLW              0x10
#define BF_SSP_STATUS_XMIT_UNDRFLW(v)           (((v) & 0x1) << 4)
#define BFM_SSP_STATUS_XMIT_UNDRFLW(v)          BM_SSP_STATUS_XMIT_UNDRFLW
#define BF_SSP_STATUS_XMIT_UNDRFLW_V(e)         BF_SSP_STATUS_XMIT_UNDRFLW(BV_SSP_STATUS_XMIT_UNDRFLW__##e)
#define BFM_SSP_STATUS_XMIT_UNDRFLW_V(v)        BM_SSP_STATUS_XMIT_UNDRFLW
#define BP_SSP_STATUS_CMD_BUSY                  3
#define BM_SSP_STATUS_CMD_BUSY                  0x8
#define BF_SSP_STATUS_CMD_BUSY(v)               (((v) & 0x1) << 3)
#define BFM_SSP_STATUS_CMD_BUSY(v)              BM_SSP_STATUS_CMD_BUSY
#define BF_SSP_STATUS_CMD_BUSY_V(e)             BF_SSP_STATUS_CMD_BUSY(BV_SSP_STATUS_CMD_BUSY__##e)
#define BFM_SSP_STATUS_CMD_BUSY_V(v)            BM_SSP_STATUS_CMD_BUSY
#define BP_SSP_STATUS_DATA_BUSY                 2
#define BM_SSP_STATUS_DATA_BUSY                 0x4
#define BF_SSP_STATUS_DATA_BUSY(v)              (((v) & 0x1) << 2)
#define BFM_SSP_STATUS_DATA_BUSY(v)             BM_SSP_STATUS_DATA_BUSY
#define BF_SSP_STATUS_DATA_BUSY_V(e)            BF_SSP_STATUS_DATA_BUSY(BV_SSP_STATUS_DATA_BUSY__##e)
#define BFM_SSP_STATUS_DATA_BUSY_V(v)           BM_SSP_STATUS_DATA_BUSY
#define BP_SSP_STATUS_DATA_XFER                 1
#define BM_SSP_STATUS_DATA_XFER                 0x2
#define BF_SSP_STATUS_DATA_XFER(v)              (((v) & 0x1) << 1)
#define BFM_SSP_STATUS_DATA_XFER(v)             BM_SSP_STATUS_DATA_XFER
#define BF_SSP_STATUS_DATA_XFER_V(e)            BF_SSP_STATUS_DATA_XFER(BV_SSP_STATUS_DATA_XFER__##e)
#define BFM_SSP_STATUS_DATA_XFER_V(v)           BM_SSP_STATUS_DATA_XFER
#define BP_SSP_STATUS_BUSY                      0
#define BM_SSP_STATUS_BUSY                      0x1
#define BF_SSP_STATUS_BUSY(v)                   (((v) & 0x1) << 0)
#define BFM_SSP_STATUS_BUSY(v)                  BM_SSP_STATUS_BUSY
#define BF_SSP_STATUS_BUSY_V(e)                 BF_SSP_STATUS_BUSY(BV_SSP_STATUS_BUSY__##e)
#define BFM_SSP_STATUS_BUSY_V(v)                BM_SSP_STATUS_BUSY

#define HW_SSP_DEBUG                        HW(SSP_DEBUG)
#define HWA_SSP_DEBUG                       (0x80010000 + 0x100)
#define HWT_SSP_DEBUG                       HWIO_32_RW
#define HWN_SSP_DEBUG                       SSP_DEBUG
#define HWI_SSP_DEBUG                       
#define BP_SSP_DEBUG_DATACRC_ERR            28
#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) & 0xf) << 28)
#define BFM_SSP_DEBUG_DATACRC_ERR(v)        BM_SSP_DEBUG_DATACRC_ERR
#define BF_SSP_DEBUG_DATACRC_ERR_V(e)       BF_SSP_DEBUG_DATACRC_ERR(BV_SSP_DEBUG_DATACRC_ERR__##e)
#define BFM_SSP_DEBUG_DATACRC_ERR_V(v)      BM_SSP_DEBUG_DATACRC_ERR
#define BP_SSP_DEBUG_DATA_STALL             27
#define BM_SSP_DEBUG_DATA_STALL             0x8000000
#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) & 0x1) << 27)
#define BFM_SSP_DEBUG_DATA_STALL(v)         BM_SSP_DEBUG_DATA_STALL
#define BF_SSP_DEBUG_DATA_STALL_V(e)        BF_SSP_DEBUG_DATA_STALL(BV_SSP_DEBUG_DATA_STALL__##e)
#define BFM_SSP_DEBUG_DATA_STALL_V(v)       BM_SSP_DEBUG_DATA_STALL
#define BP_SSP_DEBUG_DAT_SM                 24
#define BM_SSP_DEBUG_DAT_SM                 0x7000000
#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
#define BV_SSP_DEBUG_DAT_SM__DSM_START      0x1
#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
#define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY      0x6
#define BF_SSP_DEBUG_DAT_SM(v)              (((v) & 0x7) << 24)
#define BFM_SSP_DEBUG_DAT_SM(v)             BM_SSP_DEBUG_DAT_SM
#define BF_SSP_DEBUG_DAT_SM_V(e)            BF_SSP_DEBUG_DAT_SM(BV_SSP_DEBUG_DAT_SM__##e)
#define BFM_SSP_DEBUG_DAT_SM_V(v)           BM_SSP_DEBUG_DAT_SM
#define BP_SSP_DEBUG_MSTK_SM                20
#define BM_SSP_DEBUG_MSTK_SM                0xf00000
#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xb
#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) & 0xf) << 20)
#define BFM_SSP_DEBUG_MSTK_SM(v)            BM_SSP_DEBUG_MSTK_SM
#define BF_SSP_DEBUG_MSTK_SM_V(e)           BF_SSP_DEBUG_MSTK_SM(BV_SSP_DEBUG_MSTK_SM__##e)
#define BFM_SSP_DEBUG_MSTK_SM_V(v)          BM_SSP_DEBUG_MSTK_SM
#define BP_SSP_DEBUG_CMD_OE                 19
#define BM_SSP_DEBUG_CMD_OE                 0x80000
#define BF_SSP_DEBUG_CMD_OE(v)              (((v) & 0x1) << 19)
#define BFM_SSP_DEBUG_CMD_OE(v)             BM_SSP_DEBUG_CMD_OE
#define BF_SSP_DEBUG_CMD_OE_V(e)            BF_SSP_DEBUG_CMD_OE(BV_SSP_DEBUG_CMD_OE__##e)
#define BFM_SSP_DEBUG_CMD_OE_V(v)           BM_SSP_DEBUG_CMD_OE
#define BP_SSP_DEBUG_CMD_SM                 16
#define BM_SSP_DEBUG_CMD_SM                 0x70000
#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
#define BF_SSP_DEBUG_CMD_SM(v)              (((v) & 0x7) << 16)
#define BFM_SSP_DEBUG_CMD_SM(v)             BM_SSP_DEBUG_CMD_SM
#define BF_SSP_DEBUG_CMD_SM_V(e)            BF_SSP_DEBUG_CMD_SM(BV_SSP_DEBUG_CMD_SM__##e)
#define BFM_SSP_DEBUG_CMD_SM_V(v)           BM_SSP_DEBUG_CMD_SM
#define BP_SSP_DEBUG_CLK_OE                 15
#define BM_SSP_DEBUG_CLK_OE                 0x8000
#define BF_SSP_DEBUG_CLK_OE(v)              (((v) & 0x1) << 15)
#define BFM_SSP_DEBUG_CLK_OE(v)             BM_SSP_DEBUG_CLK_OE
#define BF_SSP_DEBUG_CLK_OE_V(e)            BF_SSP_DEBUG_CLK_OE(BV_SSP_DEBUG_CLK_OE__##e)
#define BFM_SSP_DEBUG_CLK_OE_V(v)           BM_SSP_DEBUG_CLK_OE
#define BP_SSP_DEBUG_MMC_SM                 12
#define BM_SSP_DEBUG_MMC_SM                 0x7000
#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
#define BF_SSP_DEBUG_MMC_SM(v)              (((v) & 0x7) << 12)
#define BFM_SSP_DEBUG_MMC_SM(v)             BM_SSP_DEBUG_MMC_SM
#define BF_SSP_DEBUG_MMC_SM_V(e)            BF_SSP_DEBUG_MMC_SM(BV_SSP_DEBUG_MMC_SM__##e)
#define BFM_SSP_DEBUG_MMC_SM_V(v)           BM_SSP_DEBUG_MMC_SM
#define BP_SSP_DEBUG_DAT0_OE                11
#define BM_SSP_DEBUG_DAT0_OE                0x800
#define BF_SSP_DEBUG_DAT0_OE(v)             (((v) & 0x1) << 11)
#define BFM_SSP_DEBUG_DAT0_OE(v)            BM_SSP_DEBUG_DAT0_OE
#define BF_SSP_DEBUG_DAT0_OE_V(e)           BF_SSP_DEBUG_DAT0_OE(BV_SSP_DEBUG_DAT0_OE__##e)
#define BFM_SSP_DEBUG_DAT0_OE_V(v)          BM_SSP_DEBUG_DAT0_OE
#define BP_SSP_DEBUG_DAT321_OE              10
#define BM_SSP_DEBUG_DAT321_OE              0x400
#define BF_SSP_DEBUG_DAT321_OE(v)           (((v) & 0x1) << 10)
#define BFM_SSP_DEBUG_DAT321_OE(v)          BM_SSP_DEBUG_DAT321_OE
#define BF_SSP_DEBUG_DAT321_OE_V(e)         BF_SSP_DEBUG_DAT321_OE(BV_SSP_DEBUG_DAT321_OE__##e)
#define BFM_SSP_DEBUG_DAT321_OE_V(v)        BM_SSP_DEBUG_DAT321_OE
#define BP_SSP_DEBUG_SSP_CMD                9
#define BM_SSP_DEBUG_SSP_CMD                0x200
#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) & 0x1) << 9)
#define BFM_SSP_DEBUG_SSP_CMD(v)            BM_SSP_DEBUG_SSP_CMD
#define BF_SSP_DEBUG_SSP_CMD_V(e)           BF_SSP_DEBUG_SSP_CMD(BV_SSP_DEBUG_SSP_CMD__##e)
#define BFM_SSP_DEBUG_SSP_CMD_V(v)          BM_SSP_DEBUG_SSP_CMD
#define BP_SSP_DEBUG_SSP_RESP               8
#define BM_SSP_DEBUG_SSP_RESP               0x100
#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) & 0x1) << 8)
#define BFM_SSP_DEBUG_SSP_RESP(v)           BM_SSP_DEBUG_SSP_RESP
#define BF_SSP_DEBUG_SSP_RESP_V(e)          BF_SSP_DEBUG_SSP_RESP(BV_SSP_DEBUG_SSP_RESP__##e)
#define BFM_SSP_DEBUG_SSP_RESP_V(v)         BM_SSP_DEBUG_SSP_RESP
#define BP_SSP_DEBUG_SSP_TXD                4
#define BM_SSP_DEBUG_SSP_TXD                0xf0
#define BF_SSP_DEBUG_SSP_TXD(v)             (((v) & 0xf) << 4)
#define BFM_SSP_DEBUG_SSP_TXD(v)            BM_SSP_DEBUG_SSP_TXD
#define BF_SSP_DEBUG_SSP_TXD_V(e)           BF_SSP_DEBUG_SSP_TXD(BV_SSP_DEBUG_SSP_TXD__##e)
#define BFM_SSP_DEBUG_SSP_TXD_V(v)          BM_SSP_DEBUG_SSP_TXD
#define BP_SSP_DEBUG_SSP_RXD                0
#define BM_SSP_DEBUG_SSP_RXD                0xf
#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) & 0xf) << 0)
#define BFM_SSP_DEBUG_SSP_RXD(v)            BM_SSP_DEBUG_SSP_RXD
#define BF_SSP_DEBUG_SSP_RXD_V(e)           BF_SSP_DEBUG_SSP_RXD(BV_SSP_DEBUG_SSP_RXD__##e)
#define BFM_SSP_DEBUG_SSP_RXD_V(v)          BM_SSP_DEBUG_SSP_RXD

#endif /* __HEADERGEN_STMP3600_SSP_H__*/
