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f965eda041
* ARMv8-M: Add SMP support to CM33 NTZ non-MPU port * Enable SMP for Arm Cortex-M33 NTZ port for GCC, ArmClang, and IAR toolchains. * Add per-core scheduler/port state: critical nesting. * Introduce spinlocks and inter-core yield/wakeup (SEV/WFE) plus primary/secondary core bring-up sync. * Update PendSV (i.e., context switch assembly) for core-safe preemption and restore paths. * Extend port macros/hooks for SMP in portmacrocommon.h, single-core builds remain unchanged. * Add the SMP boot sequence along with the necessary steps to enable SMP on Armv8-M based ports. This should help developers understand the requirements and process for enabling SMP on their Armv8-M based applications. * Update the kernel checker script to accept comma separated years in the copyright header. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * Armv8-M: Copy SMP changes to all Armv8-M based ports This commit executes the `copy_files.py` python script to copy the changes applied in the previous commit (i.e., SMP changes) to all the Armv8-M based ports. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> --------- Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
62 lines
4 KiB
Text
62 lines
4 KiB
Text
This directory tree contains the master copy of the FreeRTOS Armv8-M and
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Armv8.1-M ports.
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Do not use the files located here! These files are copied into separate
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FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories
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prior to each FreeRTOS release.
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If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
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FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories.
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If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
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the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories.
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Note:
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The Armv8-M ports support SMP (multicore) systems when both MPU and TrustZone are disabled.
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However, this has only been validated on Arm Cortex-M33 Non-TrustZone Non-MPU port.
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SMP Boot Sequence
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---------------------------------------
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Primary core flow:
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1. Perform core-specific and shared initialization (e.g., zero-initialize `.bss`).
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2. Jump to `main()`, create user tasks, optionally pin tasks to specific cores.
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3. Call `vTaskStartScheduler()` which invokes `xPortStartScheduler()`.
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4. `xPortStartScheduler()` configures the primary core tick timer and signals secondary cores that shared init is complete using the `ucPrimaryCoreInitDoneFlag` variable.
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5. Call the application-defined `configWAKE_SECONDARY_CORES` function.
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6. Wait until all secondary cores report as brought up.
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7. Once all cores are up, call `vStartFirstTask()` to schedule the first task on the primary core.
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Secondary core flow:
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1. Perform core-specific initialization.
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2. Wait until the primary core signals that shared initialization has completed (that is, `ucPrimaryCoreInitDoneFlag` is set to 1). Once this occurs,
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the application-defined `configWAKE_SECONDARY_CORES` function is invoked by the primary core to carry out the subsequent steps.
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3. Program the inter-processor signaling mechanism (e.g., Arm Doorbell Mechanism) to be used by the kernel to interrupt that core and request that it perform a context switch.
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4. Call `vPortConfigureInterruptPriorities` function to setup per core interrupt priorities.
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5. If Pointer Authentication (PAC) or Branch Target Identification (BTI) is supported, call `vConfigurePACBTI` with `pdTRUE` as the input parameter to configure the per-core special-purpose CONTROL register
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with the appropriate PACBTI settings.
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6. Signal the primary that this secondary is online and ready by setting its flag in the `ucSecondaryCoresReadyFlags` array.
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7. Issue an SVC with immediate value `102` (portSVC_START_SCHEDULER), which will call `vRestoreContextOfFirstTask()` to start scheduling on this core.
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Inter-core notification
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---------------------------------------
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On SMP systems the application must provide an implementation of the `vInterruptCore( uint8_t ucCoreID )` function. The kernel calls this function
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to interrupt another core and request that it perform a context switch (e.g., when a higher-priority task becomes ready on that core).
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Typical platform implementation: write a doorbell flag/bit or other inter-processor signaling register targeting `ucCoreID`. This should cause a
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"doorbell" (or equivalent) IRQ on the secondary core. In the secondary core’s doorbell IRQ handler, check the reason for the interrupt and, if it is a
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schedule request, trigger a context switch (i.e., by calling `portYIELD_FROM_ISR`).
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Notes:
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* `vInterruptCore` is declared weak in the port so that platforms can override it. If your hardware lacks a dedicated doorbell, use any available
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inter-core interrupt/messaging mechanism to achieve the same effect.
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* The application must define `configCORE_ID_REGISTER`, usually in `FreeRTOSConfig.h` to the memory-mapped address of the platform register used
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to read the current core ID. The port reads this register to determine the executing core and to index per-core scheduler state.
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* The application must define `configWAKE_SECONDARY_CORES`, usually in `FreeRTOSConfig.h`, to point to the application/platform-specific function
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that wakes up and make the secondary cores ready after the primary core completes initialisation.
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