mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
ebbe2cf854
Critical sections in FreeRTOS are implemented using the following two
functions:
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
}
void vPortExitCritical( void )
{
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
uxCriticalNesting is initialized to a large value at the start and set
to zero when the scheduler is started (xPortStartScheduler). As a
result, before the scheduler is started, a pair of enter/exit critical
section will leave the interrupts disabled because uxCriticalNesting
will not reach zero in the vPortExitCritical function. This is done to
ensure that the interrupts remain disabled from the time first FreeRTOS
API is called to the time when the scheduler is started. The scheduler
starting code is expected to enure that interrupts are enabled before
the first task starts executing.
Cortex-M33 ports were not enabling interrupts before starting the first
task and as a result, the first task was started with interrupts
disabled. This PR fixes the issue by ensuring that interrupts are
enabled before the first task is started.
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
346 lines
16 KiB
ArmAsm
346 lines
16 KiB
ArmAsm
/*
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* FreeRTOS Kernel V10.4.1
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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/* Including FreeRTOSConfig.h here will cause build errors if the header file
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contains code not understood by the assembler - for example the 'extern' keyword.
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To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include "FreeRTOSConfig.h"
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EXTERN pxCurrentTCB
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EXTERN xSecureContext
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EXTERN vTaskSwitchContext
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EXTERN vPortSVCHandler_C
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EXTERN SecureContext_SaveContext
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EXTERN SecureContext_LoadContext
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PUBLIC xIsPrivileged
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PUBLIC vResetPrivilege
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PUBLIC vPortAllocateSecureContext
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PUBLIC vRestoreContextOfFirstTask
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PUBLIC vRaisePrivilege
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PUBLIC vStartFirstTask
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PUBLIC ulSetInterruptMask
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PUBLIC vClearInterruptMask
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PUBLIC PendSV_Handler
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PUBLIC SVC_Handler
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PUBLIC vPortFreeSecureContext
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/*-----------------------------------------------------------*/
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/*---------------- Unprivileged Functions -------------------*/
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/*-----------------------------------------------------------*/
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SECTION .text:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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xIsPrivileged:
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mrs r0, control /* r0 = CONTROL. */
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tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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ite ne
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movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vResetPrivilege:
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mrs r0, control /* r0 = CONTROL. */
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orr r0, r0, #1 /* r0 = r0 | 1. */
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msr control, r0 /* CONTROL = r0. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vPortAllocateSecureContext:
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svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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/*----------------- Privileged Functions --------------------*/
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/*-----------------------------------------------------------*/
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SECTION privileged_functions:CODE:NOROOT(2)
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THUMB
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/*-----------------------------------------------------------*/
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vRestoreContextOfFirstTask:
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r3, [r2] /* Read pxCurrentTCB. */
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ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r4, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r4, #4 /* r4 = 4. */
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str r4, [r2] /* Program RNR = 4. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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#if ( configENABLE_MPU == 1 )
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ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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ldr r5, =xSecureContext
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str r1, [r5] /* Set xSecureContext to this task's value for the same. */
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msr psplim, r2 /* Set this task's PSPLIM value. */
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msr control, r3 /* Set this task's CONTROL value. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r4 /* Finally, branch to EXC_RETURN. */
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#else /* configENABLE_MPU */
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ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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ldr r4, =xSecureContext
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str r1, [r4] /* Set xSecureContext to this task's value for the same. */
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msr psplim, r2 /* Set this task's PSPLIM value. */
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movs r1, #2 /* r1 = 2. */
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msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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adds r0, #32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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isb
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mov r0, #0
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msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
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bx r3 /* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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/*-----------------------------------------------------------*/
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vRaisePrivilege:
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mrs r0, control /* Read the CONTROL register. */
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bic r0, r0, #1 /* Clear the bit 0. */
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msr control, r0 /* Write back the new CONTROL value. */
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bx lr /* Return to the caller. */
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/*-----------------------------------------------------------*/
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vStartFirstTask:
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ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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msr msp, r0 /* Set the MSP back to the start of the stack. */
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cpsie i /* Globally enable interrupts. */
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cpsie f
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dsb
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isb
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svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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/*-----------------------------------------------------------*/
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ulSetInterruptMask:
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mrs r0, basepri /* r0 = basepri. Return original basepri value. */
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mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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vClearInterruptMask:
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msr basepri, r0 /* basepri = ulMask. */
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dsb
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isb
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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PendSV_Handler:
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mrs r1, psp /* Read PSP in r1. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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cbz r0, save_ns_context /* No secure context to save. */
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push {r0-r2, r14}
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bl SecureContext_SaveContext
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pop {r0-r3} /* LR is now in r3. */
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mov lr, r3 /* LR = r3. */
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lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r2, [r3] /* Read pxCurrentTCB. */
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#if ( configENABLE_MPU == 1 )
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subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mrs r3, control /* r3 = CONTROL. */
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mov r4, lr /* r4 = LR/EXC_RETURN. */
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stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
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#endif /* configENABLE_MPU */
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b select_next_task
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save_ns_context:
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ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r2, [r3] /* Read pxCurrentTCB. */
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#if ( configENABLE_FPU == 1 )
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tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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it eq
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vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
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#endif /* configENABLE_FPU */
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#if ( configENABLE_MPU == 1 )
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subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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adds r1, r1, #16 /* r1 = r1 + 16. */
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stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mrs r3, control /* r3 = CONTROL. */
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mov r4, lr /* r4 = LR/EXC_RETURN. */
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subs r1, r1, #16 /* r1 = r1 - 16. */
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stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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str r1, [r2] /* Save the new top of stack in TCB. */
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adds r1, r1, #12 /* r1 = r1 + 12. */
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stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
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mrs r2, psplim /* r2 = PSPLIM. */
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mov r3, lr /* r3 = LR/EXC_RETURN. */
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subs r1, r1, #12 /* r1 = r1 - 12. */
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stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
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#endif /* configENABLE_MPU */
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select_next_task:
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mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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dsb
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isb
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bl vTaskSwitchContext
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mov r0, #0 /* r0 = 0. */
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msr basepri, r0 /* Enable interrupts. */
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ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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ldr r3, [r2] /* Read pxCurrentTCB. */
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ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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#if ( configENABLE_MPU == 1 )
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dmb /* Complete outstanding transfers before disabling MPU. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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str r4, [r2] /* Disable MPU. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
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ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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str r4, [r2] /* Program MAIR0. */
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ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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movs r4, #4 /* r4 = 4. */
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str r4, [r2] /* Program RNR = 4. */
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adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
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ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
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stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
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ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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ldr r4, [r2] /* Read the value of MPU_CTRL. */
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orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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str r4, [r2] /* Enable MPU. */
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dsb /* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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#if ( configENABLE_MPU == 1 )
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ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
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msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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msr control, r3 /* Restore the CONTROL register value for the task. */
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mov lr, r4 /* LR = r4. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r2] /* Restore the task's xSecureContext. */
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cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
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push {r1,r4}
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bl SecureContext_LoadContext /* Restore the secure context. */
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pop {r1,r4}
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mov lr, r4 /* LR = r4. */
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lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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msr psp, r1 /* Remember the new top of stack for the task. */
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bx lr
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#else /* configENABLE_MPU */
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ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
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msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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mov lr, r3 /* LR = r3. */
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ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
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str r0, [r2] /* Restore the task's xSecureContext. */
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cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
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push {r1,r3}
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bl SecureContext_LoadContext /* Restore the secure context. */
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pop {r1,r3}
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mov lr, r3 /* LR = r3. */
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lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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msr psp, r1 /* Remember the new top of stack for the task. */
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bx lr
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#endif /* configENABLE_MPU */
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restore_ns_context:
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ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */
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#if ( configENABLE_FPU == 1 )
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tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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it eq
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vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
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#endif /* configENABLE_FPU */
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msr psp, r1 /* Remember the new top of stack for the task. */
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bx lr
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/*-----------------------------------------------------------*/
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SVC_Handler:
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tst lr, #4
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ite eq
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mrseq r0, msp
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mrsne r0, psp
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b vPortSVCHandler_C
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/*-----------------------------------------------------------*/
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vPortFreeSecureContext:
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/* r0 = uint32_t *pulTCB. */
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ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
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ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
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cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
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it ne
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svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
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bx lr /* Return. */
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/*-----------------------------------------------------------*/
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END
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