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Add Vectored Interrupt Support To SiFive RISC-V Demo (#871) 
Update SiFive IAR demo to support vectored interrupts. This is a near copy of https://github.com/FreeRTOS/FreeRTOS/pull/797.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-11-09 10:34:04 -08:00
..
Demo Add Vectored Interrupt Support To SiFive RISC-V Demo (#871) 2022-11-09 10:34:04 -08:00
Source Percepio Trace Recorder v4.6.0 (#789) 2022-11-03 13:58:38 -07:00
Test Set and update submodule pointer correctly. 2022-10-19 15:18:21 -07:00
ThirdParty Apply release changes to main branch (#759) 2021-12-23 10:16:27 -08:00
readme.txt Update version numbers to V7.4.1. 2013-04-18 12:58:17 +00:00

readme.txt 

Directories:

+ The FreeRTOS-Plus/Source directory contains source code for some of the
  FreeRTOS+ components.  These subdirectories contain further readme files and
  links to documentation.

+ The FreeRTOS-Plus/Demo directory contains a demo application for every most of
  the FreeRTOS+ components.  Lots of the demo applications use the FreeRTOS
  Windows simulator for easy evaluation.  Be aware that FreeRTOS is much slower
  and not deterministic when executed in a simulated environment.

+ See http://www.freertos.org/plus