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114 lines
4 KiB
C
114 lines
4 KiB
C
/*
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FreeRTOS.org V4.3.1 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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with commercial development and support options.
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***************************************************************************
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*/
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/*
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Changes from V3.2.4
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+ Also read the EMAC_RSR register in the EMAC ISR as a work around the
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the EMAC bug that can reset the RX bit in EMAC_ISR register before the
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bit has been read.
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Changes from V4.0.1
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+ Only check the interrupt status register to see if an EMAC Tx interrupt
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has occurred. Previously the TSR register was also inspected.
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*/
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#include "FreeRTOS.h"
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#include "task.h"
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#include "semphr.h"
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#include "SAM7_EMAC.h"
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#include "AT91SAM7X256.h"
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/*-----------------------------------------------------------*/
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/* The semaphore used to signal the arrival of new data to the interface
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task. */
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static xSemaphoreHandle xSemaphore = NULL;
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void vEMACISR( void ) __attribute__((naked));
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/*-----------------------------------------------------------*/
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/*
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* The EMAC ISR. Handles both Tx and Rx complete interrupts.
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*/
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void vEMACISR( void )
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{
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/* This ISR can cause a context switch, so the first statement must be a
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call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
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variable declarations. */
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portENTER_SWITCHING_ISR();
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/* Variable definitions can be made now. */
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volatile unsigned portLONG ulIntStatus, ulEventStatus;
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portBASE_TYPE xSwitchRequired = pdFALSE;
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extern void vClearEMACTxBuffer( void );
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/* Find the cause of the interrupt. */
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ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
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ulEventStatus = AT91C_BASE_EMAC->EMAC_RSR;
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if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulEventStatus & AT91C_EMAC_REC ) )
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{
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/* A frame has been received, signal the lwIP task so it can process
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the Rx descriptors. */
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xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
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AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
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}
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if( ulIntStatus & AT91C_EMAC_TCOMP )
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{
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/* A frame has been transmitted. Mark all the buffers used by the
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frame just transmitted as free again. */
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vClearEMACTxBuffer();
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AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
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}
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/* Clear the interrupt. */
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AT91C_BASE_AIC->AIC_EOICR = 0;
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/* If a task was woken by either a frame being received then we may need to
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switch to another task. */
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portEXIT_SWITCHING_ISR( xSwitchRequired );
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}
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/*-----------------------------------------------------------*/
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void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )
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{
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/* Simply store the semaphore that should be used by the ISR. */
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xSemaphore = xCreatedSemaphore;
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}
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