mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-27 17:02:06 -04:00
145 lines
5.2 KiB
INI
145 lines
5.2 KiB
INI
// 186.cfg
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// You must select RAM, ROM for your controller 04-26-2000
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// Your TERN controller is installed with SRAM and ROM with different sizes.
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// For debug, 128K or 512K SRAM can be selected
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// For build a ROM, you need to select the ROM size.
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// How to select ?
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// 1) commend out the unwanted #define RAM size line with "//"
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// 2) delete the "//" preceding the wanted #define RAM size line
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//
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// #define RAM 32 // 32KB SRAM installed
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#define RAM 128 // 128KB SRAM installed
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// #define RAM 512 // 512KB SRAM installed
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// #define ROM 32 // Use 32KB ROM chip 27C256-70
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#define ROM 64 // Use 64KB ROM chip 27C512-70
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// #define ROM 128 // Use 128KB ROM chip 27C010-70
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// #define ROM 256 // Use 256KB ROM chip 27C020-70
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// #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board
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cputype Am186ES // AMD188/6 based controllers
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#if defined(__PDREMOTE__)
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#if RAM == 32
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map 0x00000 to 0x00fff as reserved // interrupt vector table
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map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM)
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map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM)
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map 0x08000 to 0xfffff as reserved // No access allowed
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#define CODE_START 0x0400 // Start of application code, STEP2 !
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#elif RAM == 128
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map 0x00000 to 0x00fff as reserved // interrupt vector table
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map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
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map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM)
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map 0x20000 to 0xfffff as reserved // No access allowed
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#define CODE_START 0x0800 // Start of application code
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#elif RAM == 512
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map 0x00000 to 0x00fff as reserved // interrupt vector table
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map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
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map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM)
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map 0x80000 to 0xfffff as reserved // No access allowed
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#define CODE_START 0x0800 // Start of application code
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#endif
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#define DATA_START 0x0100 // Start of application data
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#define BOOT_START 0x1fc0 // Start of initialization code
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#else
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#if ROM == 32
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map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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map 0x20000 to 0xf7fff as reserved // No access
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map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space
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#define CODE_START 0xF800 // Start of application code
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#elif ROM == 64
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map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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map 0x20000 to 0xEffff as reserved // No access
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map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space
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#define CODE_START 0xF000 // Start of application code
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#elif ROM == 128
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map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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map 0x20000 to 0xDffff as reserved // No access
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map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space
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#define CODE_START 0xE000 // Start of application code
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#elif ROM == 256
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map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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map 0x20000 to 0xBffff as reserved // No access
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map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space
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#define CODE_START 0xC000 // Start of application code
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#elif ROM == 512
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map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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map 0x20000 to 0x7ffff as reserved // No access
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map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space
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#define CODE_START 0x8000 // Start of application code
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#endif
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#define DATA_START 0x0040 // Start of application data
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#define BOOT_START 0xffc0 // Start of initialization code
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initcode reset \ // Reset vector to program entry point
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umcs = 0x80bf \ // 512K ROM, 3 wait states
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lmcs = 0x7fbf \ // 512K RAM, 3 wait states
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mpcs = 0xa0bf \
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mmcs = 0x81ff \
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pacs = 0x007f
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class ??LOCATE = BOOT_START // Chip select initialization
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output ??LOCATE
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#if ROM == 32 // 27C256-90 EPROM or FLASH
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hexfile binary offset=0xf8000 size=32 // for 27C256, bin file
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#elif ROM == 64 // 27C512-90 EPROM or FLASH
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hexfile binary offset=0xF0000 size=64 // for 27C512
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#elif ROM == 128 // 27C010-90 EPROM or FLASH
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hexfile binary offset=0xE0000 size=128 // for 27C010
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#elif ROM == 256 // 27C020-90 EPROM or FLASH
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hexfile binary offset=0xC0000 size=256 // for 27C020
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#elif ROM == 512 // 27C040-90 EPROM or FLASH
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hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file
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#endif
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#endif
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//
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// Start of common configuration file settings.
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//
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absfile axe86 // Paradigm C++ debugging output
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listfile segments // Absolute segment map
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dup DATA ROMDATA // Make a copy of initialized data
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dup FAR_DATA ROMFARDATA // Make a copy of far initialized data
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#if defined(__COMPFARDATA__) // Compress and display results
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compress ROMFARDATA
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display compression
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#endif
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class CODE = CODE_START // Application code
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class DATA = DATA_START // Application data
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order DATA \ // RAM class organization
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BSS \
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NVRAM \
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EDATA \
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STACK \
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FAR_DATA ENDFAR_DATA \
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FAR_BSS ENDFAR_BSS \
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FAR_HEAP ENDFAR_HEAP
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order CODE \ // EPROM class organization
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INITDATA EXITDATA \
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FAR_CONST ENDFAR_CONST \
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ROMDATA ENDROMDATA \
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ROMFARDATA ENDROMFARDATA
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output CODE \ // Classes in the output file(s)
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INITDATA EXITDATA \
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FAR_CONST ENDFAR_CONST \
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ROMDATA ENDROMDATA \
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ROMFARDATA ENDROMFARDATA
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