mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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161 lines
3.5 KiB
ArmAsm
161 lines
3.5 KiB
ArmAsm
/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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* @file entry.S
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* @author Microsemi SoC Products Group
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* @brief Mi-V soft processor vectors, trap handling and startup code.
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*
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* SVN $Revision: 9947 $
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* SVN $Date: 2018-04-30 20:28:49 +0530 (Mon, 30 Apr 2018) $
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*/
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#ifndef ENTRY_S
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#define ENTRY_S
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#include "encoding.h"
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#if __riscv_xlen == 64
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# define LREG ld
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# define SREG sd
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# define REGBYTES 8
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#else
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# define LREG lw
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# define SREG sw
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# define REGBYTES 4
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#endif
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.section .text.entry
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.globl _start
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_start:
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j handle_reset
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nmi_vector:
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j nmi_vector
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trap_vector:
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j trap_entry
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handle_reset:
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la t0, trap_entry
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csrw mtvec, t0
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csrwi mstatus, 0
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csrwi mie, 0
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/*Floating point support configuration*/
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#ifdef __riscv_flen
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csrr t0, mstatus
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lui t1, 0xffffa
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addi t1, t1, -1
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and t0, t0, t1
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lui t1, 0x4
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or t1, t0, t1
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csrw mstatus, t1
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lui t0, 0x0
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fscsr t0
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#endif
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.option push
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# Ensure the instruction is not optimized, since gp is not yet set
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.option norelax
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# initialize global pointer
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la gp, __global_pointer$
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.option pop
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# initialize stack pointer
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la sp, __stack_top
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# perform the rest of initialization in C
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j _init
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trap_entry:
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addi sp, sp, -32*REGBYTES
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SREG x1, 0 * REGBYTES(sp)
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SREG x2, 1 * REGBYTES(sp)
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SREG x3, 2 * REGBYTES(sp)
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SREG x4, 3 * REGBYTES(sp)
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SREG x5, 4 * REGBYTES(sp)
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SREG x6, 5 * REGBYTES(sp)
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SREG x7, 6 * REGBYTES(sp)
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SREG x8, 7 * REGBYTES(sp)
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SREG x9, 8 * REGBYTES(sp)
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SREG x10, 9 * REGBYTES(sp)
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SREG x11, 10 * REGBYTES(sp)
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SREG x12, 11 * REGBYTES(sp)
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SREG x13, 12 * REGBYTES(sp)
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SREG x14, 13 * REGBYTES(sp)
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SREG x15, 14 * REGBYTES(sp)
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SREG x16, 15 * REGBYTES(sp)
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SREG x17, 16 * REGBYTES(sp)
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SREG x18, 17 * REGBYTES(sp)
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SREG x19, 18 * REGBYTES(sp)
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SREG x20, 19 * REGBYTES(sp)
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SREG x21, 20 * REGBYTES(sp)
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SREG x22, 21 * REGBYTES(sp)
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SREG x23, 22 * REGBYTES(sp)
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SREG x24, 23 * REGBYTES(sp)
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SREG x25, 24 * REGBYTES(sp)
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SREG x26, 25 * REGBYTES(sp)
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SREG x27, 26 * REGBYTES(sp)
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SREG x28, 27 * REGBYTES(sp)
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SREG x29, 28 * REGBYTES(sp)
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SREG x30, 29 * REGBYTES(sp)
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SREG x31, 30 * REGBYTES(sp)
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csrr t0, mepc
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SREG t0, 31 * REGBYTES(sp)
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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jal handle_trap
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csrw mepc, a0
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# Remain in M-mode after mret
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li t0, MSTATUS_MPP
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csrs mstatus, t0
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LREG x1, 0 * REGBYTES(sp)
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LREG x2, 1 * REGBYTES(sp)
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LREG x3, 2 * REGBYTES(sp)
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LREG x4, 3 * REGBYTES(sp)
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LREG x5, 4 * REGBYTES(sp)
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LREG x6, 5 * REGBYTES(sp)
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LREG x7, 6 * REGBYTES(sp)
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LREG x8, 7 * REGBYTES(sp)
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LREG x9, 8 * REGBYTES(sp)
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LREG x10, 9 * REGBYTES(sp)
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LREG x11, 10 * REGBYTES(sp)
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LREG x12, 11 * REGBYTES(sp)
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LREG x13, 12 * REGBYTES(sp)
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LREG x14, 13 * REGBYTES(sp)
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LREG x15, 14 * REGBYTES(sp)
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LREG x16, 15 * REGBYTES(sp)
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LREG x17, 16 * REGBYTES(sp)
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LREG x18, 17 * REGBYTES(sp)
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LREG x19, 18 * REGBYTES(sp)
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LREG x20, 19 * REGBYTES(sp)
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LREG x21, 20 * REGBYTES(sp)
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LREG x22, 21 * REGBYTES(sp)
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LREG x23, 22 * REGBYTES(sp)
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LREG x24, 23 * REGBYTES(sp)
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LREG x25, 24 * REGBYTES(sp)
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LREG x26, 25 * REGBYTES(sp)
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LREG x27, 26 * REGBYTES(sp)
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LREG x28, 27 * REGBYTES(sp)
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LREG x29, 28 * REGBYTES(sp)
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LREG x30, 29 * REGBYTES(sp)
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LREG x31, 30 * REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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#endif
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