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FreeRTOS-Kernel/FreeRTOS/Demo/RISC-V_RV32_QEMU_VIRT_GCC
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e14002270 d60b34c8e2
risc-v: Fix build flags and linker scripts (#906) 
1. miss debug info in assembly code
RISC-V-spike-htif_GCC
        LDFLAGS add arch and abi info for linker
            for riscv64-unknown-elf multilib, if there is no arch and abi
            info, will link to default lib and have below error
            target emulation `elf32-littleriscv' does not match `elf64-littleriscv'
        use CFLAGS to replace ASFLAGS when compile assembly code
            because DEBUG flag is added in CFLAGS, if we use ASFLAGS to compile
            assembly code, there is no debug info in assembly code objfile

2. binutils 2.39 ld warn 'has a LOAD segment with RWX permissions'
RISC-V-Qemu-virt_GCC
RISC-V-spike-htif_GCC
RISC-V_RV32_QEMU_VIRT_GCC

3. fix build fail
RISC-V_RV32_QEMU_VIRT_GCC

Signed-off-by: Eric Chan <e14002270@gmail.com>
2023-05-31 11:48:13 -07:00
..
build/gcc risc-v: Fix build flags and linker scripts (#906) 2023-05-31 11:48:13 -07:00
FreeRTOSConfig.h risc-v: Fix build flags and linker scripts (#906) 2023-05-31 11:48:13 -07:00
main.c [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
main_blinky.c [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
main_full.c [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
ns16550.c [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
ns16550.h [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
Readme.md Update GCC RISC-V QEMU project to support new RISC-V port and vector mode (#780) 2022-02-08 13:58:34 -08:00
riscv-reg.h [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
riscv-virt.c [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
riscv-virt.h [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00
vector.S [AUTO][RELEASE]: Bump file header version to "202212.00" 2022-12-10 01:17:30 +00:00

Readme.md

Emulating generic RISC-V 32bit machine on QEMU

Requirements

  1. GNU RISC-V toolchains (tested on pre-built Sifive GNU Embedded Toolchain — v2020.12.8)
  1. qemu-riscv32-system (tested on pre-built Sifive QEMU — v2020.08.1)
  1. Linux OS (tested on Ubuntu 20.04.3 LTS)

How to build

Add path of toolchain that is described above section, such as:

$ export PATH="/YOUR_PATH/riscv64-unknown-elf/bin:${PATH}"

For release build:

$ make -C build/gcc/

For debug build:

$ make -C build/gcc/ DEBUG=1

To clean build artifacts:

$ make -C build/gcc/ clean

If the build was successful, the RTOSDemo.elf executable will be located in the build/gcc/output directory.

How to run

$ qemu-system-riscv32 -nographic -machine virt -net none \
  -chardev stdio,id=con,mux=on -serial chardev:con \
  -mon chardev=con,mode=readline -bios none \
  -smp 4 -kernel ./build/gcc/output/RTOSDemo.elf

How to debug with gdb

Append -s and -S options to the previous qemu command.

  • -s: enable to attach gdb to QEMU at port 1234
  • -S: start and halted CPU (wait for attach from gdb)

It is recommended to use the 'debug build' so that gdb can automatically map symbols. Run these commands after starting the QEMU with above options:

$ riscv64-unknown-elf-gdb -x build/gcc/gdbinit

Description

This demo just prints Tx/Rx message of queue to serial port, use no other hardware and use only primary core (currently hart 0). Other cores are simply going to wfi state and execute nothing else.