d60b34c8e2
1. miss debug info in assembly code
RISC-V-spike-htif_GCC
LDFLAGS add arch and abi info for linker
for riscv64-unknown-elf multilib, if there is no arch and abi
info, will link to default lib and have below error
target emulation `elf32-littleriscv' does not match `elf64-littleriscv'
use CFLAGS to replace ASFLAGS when compile assembly code
because DEBUG flag is added in CFLAGS, if we use ASFLAGS to compile
assembly code, there is no debug info in assembly code objfile
2. binutils 2.39 ld warn 'has a LOAD segment with RWX permissions'
RISC-V-Qemu-virt_GCC
RISC-V-spike-htif_GCC
RISC-V_RV32_QEMU_VIRT_GCC
3. fix build fail
RISC-V_RV32_QEMU_VIRT_GCC
Signed-off-by: Eric Chan <e14002270@gmail.com>
|
||
|---|---|---|
| .. | ||
| fake_rom.lds | ||
| FreeRTOSConfig.h | ||
| htif.c | ||
| htif.h | ||
| main.c | ||
| main_blinky.c | ||
| Makefile | ||
| README.md | ||
| riscv-reg.h | ||
| riscv-virt.c | ||
| riscv-virt.h | ||
| spike-1.cfg | ||
| start.S | ||
Emulating generic RISC-V 32bit machine on spike
Requirements
- GNU RISC-V toolchains (tested on Crosstool-NG)
- spike from https://github.com/riscv/riscv-isa-sim
- OpenOCD from https://github.com/riscv/riscv-openocd
How to build toolchain
Clone the Crosstool-NG and configure Crosstool-NG.
$ git clone https://github.com/crosstool-ng/crosstool-ng
$ cd crosstool-ng
$ ./bootstrap
$ ./configure --enable-local
$ make
Generate toolchain configuration:
-
For RV32 builds:
Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:
CT_EXPERIMENTAL=y CT_ARCH_RISCV=y CT_ARCH_64=n CT_ARCH_ARCH="rv32ima" CT_ARCH_ABI="ilp32" CT_TARGET_CFLAGS="-mcmodel=medany" CT_TARGET_LDFLAGS="-mcmodel=medany" CT_MULTILIB=y CT_DEBUG_GDB=y -
For RV64 builds: Create a file name as "defconfig" ( should be exactly the same, no file extension ) with the below content:
CT_EXPERIMENTAL=y CT_ARCH_RISCV=y CT_ARCH_64=y CT_ARCH_ARCH="rv64ima" CT_ARCH_ABI="lp64" CT_TARGET_CFLAGS="-mcmodel=medany" CT_TARGET_LDFLAGS="-mcmodel=medany" CT_MULTILIB=y CT_DEBUG_GDB=y
Run the below command. The configurations will be save to .config file.:
./ct-ng defconfig
Build the GNU toolchain for RISC-V.
$ ./ct-ng build
A toolchain is installed at ~/x-tools/riscv32-unknown-elf or ~/x-tools/riscv64-unknown-elf directory depends on your build.
How to build
Add path of toolchain that is described above section.
$ export PATH=~/x-tools/{YOUR_TOOLCHAIN}/bin:$PATH
To build, simply run make. If you want a debug build, pass DEBUG=1. If
you want an RV64 build, pass XLEN=64.
The resulting executable file is ./build/RTOSDemo32.axf or ./build/RTOSDemo64.axf.
How to run
RV32:
$ spike -p1 --isa RV32IMA -m0x80000000:0x10000000 --rbb-port 9824 \
./build/RTOSDemo32.axf
RV64:
$ spike -p1 --isa RV64IMA -m0x80000000:0x10000000 --rbb-port 9824 \
./build/RTOSDemo64.axf
How to debug with gdb
Start OpenOCD in one terminal:
$ openocd -f spike-1.cfg
Start gdb in another:
$ riscv64-unknown-elf-gdb ./build/RTOSDemo.axf
...
(gdb) target extended-remote localhost:3333
...
(gdb) info threads
(As of 3/22/2021 OpenOCD's RISC-V FreeRTOS awareness is still incomplete.)
Description
This demo starts separate transmit and receive threads. The transmit thread sends integers through a queue. Both threads print out what they're sending/receiving using HTIF.