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143 lines
6.3 KiB
C
143 lines
6.3 KiB
C
/*
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* Trace Recorder for Tracealyzer v4.6.0
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* Copyright 2021 Percepio AB
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* www.percepio.com
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* The hardware abstraction layer for the trace recorder.
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*/
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#include <trcRecorder.h>
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#if ( TRC_USE_TRACEALYZER_RECORDER == 1 )
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/* If using DWT timestamping (default on ARM Cortex-M3, M4 and M7), make sure the DWT unit is initialized. */
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#if ( ( TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M ) && ( defined( __CORTEX_M ) && ( __CORTEX_M >= 0x03 ) ) )
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#if ( TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING )
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#ifndef TRC_CFG_ARM_CM_USE_SYSTICK
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void xTraceHardwarePortInitCortexM()
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{
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/* Make sure the DWT registers are unlocked, in case the debugger doesn't do this. */
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TRC_REG_ITM_LOCKACCESS = TRC_ITM_LOCKACCESS_UNLOCK;
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/* Make sure DWT is enabled is enabled, if supported */
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TRC_REG_DEMCR |= TRC_DEMCR_TRCENA;
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do
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{
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/* Verify that DWT is supported */
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if( TRC_REG_DEMCR == 0 )
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{
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/* This function is called on Cortex-M3, M4 and M7 devices to initialize
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* the DWT unit, assumed present. The DWT cycle counter is used for timestamping.
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*
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* If the below error is produced, the DWT unit does not seem to be available.
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*
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* In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build
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* to use SysTick timestamping instead, or define your own timestamping by
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* setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED
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* and make the necessary definitions, as explained in trcHardwarePort.h.*/
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xTraceError( TRC_ERROR_DWT_NOT_SUPPORTED );
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break;
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}
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/* Verify that DWT_CYCCNT is supported */
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if( TRC_REG_DWT_CTRL & TRC_DWT_CTRL_NOCYCCNT )
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{
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/* This function is called on Cortex-M3, M4 and M7 devices to initialize
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* the DWT unit, assumed present. The DWT cycle counter is used for timestamping.
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*
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* If the below error is produced, the cycle counter does not seem to be available.
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*
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* In that case, define the macro TRC_CFG_ARM_CM_USE_SYSTICK in your build
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* to use SysTick timestamping instead, or define your own timestamping by
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* setting TRC_CFG_HARDWARE_PORT to TRC_HARDWARE_PORT_APPLICATION_DEFINED
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* and make the necessary definitions, as explained in trcHardwarePort.h.*/
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xTraceError( TRC_ERROR_DWT_CYCCNT_NOT_SUPPORTED );
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break;
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}
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/* Reset the cycle counter */
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TRC_REG_DWT_CYCCNT = 0;
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/* Enable the cycle counter */
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TRC_REG_DWT_CTRL |= TRC_DWT_CTRL_CYCCNTENA;
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} while( 0 ); /* breaks above jump here */
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}
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#endif /* TRC_CFG_ARM_CM_USE_SYSTICK */
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#endif /* (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) */
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#endif /* ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M) && (defined (__CORTEX_M) && (__CORTEX_M >= 0x03))) */
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#if ( ( TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9 ) || ( TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5 ) || ( TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_CYCLONE_V_HPS ) )
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#define CS_TYPE_NONE 0
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#define CS_TYPE_TASK 1
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#define CS_TYPE_ISR_MASK_CHANGED 2
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#define CS_TYPE_ISR_MASK_NOT_CHANGED 3
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#define CS_TYPE_INVALID 0xFFFFFFFF
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int cortex_a9_r5_enter_critical( void )
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{
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uint32_t cs_type = CS_TYPE_INVALID;
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if( ( prvGetCPSR() & 0x001F ) == 0x13 ) /* CSPR (ASPR) mode = SVC */
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{
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/* Executing in an ISR other than the context-switch (where interrupts might have been enabled, motivating a critical section). */
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if( ulPortSetInterruptMask() == pdTRUE )
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{
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cs_type = CS_TYPE_ISR_MASK_NOT_CHANGED;
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}
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else
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{
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cs_type = CS_TYPE_ISR_MASK_CHANGED;
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}
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}
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else if( pxTraceRecorderData->uiTraceSystemState == TRC_STATE_IN_TASKSWITCH )
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{
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/* In the context-switch code. All interrupts are already masked here, so don't modify the mask. */
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cs_type = CS_TYPE_NONE;
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}
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else if( pxTraceRecorderData->uiTraceSystemState != TRC_STATE_IN_TASKSWITCH )
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{
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/* Not within ISR or task-switch context, use a regular critical section. */
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vPortEnterCritical();
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cs_type = CS_TYPE_TASK;
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}
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return cs_type;
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}
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void cortex_a9_r5_exit_critical( int cs_type )
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{
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switch( cs_type )
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{
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case CS_TYPE_TASK:
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vPortExitCritical();
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break;
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case CS_TYPE_ISR_MASK_CHANGED:
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vPortClearInterruptMask( pdFALSE ); /* pdFALSE means it will reset the IRQ mask. */
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break;
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case CS_TYPE_ISR_MASK_NOT_CHANGED:
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case CS_TYPE_NONE:
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/* No action in these two cases. */
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break;
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default:
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/* Error, should not be possible; */
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for( ; ; )
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{
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}
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}
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}
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#endif /* ((TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9) || (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5)) */
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#endif /* (TRC_USE_TRACEALYZER_RECORDER == 1) */
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