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229 lines
6.9 KiB
C
229 lines
6.9 KiB
C
/*
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* Percepio Trace Recorder for Tracealyzer v4.6.0
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* Copyright 2021 Percepio AB
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* www.percepio.com
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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*
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* @brief Public trace ISR APIs.
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*/
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#ifndef TRC_ISR_H
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#define TRC_ISR_H
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#if ( TRC_USE_TRACEALYZER_RECORDER == 1 )
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#if ( TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING )
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#include <trcTypes.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup trace_isr_apis Trace ISR APIs
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* @ingroup trace_recorder_apis
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* @{
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*/
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/**
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* @internal Trace ISR Core Info Structure
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*/
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typedef struct TraceISRCoreInfo
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{
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TraceISRHandle_t handleStack[ TRC_CFG_MAX_ISR_NESTING ]; /**< */
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int32_t stackIndex; /**< */
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int32_t isPendingContextSwitch; /**< */
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} TraceISRCoreInfo_t;
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/**
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* @internal Trace ISR Info Structure
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*/
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typedef struct TraceISRInfo
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{
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TraceISRCoreInfo_t coreInfos[ TRC_CFG_CORE_COUNT ]; /* ISR handles */
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} TraceISRInfo_t;
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/* We expose this to enable faster access */
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extern TraceISRInfo_t * pxTraceISRInfo;
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#define TRACE_ISR_INFO_BUFFER_SIZE ( sizeof( TraceISRInfo_t ) )
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/**
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* @internal Trace ISR Info Buffer
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*/
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typedef struct TraceISRInfoBuffer
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{
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uint8_t buffer[ ( TRACE_ISR_INFO_BUFFER_SIZE ) ]; /**< */
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} TraceISRInfoBuffer_t;
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/**
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* @internal Initialize ISR trace system.
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*
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* @param[in] pxBuffer Pointer to memory that will be used by the ISR
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* trace system.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISRInitialize( TraceISRInfoBuffer_t * pxBuffer );
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/**
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* @brief Registers trace ISR.
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*
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* This routine stores a name and priority level for an Interrupt Service Routine,
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* to allow for better visualization. Returns a TraceISRHandle_t used by
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* xTraceISRBegin/xTraceISREnd.
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*
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* Example:
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* #define PRIO_OF_ISR_TIMER1 3 // the hardware priority of the interrupt
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* TraceISRHandle_t xISRTimer1Handle = 0; // The ID set by the recorder
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* ...
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* xTraceISRRegister("ISRTimer1", PRIO_OF_ISR_TIMER1, &xISRTimer1Handle);
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* ...
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* void ISR_handler()
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* {
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* xTraceISRBegin(xISRTimer1Handle);
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* ...
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* xTraceISREnd(0);
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* }
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*
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* @param[in] szName Name.
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* @param[in] uiPriority Priority.
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* @param[out] pxISRHandle Pointer to uninitialized ISR trace handle.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISRRegister( const char * szName,
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uint32_t uiPriority,
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TraceISRHandle_t * pxISRHandle );
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/**
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* @brief Registers the beginning of an Interrupt Service Routine.
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*
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* This routine register the beginning of an ISR using a TraceISRHandle_t.
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* See xTraceISRRegister for and example of using ISR tracing.
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*
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* @param[in] xISRHandle Pointer to initialized ISR trace handle.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISRBegin( TraceISRHandle_t xISRHandle );
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/**
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* @brief Registers the end of an Interrupt Service Routine.
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*
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* This routine register the end of an ISR using a TraceISRHandle_t.
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* See xTraceISRRegister for and example of using ISR tracing.
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*
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* The parameter uxIsTaskSwitchRequired indicates if the interrupt has requested
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* a task-switch (= 1), e.g., by signaling a semaphore. Otherwise (= 0) the
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* interrupt is assumed to return to the previous context.
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*
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* @param[in] xIsTaskSwitchRequired Task switch required.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISREnd( TraceBaseType_t xIsTaskSwitchRequired );
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#if ( ( TRC_CFG_USE_TRACE_ASSERT ) == 1 )
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/**
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* @brief Gets current trace ISR nesting level.
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*
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* This routine gets the current trace ISR nesting level for the
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* CPU on which it is called.
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*
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* @param[out] puiValue Value.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISRGetCurrentNesting( int32_t * puiValue );
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/**
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* @brief
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*
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* @return int32_t
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*/
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int32_t xTraceISRGetCurrentNestingReturned( void );
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/**
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* @brief Gets current ISR trace handle.
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*
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* @param[out] pxISRHandle ISR Handle.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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traceResult xTraceISRGetCurrent( TraceISRHandle_t * pxISRHandle );
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#else /* ((TRC_CFG_USE_TRACE_ASSERT) == 1) */
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/**
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* @brief Gets current trace ISR nesting level.
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*
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* This routine gets the current trace ISR nesting level for the
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* CPU on which it is called.
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*
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* @param[out] puiValue Value.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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#define xTraceISRGetCurrentNesting( puiValue ) TRC_COMMA_EXPR_TO_STATEMENT_EXPR_2( *( puiValue ) = pxTraceISRInfo->coreInfos[ TRC_CFG_GET_CURRENT_CORE() ].stackIndex, TRC_SUCCESS )
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/**
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* @brief
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*
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* @return int32_t
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*/
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#define xTraceISRGetCurrentNestingReturned() ( pxTraceISRInfo->coreInfos[ TRC_CFG_GET_CURRENT_CORE() ].stackIndex )
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/**
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* @brief Gets current trace ISR nesting level.
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*
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* This routine gets the current trace ISR nesting level for the
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* CPU on which it is called.
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*
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* @param[out] puiValue Value.
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*
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* @retval TRC_FAIL Failure
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* @retval TRC_SUCCESS Success
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*/
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#define xTraceISRGetCurrent( pxISRHandle ) ( xTraceISRGetCurrentNestingReturned() >= 0 ? ( *( pxISRHandle ) = pxTraceISRInfo->coreInfos[ TRC_CFG_GET_CURRENT_CORE() ].handleStack[ xTraceISRGetCurrentNestingReturned() ], TRC_SUCCESS ) : TRC_FAIL )
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#endif /* ((TRC_CFG_USE_TRACE_ASSERT) == 1) */
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/** @internal Deprecated - Provides backwards-compability with older recorders for now, will be removed in the future */
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TraceISRHandle_t xTraceSetISRProperties( const char * szName,
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uint32_t uiPriority );
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/** @internal Deprecated - Provides backwards-compability with older recorders for now, will be removed in the future */
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#define xTraceGetCurrentISRNesting( puiValue ) xTraceISRGetCurrentNesting( puiValue )
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/** @internal Deprecated - Provides backwards-compability with older recorders for now, will be removed in the future */
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#define vTraceStoreISRBegin( xISRHandle ) xTraceISRBegin( xISRHandle )
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/** @internal Deprecated - Provides backwards-compability with older recorders for now, will be removed in the future */
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#define vTraceStoreISREnd( xIsTaskSwitchRequired ) xTraceISREnd( xIsTaskSwitchRequired )
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING) */
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#endif /* (TRC_USE_TRACEALYZER_RECORDER == 1) */
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#endif /* TRC_ISR_H */
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