mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
d0d55f3031
Fix FPU stack order issue and Improve FPU checking flow Fix Interrupt depth comparison logic Fix parameter mismatch in portmacro.h file Add comment to explain assembly code
735 lines
29 KiB
C
735 lines
29 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* This port uses xTaskGetCurrentTaskHandle to get TCB stack, it is required to
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* enable this API. */
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#if ( ( INCLUDE_xTaskGetCurrentTaskHandle != 1 ) && ( configNUMBER_OF_CORES == 1 ) )
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#error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 in single core.
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#endif
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/***********************************************************
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* Macro definitions
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***********************************************************/
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/* Hardware specific macros */
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#define portPSW_REGISTER_ID ( 5 )
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#define portFPSR_REGISTER_ID ( 6 )
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/* PSW.EBV and PSW.CUx bits are kept as current status */
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#define portINITIAL_PSW_MASK ( 0x000f8000 )
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#define portCURRENT_PSW_VALUE ( portSTSR( portPSW_REGISTER_ID ) )
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#define portCURRENT_SR_ZERO_VALUE ( ( StackType_t ) 0x00000000 )
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#define portCURRENT_FPSR_VALUE ( portSTSR( portFPSR_REGISTER_ID ) )
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/* Mask for FPU configuration bits (FN, PEM, RM, FS) */
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#define portINITIAL_FPSR_MASK ( 0x00ae0000 )
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#define portPSW_ID_MASK ( 0x00000020 )
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/* Define necessary hardware IO for OSTM timer. OSTM0 is used by default as
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* it is common for almost device variants. If it conflicts with application,
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* the application shall implement another timer.*/
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#define portOSTM_EIC_ADDR ( 0xFFFFB0A8 )
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#define portOSTM0CMP_ADDR ( 0xFFD70000 )
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#define portOSTM0CTL_ADDR ( 0xFFD70020 )
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#define portOSTM0TS_ADDR ( 0xFFD70014 )
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#if ( configNUMBER_OF_CORES > 1 )
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/* IPIR base address, the peripheral is used for Inter-Processor communication
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* Hardware supports 4 channels which is offset by 0x0, 0x4, 0x8, 0xC bytes from
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* base address. By default, channel 0 is selected. */
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#ifdef configIPIR_CHANNEL
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#define portIPIR_BASE_ADDR ( ( 0xFFFEEC80 ) + ( configIPIR_CHANNEL << 2 ) )
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#else
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#define portIPIR_BASE_ADDR ( 0xFFFEEC80 )
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#endif
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/* Address used for exclusive control for variable shared between PEs
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* (common resources), each CPU cores have independent access path to
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* this address. By default, G0MEV0 register is selected*/
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#ifdef configEXCLUSIVE_ADDRESS
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#define portMEV_BASE_ADDR configEXCLUSIVE_ADDRESS
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#else
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#define portMEV_BASE_ADDR ( 0xFFFEEC00 )
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#endif
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#endif /* if ( configNUMBER_OF_CORES > 1 ) */
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/* Macros required to set up the initial stack. */
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#define portSTACK_INITIAL_VALUE_R1 ( ( StackType_t ) 0x01010101 )
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#define portSTACK_INITIAL_VALUE_R2 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x02 )
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#define portSTACK_INITIAL_VALUE_R3 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x03 )
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#define portSTACK_INITIAL_VALUE_R4 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x04 )
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#define portSTACK_INITIAL_VALUE_R5 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x05 )
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#define portSTACK_INITIAL_VALUE_R6 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x06 )
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#define portSTACK_INITIAL_VALUE_R7 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x07 )
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#define portSTACK_INITIAL_VALUE_R8 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x08 )
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#define portSTACK_INITIAL_VALUE_R9 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x09 )
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#define portSTACK_INITIAL_VALUE_R10 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x10 )
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#define portSTACK_INITIAL_VALUE_R11 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x11 )
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#define portSTACK_INITIAL_VALUE_R12 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x12 )
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#define portSTACK_INITIAL_VALUE_R13 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x13 )
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#define portSTACK_INITIAL_VALUE_R14 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x14 )
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#define portSTACK_INITIAL_VALUE_R15 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x15 )
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#define portSTACK_INITIAL_VALUE_R16 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x16 )
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#define portSTACK_INITIAL_VALUE_R17 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x17 )
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#define portSTACK_INITIAL_VALUE_R18 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x18 )
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#define portSTACK_INITIAL_VALUE_R19 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x19 )
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#define portSTACK_INITIAL_VALUE_R20 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x20 )
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#define portSTACK_INITIAL_VALUE_R21 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x21 )
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#define portSTACK_INITIAL_VALUE_R22 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x22 )
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#define portSTACK_INITIAL_VALUE_R23 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x23 )
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#define portSTACK_INITIAL_VALUE_R24 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x24 )
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#define portSTACK_INITIAL_VALUE_R25 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x25 )
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#define portSTACK_INITIAL_VALUE_R26 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x26 )
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#define portSTACK_INITIAL_VALUE_R27 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x27 )
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#define portSTACK_INITIAL_VALUE_R28 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x28 )
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#define portSTACK_INITIAL_VALUE_R29 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x29 )
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#define portSTACK_INITIAL_VALUE_R30 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x30 )
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/***********************************************************
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* Typedef definitions
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***********************************************************/
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/* OSTM Count Start Trigger Register (OSTMnTS) */
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#define portOSTM_COUNTER_START ( 0x01U ) /* Starts the counter */
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/* OSTM Count Stop Trigger Register (OSTMnTT) */
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#define portOSTM_COUNTER_STOP ( 0x01U ) /* Stops the counter */
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/* OSTM Control Register (OSTMnCTL) */
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#define portOSTM_MODE_INTERVAL_TIMER ( 0x00U )
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#define portOSTM_MODE_FREE_RUNNING ( 0x02U )
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/* Disables or Enable the interrupts when counting starts */
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#define portOSTM_START_INTERRUPT_DISABLE ( 0x00U )
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#define portOSTM_START_INTERRUPT_ENABLE ( 0x01U )
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/* Interrupt vector method select (TBxxx) */
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#define portINT_DIRECT_VECTOR ( 0x0U )
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#define portINT_TABLE_VECTOR ( 0x1U )
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/* Interrupt mask (MKxxx) */
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#define portINT_PROCESSING_ENABLED ( 0x0U )
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#define portINT_PROCESSING_DISABLED ( 0x1U )
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/* Specify 16 interrupt priority levels */
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#define portINT_PRIORITY_HIGHEST ( 0x0000U ) /* Level 0 (highest) */
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#define portINT_PRIORITY_LEVEL1 ( 0x0001U ) /* Level 1 */
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#define portINT_PRIORITY_LEVEL2 ( 0x0002U ) /* Level 2 */
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#define portINT_PRIORITY_LEVEL3 ( 0x0003U ) /* Level 3 */
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#define portINT_PRIORITY_LEVEL4 ( 0x0004U ) /* Level 4 */
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#define portINT_PRIORITY_LEVEL5 ( 0x0005U ) /* Level 5 */
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#define portINT_PRIORITY_LEVEL6 ( 0x0006U ) /* Level 6 */
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#define portINT_PRIORITY_LEVEL7 ( 0x0007U ) /* Level 7 */
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#define portINT_PRIORITY_LEVEL8 ( 0x0008U ) /* Level 8 */
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#define portINT_PRIORITY_LEVEL9 ( 0x0009U ) /* Level 9 */
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#define portINT_PRIORITY_LEVEL10 ( 0x000AU ) /* Level 10 */
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#define portINT_PRIORITY_LEVEL11 ( 0x000BU ) /* Level 11 */
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#define portINT_PRIORITY_LEVEL12 ( 0x000CU ) /* Level 12 */
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#define portINT_PRIORITY_LEVEL13 ( 0x000DU ) /* Level 13 */
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#define portINT_PRIORITY_LEVEL14 ( 0x000EU ) /* Level 14 */
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#define portINT_PRIORITY_LOWEST ( 0x000FU ) /* Level 15 (lowest) */
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/* Macros indicating status of scheduler request */
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#define PORT_SCHEDULER_NOREQUEST 0UL
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#define PORT_SCHEDULER_TASKSWITCH 1UL /* Do not modify */
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#define PORT_SCHEDULER_STARTFIRSTTASK 2UL /* Do not modify */
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#ifndef configSETUP_TICK_INTERRUPT
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/* The user has not provided their own tick interrupt configuration so use
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* the definition in this file (which uses the interval timer). */
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#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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#endif /* configSETUP_TICK_INTERRUPT */
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#if ( !defined( configMAX_INT_NESTING ) || ( configMAX_INT_NESTING == 0 ) )
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/* Set the default value for depth of nested interrupt. In theory, the
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* microcontroller have mechanism to limit number of nested level of interrupt
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* by priority (maximum 16 levels). However, the large stack memory should be
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* prepared for each task to save resource in interrupt handler. Therefore, it
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* is necessary to limit depth of nesting interrupt to optimize memory usage.
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* In addition, the execution time of interrupt handler should be very short
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* (typically not exceed 20us), this constraint does not impact to system.
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*/
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#define configMAX_INT_NESTING 2UL
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#endif
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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/*
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* Sets up the periodic ISR used for the RTOS tick using the OSTM.
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* The application writer can define configSETUP_TICK_INTERRUPT() (in
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* FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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* in place of prvSetupTimerInterrupt().
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*/
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static void prvSetupTimerInterrupt( void );
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#if ( configNUMBER_OF_CORES > 1 )
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/*
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* Functions implement spin-lock between cores by atomic accesses to Exclusive
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* Control Register (G0MEVm). There are separated access path between CPU cores,
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* but they should wait if access to same register
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*/
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static void prvExclusiveLock( BaseType_t xFromIsr );
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static void prvExclusiveRelease( BaseType_t xFromIsr );
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#endif
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/*
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* Function to start the first task executing
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*/
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extern void vPortStartFirstTask( void );
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/* Scheduler request on each cores which are starting first task and switching
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* context */
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volatile BaseType_t xPortScheduleStatus[ configNUMBER_OF_CORES ] = { 0 };
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* the nesting depth is 0. In addition, the interrupt shares same stack
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* allocated for each tasks. With supporting nesting interrupt, the stack
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* may be overflowed.
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* It is necessary to control maximum stack depth.
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*/
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volatile UBaseType_t uxInterruptNesting[ configNUMBER_OF_CORES ] = { 0 };
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volatile const UBaseType_t uxPortMaxInterruptDepth = configMAX_INT_NESTING;
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/* Count number of nested locks by same cores. The lock is completely released
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* only if this count is decreased to 0, the lock is separated for task
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* and isr */
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UBaseType_t uxLockNesting[ configNUMBER_OF_CORES ][ 2 ] = { 0 };
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#if ( configNUMBER_OF_CORES > 1 )
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/* Pointer to exclusive access memory */
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volatile BaseType_t * pxPortExclusiveReg = ( volatile BaseType_t * ) ( portMEV_BASE_ADDR );
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#endif
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/* Interrupt handler for OSTM timer which handling tick increment and resulting
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* to switch context. */
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void vPortTickISR( void );
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#if ( configNUMBER_OF_CORES > 1 )
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/* Yield specific cores by send inter-processor interrupt */
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void vPortYieldCore( uint32_t xCoreID );
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/*
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* Inter-processor interrupt handler. The interrupt is triggered by
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* portYIELD_CORE().
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*/
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void vPortIPIHander( void );
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/* These functions below implement recursive spinlock for exclusive access among
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* cores. The core will wait until lock will be available, whilst the core which
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* already had lock can acquire lock without waiting. This function could be
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* call from task and interrupt context, the critical section is called
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* as in ISR */
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void vPortRecursiveLockAcquire( BaseType_t xFromIsr );
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void vPortRecursiveLockRelease( BaseType_t xFromIsr );
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#endif /* (configNUMBER_OF_CORES > 1) */
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/*-----------------------------------------------------------*/
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/*
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* These below functions implement interrupt mask from interrupt. They are not
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* called in nesting, it is protected by FreeRTOS kernel.
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*/
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portLONG xPortSetInterruptMask( void )
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{
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portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID );
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portDISABLE_INTERRUPTS();
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/* It returns current value of Program Status Word register */
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return ulPSWValue;
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}
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/*-----------------------------------------------------------*/
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void vPortClearInterruptMask( portLONG uxSavedInterruptStatus )
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{
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portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID );
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/* Interrupt Disable status is indicates by bit#5 of PSW
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* (1: Interrupt is disabled; 0: Interrupt is enabled) */
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/* Revert to the status before interrupt mask. */
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ulPSWValue &= ( ~( portPSW_ID_MASK ) );
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ulPSWValue |= ( portPSW_ID_MASK & uxSavedInterruptStatus );
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portLDSR( portPSW_REGISTER_ID, ulPSWValue );
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}
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/*-----------------------------------------------------------*/
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/*
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* Using CC-RH intrinsic function to get HTCFG0 (regID, selID) = (0,2)
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* Core ID is indicates by bit HTCFG0.PEID located at bit 18 to 16
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* Bit 31 to 19 are read only and always be read as 0. HTCFG0.PEID is 1 and 2
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* corresponding to core 0 (PE1) and core 1 (PE2). It is adjusted to 0 and 1.
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*/
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BaseType_t xPortGET_CORE_ID( void )
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{
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#if ( configNUMBER_OF_CORES > 1 )
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return ( portSTSR_CCRH( 0, 2 ) >> 16 ) - 1;
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#else
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/* In single core, xPortGET_CORE_ID is used in this port only.
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* The dummy core ID could be controlled inside this port. */
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return 0;
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#endif
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}
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/*-----------------------------------------------------------*/
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/*
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* This port supports both multi-cores and single-core, whilst TCB stack
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* variables are different which are respectively pxCurrentTCB (single-core)
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* and pxCurrentTCBs[] (multiple-cores). This function is defined to obtains
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* TCBs of current cores. Also, the C function could switch to corresponding
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* pointer by pre-compile conditions.
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*/
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void * pvPortGetCurrentTCB( void )
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{
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void * pvCurrentTCB = ( void * ) xTaskGetCurrentTaskHandle();
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configASSERT( pvCurrentTCB != NULL );
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return pvCurrentTCB;
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}
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/*-----------------------------------------------------------*/
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/*
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* This function checks if a context switch is required and, if so, updates
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* the scheduler status for the core on which the function is called. The
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* scheduler status is set to indicate that a task switch should occur.
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*/
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void vPortSetSwitch( BaseType_t xSwitchRequired )
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{
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if( xSwitchRequired != pdFALSE )
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{
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xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH;
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* Setup the stack of a new task so it is ready to be placed under the
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* scheduler control. The registers have to be placed on the stack in the
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* order that the port expects to find them.
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*
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* @param[in] pxTopOfStack Pointer to top of this task's stack
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* @param[in] pxCode Task function, stored as initial PC for the task
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* @param[in] pvParameters Parameters for task
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Simulate the stack frame as it would be created by
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* a context switch interrupt. */
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*pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R31 (LP) */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R5; /* R5 (TP) */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R7; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R8; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R9; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R10; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R11; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R12; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R13; /* R13 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R14; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R15; /* R15 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R16; /* R16 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R17; /* R17 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R18; /* R18 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R19; /* R19 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R20; /* R20 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R21; /* R21 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R22; /* R22 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R23; /* R23 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R24; /* R24 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R25; /* R25 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R26; /* R26 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R27; /* R27 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R28; /* R28 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R29; /* R29 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R30; /* R30 (EP) */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R1; /* R1 */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R2; /* R2 */
|
|
|
|
pxTopOfStack--;
|
|
|
|
/* Keep System pre-configuration (HV, CUx, EBV) as current setting in
|
|
* PSW register */
|
|
*pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* EIPSW */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) pxCode; /* EIPC */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* EIIC */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* CTPSW */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* CTPC */
|
|
|
|
/* __FPU is defined by CCRH compiler if FPU is enabled */
|
|
#if ( configENABLE_FPU == 1 )
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) ( portCURRENT_FPSR_VALUE & portINITIAL_FPSR_MASK ); /* FPSR */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* FPEPC */
|
|
#endif /* (configENABLE_FPU == 1) */
|
|
|
|
return pxTopOfStack;
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* Configures the tick frequency and starts the first task.
|
|
*/
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
BaseType_t xCurrentCore = xPortGET_CORE_ID();
|
|
#endif
|
|
|
|
/* Prevent interrupt by timer interrupt during starting first task.
|
|
* The interrupt shall be enabled automatically by being restored from
|
|
* task stack */
|
|
portDISABLE_INTERRUPTS();
|
|
|
|
/* Setup the tick interrupt */
|
|
configSETUP_TICK_INTERRUPT();
|
|
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
/* Start scheduler on other cores */
|
|
for( uint16_t xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
|
|
{
|
|
if( xCoreID != xCurrentCore )
|
|
{
|
|
/* Send yielding request to other cores with flag to start
|
|
* first task. TaskContextSwitch is not executed */
|
|
xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_STARTFIRSTTASK;
|
|
vPortYieldCore( xCoreID );
|
|
}
|
|
else
|
|
{
|
|
/* Nothing to do. The first task is started in this call by
|
|
* below vPortStartFirstTask() */
|
|
xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_NOREQUEST;
|
|
}
|
|
}
|
|
#endif /* if ( configNUMBER_OF_CORES > 1 ) */
|
|
|
|
/* Start first task in primary core */
|
|
vPortStartFirstTask();
|
|
|
|
/* Should never get here as the tasks will now be executing! */
|
|
prvTaskExitError();
|
|
|
|
/* To prevent compiler warnings in the case that the application writer
|
|
* overrides this functionality by defining configTASK_RETURN_ADDRESS.
|
|
* Call vTaskSwitchContext() so link time optimization does not remove
|
|
* the symbol. */
|
|
vTaskSwitchContext(
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
xCurrentCore
|
|
#endif
|
|
);
|
|
|
|
return pdFALSE;
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* Used to catch tasks that attempt to return from their implementing function.
|
|
*/
|
|
static void prvTaskExitError( void )
|
|
{
|
|
/* A function that implements a task must not exit or attempt to return to
|
|
* its caller as there is nothing to return to. If a task wants to exit it
|
|
* should instead call vTaskDelete( NULL ).
|
|
*
|
|
* Artificially force an assert() to be triggered if configASSERT() is
|
|
* defined, then stop here so application writers can catch the error. */
|
|
|
|
/* This statement will always fail, triggering the assert */
|
|
configASSERT( pdFALSE );
|
|
|
|
/*
|
|
* The following statement may be unreachable because configASSERT(pdFALSE)
|
|
* always triggers an assertion failure, which typically halts program
|
|
* execution.
|
|
* The warning may be reported to indicate to indicate that the compiler
|
|
* detects the subsequent code will not be executed.
|
|
* The warning is acceptable to ensure program is halt regardless of
|
|
* configASSERT(pdFALSE) implementation
|
|
*/
|
|
portDISABLE_INTERRUPTS();
|
|
|
|
for( ; ; )
|
|
{
|
|
/* Infinite loop to ensure the function does not return. */
|
|
}
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEndScheduler( void )
|
|
{
|
|
/* Not implemented in ports where there is nothing to return to.
|
|
* Artificially force an assert. */
|
|
configASSERT( pdFALSE );
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
|
|
void vPortYieldCore( uint32_t xCoreID )
|
|
{
|
|
/* Check if we need to yield on a different core */
|
|
if( xCoreID != xPortGET_CORE_ID() )
|
|
{
|
|
volatile uint32_t * pulIPIRReg;
|
|
|
|
/* Determine the IPI register based on the target core ID */
|
|
pulIPIRReg = ( volatile uint32_t * ) ( portIPIR_BASE_ADDR );
|
|
|
|
/*Inter-processor interrupt generates an interrupt request by
|
|
* writing 1 to applicable bits of target cores. The interrupt
|
|
* should be enabled by application in corresponding cores
|
|
* including PSW.ID (EI instruction) and interrupt control setting
|
|
* for ICIPIRn channel (interrupt mask, vector method)
|
|
*/
|
|
*pulIPIRReg = ( 1 << xCoreID );
|
|
}
|
|
else
|
|
{
|
|
/* Yielding current core */
|
|
vPortYield();
|
|
}
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* Handler for inter-processor interrupt in second cores. The interrupt is
|
|
* triggered by portYIELD_CORE(). vTaskSwitchContext() is invoked to
|
|
* switch tasks
|
|
*/
|
|
void vPortIPIHander( void )
|
|
{
|
|
BaseType_t xCurrentCore = xPortGET_CORE_ID();
|
|
|
|
/* 1st execution starts 1st task, TaskSwitchContext is not executed */
|
|
if( PORT_SCHEDULER_STARTFIRSTTASK != xPortScheduleStatus[ xCurrentCore ] )
|
|
{
|
|
xPortScheduleStatus[ xCurrentCore ] = PORT_SCHEDULER_TASKSWITCH;
|
|
}
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#endif /* (configNUMBER_OF_CORES > 1) */
|
|
|
|
void vPortTickISR( void )
|
|
{
|
|
/* In case of multicores with SMP, xTaskIncrementTick is required to
|
|
* called in critical section to avoid conflict resource as this function
|
|
* could be called by xTaskResumeAll() from any cores. */
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
BaseType_t xSavedInterruptStatus;
|
|
|
|
xSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR();
|
|
#endif
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
/* Pend a context switch. */
|
|
xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH;
|
|
}
|
|
}
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
portEXIT_CRITICAL_FROM_ISR( xSavedInterruptStatus );
|
|
#endif
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvSetupTimerInterrupt( void )
|
|
{
|
|
volatile uint32_t * pulOSTMIntReg;
|
|
|
|
/* Interrupt configuration for OSTM Timer
|
|
* By default, the second lowest priority is set for timer interrupt to
|
|
* avoid blocking other interrupt. Normally, user could set the lowest
|
|
* priority for non-critical event. It try to keep timer on time.
|
|
* In addition, direct vector table is used by default.
|
|
*/
|
|
pulOSTMIntReg = ( volatile uint32_t * ) portOSTM_EIC_ADDR;
|
|
*pulOSTMIntReg = ( portINT_PROCESSING_ENABLED | portINT_DIRECT_VECTOR | portINT_PRIORITY_LEVEL14 );
|
|
|
|
/* Set OSTM0 control setting */
|
|
*( ( volatile uint32_t * ) portOSTM0CTL_ADDR ) =
|
|
( portOSTM_MODE_INTERVAL_TIMER | portOSTM_START_INTERRUPT_DISABLE );
|
|
*( ( volatile uint32_t * ) portOSTM0CMP_ADDR ) =
|
|
( ( configCPU_CLOCK_HZ / configTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
|
|
|
|
/* Enable OSTM0 operation */
|
|
*( ( volatile uint32_t * ) portOSTM0TS_ADDR ) = portOSTM_COUNTER_START;
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
|
|
/*
|
|
* These functions implement spin-lock mechanism among cores using hardware
|
|
* exclusive control with atomic access by CLR1 and SET1 instruction.
|
|
* Nesting calls to these APIs are possible.
|
|
*/
|
|
#pragma inline_asm prvExclusiveLock
|
|
static void prvExclusiveLock( BaseType_t xBitPosition )
|
|
{
|
|
/* No problem with r19, CCRH does not required to restore same value
|
|
* before and after function call. */
|
|
mov # _pxPortExclusiveReg, r19
|
|
ld.w 0[ r19 ], r19
|
|
|
|
prvExclusiveLock_Lock:
|
|
|
|
/* r6 is xBitPosition */
|
|
set1 r6, [ r19 ]
|
|
bz prvExclusiveLock_Lock_success
|
|
snooze
|
|
br prvExclusiveLock_Lock
|
|
|
|
prvExclusiveLock_Lock_success:
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#pragma inline_asm prvExclusiveRelease
|
|
static void prvExclusiveRelease( BaseType_t xBitPosition )
|
|
{
|
|
mov # _pxPortExclusiveReg, r19
|
|
ld.w 0[ r19 ], r19
|
|
|
|
/* r6 is xBitPosition */
|
|
clr1 r6, [ r19 ]
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
void vPortRecursiveLockAcquire( BaseType_t xFromIsr )
|
|
{
|
|
BaseType_t xSavedInterruptStatus;
|
|
BaseType_t xCoreID = xPortGET_CORE_ID();
|
|
BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
|
|
|
|
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
|
|
if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 )
|
|
{
|
|
prvExclusiveLock( xBitPosition );
|
|
}
|
|
|
|
uxLockNesting[ xCoreID ][ xBitPosition ]++;
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
|
|
}
|
|
|
|
void vPortRecursiveLockRelease( BaseType_t xFromIsr )
|
|
{
|
|
BaseType_t xSavedInterruptStatus;
|
|
BaseType_t xCoreID = xPortGET_CORE_ID();
|
|
BaseType_t xBitPosition = ( xFromIsr == pdTRUE );
|
|
|
|
xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
|
|
/* Sync memory */
|
|
portSYNCM();
|
|
|
|
/* Error check whether vPortRecursiveLockRelease() is not called in
|
|
* pair with vPortRecursiveLockAcquire() */
|
|
configASSERT( ( uxLockNesting[ xCoreID ][ xBitPosition ] > 0 ) );
|
|
uxLockNesting[ xCoreID ][ xBitPosition ]--;
|
|
|
|
if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 )
|
|
{
|
|
prvExclusiveRelease( xBitPosition );
|
|
}
|
|
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus );
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#endif /* (configNUMBER_OF_CORES > 1) */
|