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b4972f4093
Bits 0-4 are reserved for VALID and REGION, while ADDR spans at most bits 5-31 (bits 5-7 are sometimes reserved and not assigned to ADDR field). Masking ensures that a misaligned base address cannot modify less significant bits in the attribute reserved for other use. Failing to mask the address may allow a malicious user to pass in misaligned addresses in a user-defined region or as stack buffer which could in turn override the settings for higher-priority kernel-defined regions. This change doesn't guarantee that only properly aligned addresses are written to the ADDR field of the register, and doesn't ensure that reserved field from bits 5-7 are not written to, but protects the VALID and REGION fields. |
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| ARM7_LPC21xx | ||
| ARM_CA9 | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM4_MPU | ||
| ARM_CM4F | ||
| ARM_CM7 | ||