Corentin Pane b4972f4093 Mask MPU region base addresses when writing to MPU_RBAR on ARM_CM3/4 ... Bits 0-4 are reserved for VALID and REGION, while ADDR spans at most bits 5-31 (bits 5-7 are sometimes reserved and not assigned to ADDR field). Masking ensures that a misaligned base address cannot modify less significant bits in the attribute reserved for other use. Failing to mask the address may allow a malicious user to pass in misaligned addresses in a user-defined region or as stack buffer which could in turn override the settings for higher-priority kernel-defined regions. This change doesn't guarantee that only properly aligned addresses are written to the ADDR field of the register, and doesn't ensure that reserved field from bits 5-7 are not written to, but protects the VALID and REGION fields.		2026-08-31 16:34:46 +02:00
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mpu_wrappers_v2_asm.c	Fix AutoReload variable name (#1166)	2024-10-31 21:33:25 +05:30
port.c	Mask MPU region base addresses when writing to MPU_RBAR on ARM_CM3/4	2026-08-31 16:34:46 +02:00
portmacro.h	Fix the context array size for MPU ports (#1230)	2025-01-25 13:34:03 +05:30