mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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249 lines
8.4 KiB
C
249 lines
8.4 KiB
C
/**************************************************************************//**
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* @file
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* @brief EBI implementation of Board Control interface
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* This implementation works for devices w/o LCD display on the
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* MCU module, specifically the EFM32_G2xx_DK development board
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* @author Energy Micro AS
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* @version 1.0.1
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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#include "efm32.h"
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#include "dvk.h"
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#include "dvk_bcregisters.h"
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/**************************************************************************//**
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* @brief Configure EBI (external bus interface) for Board Control register
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* access
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*****************************************************************************/
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void DVK_EBI_configure(void)
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{
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GPIO_TypeDef *gpio = GPIO;
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EBI_TypeDef *ebi = EBI;
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CMU_TypeDef *cmu = CMU;
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/* Run time check if we have EBI on-chip capability on this device */
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switch ((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) >>
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_DEVINFO_PART_DEVICE_NUMBER_SHIFT)
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{
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/* Only device types EFM32G 280/290/880 and 890 have EBI capability */
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case 280:
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case 290:
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case 880:
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case 890:
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break;
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default:
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/* This device do not have EBI capability - use SPI to interface DVK */
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/* With high probability your project has been configured for an */
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/* incorrect part number. */
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while (1) ;
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}
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/* Enable clocks */
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cmu->HFCORECLKEN0 |= CMU_HFCORECLKEN0_EBI;
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cmu->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
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/* Configure bus connect PC bit 12 active low */
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gpio->P[2].MODEH |=
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GPIO_P_MODEH_MODE12_PUSHPULL;
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gpio->P[2].DOUT &= ~(1UL << 12);
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/* Configure GPIO pins as push pull */
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/* EBI AD9..15 */
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gpio->P[0].MODEL |=
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(GPIO_P_MODEL_MODE0_PUSHPULL |
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GPIO_P_MODEL_MODE1_PUSHPULL |
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GPIO_P_MODEL_MODE2_PUSHPULL |
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GPIO_P_MODEL_MODE3_PUSHPULL |
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GPIO_P_MODEL_MODE4_PUSHPULL |
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GPIO_P_MODEL_MODE5_PUSHPULL |
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GPIO_P_MODEL_MODE6_PUSHPULL);
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/* EBI AD8 */
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gpio->P[0].MODEH |=
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GPIO_P_MODEH_MODE15_PUSHPULL;
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/* EBI CS0-CS3 */
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gpio->P[3].MODEH |=
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(GPIO_P_MODEH_MODE9_PUSHPULL |
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GPIO_P_MODEH_MODE10_PUSHPULL |
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GPIO_P_MODEH_MODE11_PUSHPULL |
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GPIO_P_MODEH_MODE12_PUSHPULL);
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/* EBI AD0..7 */
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gpio->P[4].MODEH |=
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(GPIO_P_MODEH_MODE8_PUSHPULL |
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GPIO_P_MODEH_MODE9_PUSHPULL |
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GPIO_P_MODEH_MODE10_PUSHPULL |
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GPIO_P_MODEH_MODE11_PUSHPULL |
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GPIO_P_MODEH_MODE12_PUSHPULL |
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GPIO_P_MODEH_MODE13_PUSHPULL |
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GPIO_P_MODEH_MODE14_PUSHPULL |
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GPIO_P_MODEH_MODE15_PUSHPULL);
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/* EBI ARDY/ALEN/Wen/Ren */
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gpio->P[5].MODEL |=
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(GPIO_P_MODEL_MODE2_PUSHPULL |
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GPIO_P_MODEL_MODE3_PUSHPULL |
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GPIO_P_MODEL_MODE4_PUSHPULL |
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GPIO_P_MODEL_MODE5_PUSHPULL);
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/* Configure EBI controller */
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/* 16 bit address, 16 bit data mode */
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/* Enable bank 0 address map 0x80000000, FPGA Flash */
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/* Enable bank 1 address map 0x84000000, FPGA SRAM */
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/* Enable bank 2 address map 0x88000000, FPGA TFT Display (SSD2119) */
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/* Enable bank 3 address map 0x8c000000, FPGA Board Control Registers */
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ebi->CTRL =
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EBI_CTRL_MODE_D16A16ALE |
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EBI_CTRL_BANK0EN |
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EBI_CTRL_BANK1EN |
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EBI_CTRL_BANK2EN |
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EBI_CTRL_BANK3EN;
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/* Setup and hold time */
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ebi->ADDRTIMING = 3 << _EBI_ADDRTIMING_ADDRHOLD_SHIFT | 3 << _EBI_ADDRTIMING_ADDRSET_SHIFT;
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/* Default values for all write timing registers, read timing conservative */
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ebi->RDTIMING = 7 << _EBI_RDTIMING_RDSTRB_SHIFT | 3 << _EBI_RDTIMING_RDHOLD_SHIFT | 3 << _EBI_RDTIMING_RDSETUP_SHIFT;
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ebi->WRTIMING = 7 << _EBI_WRTIMING_WRSTRB_SHIFT | 3 << _EBI_WRTIMING_WRHOLD_SHIFT | 3 << _EBI_WRTIMING_WRSETUP_SHIFT;
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ebi->POLARITY = _EBI_POLARITY_RESETVALUE;
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/* Toggle on all chip selects for all banks */
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ebi->ROUTE =
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EBI_ROUTE_CS0PEN |
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EBI_ROUTE_CS1PEN |
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EBI_ROUTE_CS2PEN |
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EBI_ROUTE_CS3PEN |
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EBI_ROUTE_ALEPEN |
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EBI_ROUTE_EBIPEN;
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}
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/**************************************************************************//**
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* @brief Initialize EBI
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* access
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*****************************************************************************/
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void DVK_EBI_init(void)
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{
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uint16_t ebiMagic;
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int ctr;
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volatile int i;
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/* Configure EBI */
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DVK_EBI_configure();
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/* Verify that EBI access is working, if not kit is in SPI mode and needs to
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* be configured for EBI access */
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ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
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if (ebiMagic != BC_MAGIC_VALUE)
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{
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/* Disable EBI */
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DVK_EBI_disable();
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/* Enable SPI interface */
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DVK_SPI_init();
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/* Set EBI mode - after this SPI access will no longer be available */
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DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
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/* Disable SPI */
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DVK_SPI_disable();
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/* Now setup EBI again */
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DVK_EBI_configure();
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/* Wait until ready */
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ctr = 0;
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do {
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/* Check if FPGA responds */
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ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
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ctr++;
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DVK_EBI_writeRegister(BC_LED, ctr);
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} while (ebiMagic != BC_MAGIC_VALUE);
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}
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}
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/**************************************************************************//**
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* @brief Disable EBI interface, free all GPIO pins
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*****************************************************************************/
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void DVK_EBI_disable(void)
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{
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GPIO_TypeDef *gpio = GPIO;
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EBI_TypeDef *ebi = EBI;
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CMU_TypeDef *cmu = CMU;
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/* Toggle off all chip selects for all banks */
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ebi->ROUTE = _EBI_ROUTE_RESETVALUE;
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/* Disable EBI controller */
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ebi->CTRL = _EBI_CTRL_RESETVALUE;
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/* Disable EBI clock */
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cmu->HFCORECLKEN0 &= ~(CMU_HFCORECLKEN0_EBI);
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/* Disable EBI _BC_BUS_CONNECT */
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gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE12_MASK);
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/* Configure GPIO pins as disabled */
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gpio->P[0].MODEL &= ~(
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_GPIO_P_MODEL_MODE0_MASK |
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_GPIO_P_MODEL_MODE1_MASK |
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_GPIO_P_MODEL_MODE2_MASK |
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_GPIO_P_MODEL_MODE3_MASK |
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_GPIO_P_MODEL_MODE4_MASK |
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_GPIO_P_MODEL_MODE5_MASK |
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_GPIO_P_MODEL_MODE6_MASK);
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gpio->P[0].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
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gpio->P[3].MODEH &= ~(
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_GPIO_P_MODEH_MODE9_MASK|
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_GPIO_P_MODEH_MODE10_MASK|
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_GPIO_P_MODEH_MODE11_MASK|
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_GPIO_P_MODEH_MODE12_MASK
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);
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gpio->P[4].MODEH &= ~(
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_GPIO_P_MODEH_MODE8_MASK |
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_GPIO_P_MODEH_MODE9_MASK |
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_GPIO_P_MODEH_MODE10_MASK |
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_GPIO_P_MODEH_MODE11_MASK |
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_GPIO_P_MODEH_MODE12_MASK |
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_GPIO_P_MODEH_MODE13_MASK |
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_GPIO_P_MODEH_MODE14_MASK |
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_GPIO_P_MODEH_MODE15_MASK);
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gpio->P[5].MODEL &= ~(
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_GPIO_P_MODEL_MODE2_MASK |
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_GPIO_P_MODEL_MODE3_MASK |
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_GPIO_P_MODEL_MODE4_MASK |
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_GPIO_P_MODEL_MODE5_MASK);
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}
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/**************************************************************************//**
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* @brief Write data into 16-bit board control register
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* @param addr Address to board control register
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* @param data Data to write into register
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*****************************************************************************/
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void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data)
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{
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*addr = data;
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}
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/**************************************************************************//**
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* @brief Write data into 16-bit board control register
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* @param addr Register to read from
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*****************************************************************************/
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uint16_t DVK_EBI_readRegister(volatile uint16_t *addr)
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{
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return *addr;
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}
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