Yuhui Zheng fa74f7dccf Removing writes to read-only PLIC interrupt pending registers. ... Signed-off-by: Yuhui Zheng <10982575+yuhui-zheng@users.noreply.github.com>		2020-04-07 10:09:20 -07:00
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.settings	Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant.	2020-01-09 02:28:45 +00:00
blinky_demo	Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.	2020-02-07 20:14:50 +00:00
bsp	Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware.	2020-01-01 22:05:35 +00:00
freedom-metal	Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware.	2020-01-01 22:05:35 +00:00
full_demo	Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.	2020-02-07 20:14:50 +00:00
.cproject	unix separators for path and remove .exe suffix from risc compiler (works on windows/mac)	2020-03-22 20:23:03 -07:00
.project	Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware.	2020-01-01 22:05:35 +00:00
FreeRTOSConfig.h	Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.	2020-02-07 20:14:50 +00:00
main.c	Removing writes to read-only PLIC interrupt pending registers.	2020-04-07 10:09:20 -07:00