FreeRTOS-Kernel/FreeRTOS/Source/portable/GCC/RISC-V
2019-04-29 00:57:14 +00:00
..
chip_specific_extensions Correcting spelling mistakes in comments only. 2019-03-08 17:30:49 +00:00
port.c Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. 2019-04-29 00:57:14 +00:00
portASM.S Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. 2019-04-29 00:57:14 +00:00
portmacro.h Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation. 2019-04-21 20:15:34 +00:00
readme.txt Fix bug in core_cm3.c atomic macros. 2019-02-16 01:08:38 +00:00

/*
 * The FreeRTOS kernel's RISC-V port is split between the the code that is
 * common across all currently supported RISC-V chips (implementations of the
 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
 *
 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
 *   is common to all currently supported RISC-V chips.  There is only one
 *   portASM.S file because the same file is built for all RISC-V target chips.
 *
 * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
 *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
 *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
 *   as there are multiple RISC-V chip implementations.
 *
 * !!!NOTE!!!
 * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
 * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
 * compiler's!) include path.  For example, if the chip in use includes a core
 * local interrupter (CLINT) and does not include any chip specific register
 * extensions then add the path below to the assembler's include path:
 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
 *
 */